Hybrid integrated circuit
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Description
FIG. 1 is a top, front and right side perspective view of our new design for a hybrid integrated circuit;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof; and,
FIG. 7 is a left side elevational view thereof.
Referenced Cited
Patent History
Patent number: D345963
Type: Grant
Filed: Apr 29, 1992
Date of Patent: Apr 12, 1994
Assignee: Sanyo Electric Co., Ltd. (Osaka)
Inventors: Masahito Kanaya (Gunma), Masakazu Ueno (Gunma), Kenichi Kobayashi (Gunma)
Primary Examiner: Wallace R. Burke
Assistant Examiner: Joel Sincavage
Law Firm: Darby & Darby
Application Number: 7/876,211
Type: Grant
Filed: Apr 29, 1992
Date of Patent: Apr 12, 1994
Assignee: Sanyo Electric Co., Ltd. (Osaka)
Inventors: Masahito Kanaya (Gunma), Masakazu Ueno (Gunma), Kenichi Kobayashi (Gunma)
Primary Examiner: Wallace R. Burke
Assistant Examiner: Joel Sincavage
Law Firm: Darby & Darby
Application Number: 7/876,211
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)