Transistor substrate

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Description

FIG. 1 is a front elevational view showing a transistor substrate according to a first embodiment of the present invention;

FIG. 2 is a rear elevational view of the substrate of FIG. 1;

FIG. 3 is a top plan view of the substrate of FIG. 1;

FIG. 4 is a bottom plan view of the substrate of FIG. 1;

FIG. 5 is a right side elevational view of the substrate of FIG. 1, the left side elevational view being a mirror image of the right side elevational view;

FIG. 6 is a top front perspective view of the substrate of FIG. 1;

FIG. 7 is a top plan view showing a transistor substrate according to a second embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment;

FIG. 8 is a top front perspective view of the substrate of FIG. 7;

FIG. 9 is a top plan view showing a transistor substrate according to a third embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment;

FIG. 10 is a top front perspective view of the substrate of FIG. 9;

FIG. 11 is a top plan view showing a transistor substrate according to a fourth embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment; and,

FIG. 12 is a top front perspective view of the substrate of FIG. 11.

Claims

The ornamental design for a transistor substrate, as shown and described.

Referenced Cited
U.S. Patent Documents
D318271 July 16, 1991 Hasegawa et al.
D319629 September 3, 1991 Hasegawa et al.
D350942 September 27, 1994 Pellet et al.
D426522 June 13, 2000 Matsumura
5156983 October 20, 1992 Schlesinger et al.
Patent History
Patent number: D443253
Type: Grant
Filed: Jan 13, 2000
Date of Patent: Jun 5, 2001
Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho (Kariya)
Inventors: Toshiaki Nagase (Kariya), Jun Ishikawa (Kariya)
Primary Examiner: Brian N. Vinson
Attorney, Agent or Law Firm: Morgan & Finnegan, LLP
Application Number: 29/116,954
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;