Process tube for semiconductor device manufacturing apparatus
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Description
FIG. 1 is an isometric view of a process tube for semiconductor device manufacturing apparatus of the present invention;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof;
FIG. 8 is a sectional view along line 8—8 shown in FIG. 6;
FIG. 9 is a sectional view along line 9—9 shown in FIG. 6;
FIG. 10 is a sectional view along line 10—10 shown in FIG. 6; and,
FIG. 11 is a sectional view along line 11—11 shown in FIG. 2.
Claims
The ornamental design for a process tube for semiconductor device manufacturing apparatus, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
5037502 | August 6, 1991 | Suzuki et al. |
5279986 | January 18, 1994 | Maloney et al. |
5352293 | October 4, 1994 | Yang et al. |
5752819 | May 19, 1998 | Hansotte et al. |
D405062 | February 2, 1999 | Shimazu |
6240875 | June 5, 2001 | Van Wijck et al. |
6402849 | June 11, 2002 | Kwag et al. |
2003-209063 | July 2003 | JP |
Patent History
Patent number: D521465
Type: Grant
Filed: Apr 29, 2004
Date of Patent: May 23, 2006
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Katsutoshi Ishii (Tokyo), Hiroyuki Matsuura (Tokyo)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/204,408
Type: Grant
Filed: Apr 29, 2004
Date of Patent: May 23, 2006
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Katsutoshi Ishii (Tokyo), Hiroyuki Matsuura (Tokyo)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/204,408
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)