Wafer-boat for heat-processing of semiconductor wafers
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Description
Claims
The ornamental design for a wafer-boat for heat-processing of semiconductor wafers, as shown and described.
Referenced Cited
U.S. Patent Documents
5219079 | June 15, 1993 | Nakamura |
D361752 | August 29, 1995 | Yamaga |
D404371 | January 19, 1999 | Shimazu |
D409158 | May 4, 1999 | Shimazu |
D411176 | June 22, 1999 | Shimazu |
6065615 | May 23, 2000 | Uchiyama et al. |
D429224 | August 8, 2000 | Ishii |
6488497 | December 3, 2002 | Buckley et al. |
6796439 | September 28, 2004 | Araki |
20020092815 | July 18, 2002 | Kim et al. |
20030010730 | January 16, 2003 | Buckley |
20030024888 | February 6, 2003 | Payne et al. |
20050145584 | July 7, 2005 | Buckley et al. |
Patent History
Patent number: D551634
Type: Grant
Filed: Aug 25, 2005
Date of Patent: Sep 25, 2007
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Kazuyuki Sugawara (Minato-ku)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/236,991
Type: Grant
Filed: Aug 25, 2005
Date of Patent: Sep 25, 2007
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Kazuyuki Sugawara (Minato-ku)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/236,991
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)