Arm for wafer transportation for manufacturing semiconductor
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Description
The broken lines in the drawings form no part of the claimed design.
Claims
The ornamental design for arm for wafer transportation for manufacturing semiconductor, as shown and described.
Referenced Cited
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Patent History
Patent number: D673923
Type: Grant
Filed: Jun 24, 2011
Date of Patent: Jan 8, 2013
Assignee: Tokyo Electron Limited (Minato-Ku)
Inventor: Hideki Kajiwara (Koshi)
Primary Examiner: Selina Sikder
Attorney: Burr & Brown
Application Number: 29/396,042
Type: Grant
Filed: Jun 24, 2011
Date of Patent: Jan 8, 2013
Assignee: Tokyo Electron Limited (Minato-Ku)
Inventor: Hideki Kajiwara (Koshi)
Primary Examiner: Selina Sikder
Attorney: Burr & Brown
Application Number: 29/396,042
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)