Liquid crystal display device and method of driving the same

- Sharp Kabushiki Kaisha

A liquid crystal display device is formed by arranging a plurality of scanning lines 31, 32, . . . to which scanning signals are successively applied and a plurality of signal lines 41, 42, . . . to which data signals are successively applied to intersect at right angles. Mounted in the vicinity of each of the intersections of the scanning lines 31, 32, . . . and signals lines 41, 42, . . . are a TFT 5 electrically connected to both of the lines, and a pixel electrode 6 connected to the TFT 5. A common electrode is placed to face the pixel electrode 6 with liquid crystals 2 therebetween. One of electrodes of a pixel capacitance formed by the pixel electrode 6 is connected to a common line 9 for supplying a common signal to the common electrode 7. A dummy scanning line 30 for forming a capacitance is arranged outside of the scanning line 31 located at the outermost position on a scanning start side of scanning signal. In this structure, since an equal parasitic capacitance is generated in the pixels irrespectively of their positions, it is possible to eliminate defects, such as deterioration of display quality due to an appearance of a bright line in particular pixels.

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Description
FIELD OF THE INVENTION

The present invention relates to an active matrix type liquid crystal display device having switching elements, such as thin film transistors, arranged in a matrix pattern, and a method of driving the liquid crystal display device.

BACKGROUND OF THE INVENTION

As illustrated in FIG. 10, an active liquid crystal display device is constructed by sealing liquid crystals 2 in the space between a pair of upper and lower transparent glass substrates 1b and 1a.

As shown in FIG. 9, formed on the lower substrate 1a are scanning lines 31, 32 . . . , and signal lines 41, 42 . . . intersecting the scanning lines 31, 32 . . . at right angles. The scanning lines 31, 32 . . . are formed by a conducting film, and scanning signals from a scanning drive circuit K are successively applied to the scanning lines 31, 32 . . . On the other hand, the signal lines 41, 42 . . . are formed by a conducting film, and data signals from a data drive circuit L are successively applied to the signal lines 41, 42 . . .

Mounted in the vicinity of each of the intersections of the scanning lines 31, 32 . . . and the signal lines 41, 42 . . . are a thin film transistor (TFT) 5 as a switching element, and a pixel electrode 6 formed by a conducting film. The TFT 5 is electrically connected to both of the lines, and the pixel electrode 6 is connected to the TFT 5.

As shown in FIG. 10, a common electrode 7 and a color filter 8 are mounted on the upper glass substrate 1b. The common electrode 7 is formed by a transparent conducting film and connected to a common line 9 to which a common signal is applied. The pixel electrode 6 and the common electrode 7 form a capacitor 12 for ensuring a liquid crystal capacitance CLC as shown in FIG. 11.

As illustrated in FIG. 9, in the TFT 5, a gate electrode 5g is connected to each of the scanning lines 31, 32 . . . , a source electrode 5s is connected to each of the signal lines 41, 42 . . . , and a drain electrode 5d is connected to the pixel electrode 6.

Moreover, an additional capacitance line 10 formed by a conducting film is arranged below the pixel electrode 6, and connected to the common line 9. Considering an improvement of the data retentivity of the liquid crystals 2 to achieve high image quality, a capacitor 13 for ensuring an additional capacitance Cs is formed by the pixel electrode 6 and the additional capacitance line 10 as shown in FIG. 11.

In the liquid crystal display device of the above-mentioned structure, for example, when scanning signals are successively input downward from the scanning drive circuit K to the scanning lines 31, 32 . . . , the gates of a line of the TFTs 5 are simultaneously turned ON by the input of the scanning signals, and a display-use data signal is input for each pixel from the signal lines 41, 42 . . . by the data drive circuit L. As a result, the data signal is applied to the pixel electrode 6, and the transmittance of the liquid crystals 2 is changed by the potential difference between the pixel electrode 6 and the common electrode 7.

In this case, when a direct current continues to be supplied over a long time, the data retentivity of the liquid crystals 2 deteriorate. Therefore, the liquid crystals 2 are driven by a so-called AC drive method in which a positive voltage and a negative voltage are alternately applied to the pixel electrode 6 by switching the polarity of data signals to be input to the signal lines 41, 42 . . . for example, every horizontal period.

As the ideal capacitance (pixel capacitance) for a single pixel, in general, only the liquid crystal capacitance CLC and the additional capacitance Cs exist between the pixel electrode 6 and the common electrode 7 and between the pixel electrode 6 and the additional capacitance line 10, respectively, as shown in FIG. 11.

Actually, when conducting films are placed parallel to each other or conducting films are placed one upon another with an insulating film therebetween, a parasitic capacitance is generated between the conducting films. For example, as shown in FIG. 15, in a pixel located in the second row and the first column, i.e., a pixel in which the gate of the TFT 5 is connected to the second scanning line from the top, 32, and the source thereof is connected to the first signal line from the left, 41, the periphery of the pixel electrode 6 is enclosed by the upper and lower scanning lines 31 and 32, and the right and left signal lines 41 and 42 as shown in FIG. 9. Therefore, as illustrated in FIG. 12, parasitic capacitances Cgd2, Cgd1, Csd2 and Csd1 are generated between the pixel electrode 6 and the lines 31, 32, 41, 42, respectively.

The parasitic capacitance ratio in this pixel is given by
α=ΔC/(CLC+Cs+ΔC)  (1)
where ΔC=Cgd1+Cgd2.

When driving the liquid crystals 2 by the above-mentioned AC drive method, such a parasitic capacitance ratio α affects the fluctuation ΔV of a voltage applied to the pixel electrode 6, and the voltage fluctuation ΔV generates a DC component, resulting in deterioration of the data retentivity. In order to prevent the generation of the DC component, in prior arts, optimization is performed for each gray scale according to the parasitic capacitance ratio α.

The above explanation of the parasitic capacitance generated in each pixel is given for a pixel whose TFT 5 is connected to the scanning line 32 located in the second row from the top.

Next, with reference to a pixel whose TFT 5 is connected to the topmost scanning line 31 from which the scanning of scanning signal is initiated, the following description will explain a parasitic capacitance generated in this pixel. Since no scanning line is present above the pixel electrode 6 constituting this pixel, the parasitic capacitance Cgd2 is not generated.

Therefore, in this case, the parasitic capacitance ratio is given by
α′=ΔC/(CLC+Cs+ΔC′)  (2)
where ΔC′=Cgd1.

Namely, the parasitic capacitance ratio in the pixels corresponding the scanning lines 32, 33 . . . other than topmost scanning line 31 becomes the parasitic capacitance ratio α given by Equation (1) because these scanning lines are all symmetrically arranged about the additional capacitance line 10 as shown in FIG. 9. However, since the topmost scanning line 31 is not symmetrical about the additional capacitance line 10, the parasitic capacitance ratio in the pixels corresponding to the topmost scanning lines 31 becomes the parasitic capacitance α′ given by Equation (2).

Thus, the parasitic capacitance ratio in the pixels corresponding to the topmost scanning line 31 differs from the parasitic capacitance ratio in the pixels corresponding to the scanning lines 32, 33 . . . located after the first row.

As described above, optimization is performed for the pixels corresponding to the scanning lines 32, 33 . . . after the first row so as to reduce the influence of the parasitic capacitance ratio α and prevent the application of a DC component to the liquid crystals 2.

However, since the parasitic capacitance ratio α′ in the pixels corresponding to the topmost scanning line 31 differs from the parasitic capacitance ratio in the pixels corresponding to other scanning lines, the fluctuation ΔV of the voltage to be applied to the pixel electrodes 6 cannot be eliminated. As a result, an extremely small DC component is applied to the liquid crystals 2 in the pixels corresponding to the first scanning line 31, and therefore the data retentivity of the liquid crystals 2 deteriorate with time.

Consequently, a line of pixels corresponding to the topmost scanning lines 31 may cause a defect, for example, a bright line, deteriorating the display quality. In this case, for example, if the liquid crystals 2 are of normally white type, a bright line appears in the halftone display. On the other hand, if the liquid crystals 2 are of normally black type, a black line appears in the halftone display. Such a phenomenon is particularly noticeable when a current is supplied under high temperatures.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a liquid crystal display device and a drive method thereof, capable of preventing defects such as the deterioration of display quality due to the appearance of particular pixels as a bright line by ensuring an equal parasitic capacitance for pixels of any location.

In order to achieve the above object, a liquid crystal display device of the present invention includes:

    • a pair of substrates sandwiching liquid crystals therebetween;
    • a plurality of scanning lines to which scanning signals are successively applied;
    • a plurality of signal lines to which data signals are successively applied, the signal lines intersecting the scanning lines at right angles;
    • a switching element which is arranged in the vicinity of each of the intersections of the scanning lines and the signal lines, and electrically connected to both of the scanning and signal lines;
    • a pixel electrode connected to each of the switching elements;
    • the scanning lines, signal lines, switching elements and pixel electrodes being formed on one of the substrates,
    • a common electrode formed on the other of the substrates so that the common electrode faces the pixel electrode with the liquid crystals therebetween;
    • a common line for supplying a common signal to the common electrode;
    • a pixel capacitance, one of electrodes of the pixel capacitance formed by the pixel electrode being connected to the common line; and
    • a dummy scanning line formed outside of one of the scanning lines located at an outermost position on either a scanning start side or a scanning end side of scanning signal.

In this liquid crystal display device, an equal parasitic capacitance is formed in any pixels irrespectively of their positions by providing the dummy scanning line. This structure reduces conventional defects caused by unequal parasitic capacitances in the respective pixels, i.e., defects such as the deterioration of display quality due to the appearance of particular pixels as a bright line.

For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the structure of a liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart for inputting signals to a dummy scanning line and scanning lines in the liquid crystal display device shown in FIG. 1.

FIG. 3 is a circuit diagram showing the structure of a liquid crystal display device according to Embodiment 2 of the present invention.

FIG. 4 is a timing chart for inputting signals to a dummy scanning line and scanning lines in the liquid crystal display device shown in FIG. 3.

FIG. 5 is a circuit diagram showing the structure of a liquid crystal display device according to Embodiment 3 of the present invention.

FIG. 6 is a timing chart for inputting common signals to a dummy scanning line in the liquid crystal display device shown in FIG. 5.

FIG. 7 is a timing chart for inputting signals to a dummy scanning line in the liquid crystal display device shown in FIG. 1 according to another example.

FIG. 8 is a graph showing results of examination of the occurrence of a blanking line in the respective embodiments.

FIG. 9 is a plane view showing the structure of a single pixel on a display panel of an active matrix type liquid crystal display device.

FIG. 10 is a cross sectional view of FIG. 9 cut across the A—A′ line.

FIG. 11 is a diagram of an equivalent circuit of a capacitance which is generated in an ideal state in the single pixel shown in FIG. 9.

FIG. 12 is a diagram of an equivalent circuit of a capacitance which is generated in an actual state in the single pixel shown in FIG. 9.

FIG. 13 is a plane view of a single pixel of a liquid crystal display device according to Embodiment 6 of the present invention.

FIG. 14 is a cross sectional view of FIG. 13 cut across the B—B′ line.

FIG. 15 is a circuit diagram showing the structure of a conventional liquid crystal display device.

 DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1]

The following description will discuss one embodiment of the present invention.

In this embodiment, an active matrix type liquid crystal display device will be explained as a liquid crystal display device. The display mode of the liquid crystal display device is a super video graphics array (SVGA) mode. The same can be said for embodiments discussed later.

As illustrated in FIG. 1, the liquid crystal display device includes scanning lines 31, 32, . . . and signal lines 41, 42, . . . intersecting the scanning lines 31, 32, . . . at right angles. The scanning lines 31, 32, . . . are formed by a conducting film. Scanning signals from a scanning signal drive circuit K are successively applied to the scanning lines 31, 32, . . . On the other hand, the signal lines 41, 42, . . . are formed by a conducting film. Data signals from a data drive circuit L are successively applied to the signal lines 41, 42, . . .

Disposed in the vicinity of the intersections of the scanning lines 31, 32, . . . and signal lines 41, 42, . . . are thin film transistors (TFTs) 5 as switching elements which are electrically connected to both of the lines, and pixel electrodes 6 which are formed by a conducting film and connected to the TFTs 5.

A dummy scanning line 30 for producing a capacitance is arranged outside of the scanning lines 31, 32, . . . i.e., outside of the outermost scanning line 31 arranged at a scanning start position from which the scanning of scanning signal starts. The dummy scanning line 30 is parallel to and faces the scanning line 31 with the pixel electrode 6 connected to the TFT 5 connected to the scanning line 31 therebetween.

More specifically, the dummy scanning line 30 is arranged at the same pitch as the pitch of other adjacent scanning lines, for example, 31 and 32, so that the pixel electrode 6 is located between the dummy scanning line 30 and the scanning line 31. The dummy scanning line 30 will be explained in detail later.

The pixel electrode 6 is formed by a transparent conducting film, aluminum, etc. For example, as illustrated in FIG. 9, an additional capacitance line 10 formed by a conducting film is arranged below the pixel electrode 6. A common line 9 is connected to the additional capacitance line 10. FIG. 10 is a cross sectional view showing the vicinity of the junction of the pixel electrode 6 and the TFT 5.

As illustrated in FIG. 10, the above-mentioned liquid crystal display device is constructed by sealing in liquid crystals 2 between a pair of upper and lower transparent glass substrates 1b and 1a.

Formed on the lower glass substrate 1a are a gate electrode 5g of the TFT 5, and a gate insulating film 20 covering the gate electrode 5g.

An i layer 22 and an n+ layer 23 are successively formed by amorphous Si on the gate insulating film 20 at the position corresponding to the gate electrode 5g. Formed on the n+ layer 23 of amorphous Si are a source electrode 5s and a drain electrode 5d of the TFT 5. The pixel electrode 6 is formed in a pixel region on the gate insulating film 20. The pixel electrode 6 is connected to the drain electrode 5d.

Namely, in the TFTs 5, the gate electrodes 5g are connected to the scanning lines 31, 32, . . . , the source electrodes 5s are connected to the signal lines 41, 42, . . . , and the drain electrodes 5d are connected to the pixel electrodes 6.

On the other hand, a color filter 8 and a common electrode 7 are successively formed on the upper glass substrate 1b. The common line 9 (FIG. 1) to which a common signal is applied is connected to the common electrode 7. The color filter 8 is made of three primary colors, red, green and blue, and placed in a position corresponding to each pixel electrode 6.

An alignment film (not shown) for aligning the liquid crystals 2 is formed to cover the pixel electrode 6. Similarly, on the upper glass substrate 1b, an alignment film (not shown) is formed to cover the common electrode 7.

Further, a polarizing plate (not shown) is mounted on outer surfaces of the glass substrates 1a and 1b, i.e., surfaces which do not come into contact with the liquid crystals 2.

Capacitors 12 and 13 as pixel capacitances are formed by the pixel electrode 6, and the opposite common electrode 7 and additional capacitance line 10, respectively. More specifically, as illustrated in FIG. 11, the capacitor 12 is formed by the pixel electrode 6 and the common electrode 7 to ensure a liquid crystal capacitance CLC. In order to achieve high image quality by improving the data retentivity of the liquid crystals 2, the capacitor 13 is formed by the pixel electrode 6 and the additional capacitance 10 to ensure an additional capacitance Cs.

In the liquid crystal display device of the above-mentioned structure, when scanning signals are successively input downward from the scanning drive circuit K to the scanning lines 31, 32, . . . , the gates of a line of the TFTs 5 are simultaneously turned on, and display-use data signals are input to the signal lines 41, 42, . . . for each pixel by the data drive circuit L. As a result, the data signals are input to the pixel electrodes 6, and the transmittance of the liquid crystals 2 is varied by the potential difference between the pixel electrodes 6 and the common electrodes 7.

In this case, when a direct current continues to be supplied over a long time, the data retentivity of the liquid crystals 2 deteriorates. Therefore, the liquid crystals 2 are driven by a so-called AC drive method in which a positive voltage and a negative voltage are alternately applied to the pixel electrode 6 by switching the polarity of the data signals to be input to the signal lines 41, 42, . . . , for example, every horizontal scanning period.

In general, as an ideal capacitance (pixel capacitance) of a single pixel, only the liquid crystal capacitance CLC and the additional capacitance CS exist between the pixel electrode 6 and the common electrode 7 and between the pixel electrode 6 and the additional capacitance line 10, respectively, as shown in FIG. 11.

However, in actual fact, when conducting films are arranged parallel to each other, or the conducting films are placed one upon another with an insulating film therebetween, a parasitic capacitance is generated between the conducting films.

Therefore, for example, in a pixel located in the second row and the first column, i.e., a pixel in which the gate electrode 5g of the TFT 5 is connected to the second scanning line from the top, 32, and the source electrode 5s is connected to the first signal line from the left, 41, the periphery of the pixel electrode 6 is enclosed by the upper and lower scanning lines 31 and 32, and the left and right signal lines 41 and 42 as shown in FIG. 9. Thus, in this pixel, as shown in FIG. 12, parasitic capacitances Cgd2, Cgd1, Csd2, and Csd1 are generated between the pixel electrode 6 and the lines 31, 32, 41, and 42, respectively, as well as the liquid crystal capacitance CLC and the additional capacitance Cs.

The parasitic capacitance ratio in this pixel is given by
α=ΔC/(CLC+Cs+ΔC)  (1)
where ΔC=Cgd1+Cgd2.

When driving the liquid crystals 2 by the above-mentioned AC drive method, the parasitic capacitance ratio α affects a fluctuation ΔV of a voltage applied to the pixel electrode 6, and the voltage fluctuation ΔV produces a DC component and deteriorates the data retentivity. Therefore, optimization is performed for each gray scale according to the parasitic capacitance ratio α so as to prevent the generation of the DC component.

Next, with reference to a pixel in which the gate electrode 5g of the TFT 5 is connected to the topmost scanning line, 31, shown in FIG. 1 from which the scanning of scanning signal starts and the source electrode 5s is connected to the first signal line, 41, from the left, a parasitic capacitance ratio α′ in this pixel will be discussed.

Since the dummy scanning line 30 is arranged above the pixel electrode 6 constituting this pixel at the same pitch as the pitch of other adjacent scanning lines, for example, 31 and 32 so that the pixel electrode 6 is located between the dummy scanning line 30 and the scanning line 31, Ggd2 is generated between the pixel electrode 6 and the dummy electrode 30 in the same manner as the above-mentioned parasitic capacitance generated between the pixel electrode 6 and the scanning line 31.

Thus, the parasitic capacitance ratio in this pixel is given by
α′=ΔC′/(CLC+Cs+ΔC′)  (2)
where ΔC′=Cgd1+Cgd2=ΔC.

Therefore, α′=ΔC/(CLC+Cs+ΔC)=α.

Namely, the pixel electrode 6 connected to the TFT 5 connected to the topmost scanning line 31 is sandwiched between the dummy scanning line 30 above and the scanning line 31 below. As a result, since all of the pixels are geometrically symmetrical about the additional capacitance line 10 as shown in FIG. 9, the parasitic capacitance ratio in all of the pixels becomes α given by Equation (1) above, thereby preventing different parasitic capacitance ratios which are seen in a conventional structure.

Moreover, in this embodiment, a scanning signal G0 having the same waveform and the same time difference ΔT as normal scanning signals G1, G2, G3, . . . to be input to the scanning lines 31, 32, . . . , by the scanning drive circuit K is newly generated as shown in FIG. 2. The scanning signal G0 is applied to the dummy scanning line 30 before an output of the scanning signal G1 to be applied to the topmost scanning line 31. Hence, a part of the scanning drive circuit K forms signal input means for inputting a signal to the dummy scanning line 30.

Thus, by performing optimization in advance according to the parasitic capacitance ratio α, the pixel driven by the topmost scanning line 31 has completely the same conditions as the pixels driven by other scanning lines 32, 33, . . . Therefore, in the case of a normally white display, it is possible to completely eliminate such a conventional phenomenon that a line of pixels in the topmost row appears as a bright line.

It is arranged in this embodiment that the scanning of scanning signal starts from the topmost scanning line 31. However, if the scanning of scanning signal is arranged to start from the lowest scanning line, 3i, the topmost scanning line 31 becomes the outermost scanning line on the scanning end side of scanning signal. Thus, the dummy scanning line 30 can be formed at the outermost position on either the scanning start side or the scanning end side of scanning signal.

The following description will discuss the rate of occurrence of bright line in the liquid crystal display device of the above-mentioned structure.

With respect to the halftone display of a line of pixels corresponding to the topmost scanning line 31, the rate of occurrence of bright line (relative value) was measured after continuously supplying a current under a temperature of 60° C. for 6 hours and 240 hours. In FIG. 8, the block bar graph represents the rate of occurrence of bright line measured when 6 hours elapsed, while the white bar graph shows the value measured when 240 hours elapsed.

In this case, the rate of occurrence of bright line measured when six hours elapsed after successively inputting scanning signals G1, G2, . . . to the scanning lines 31, 32, . . . without inputting any signal to the dummy scanning line 30, was indicated as a reference value, 100.

In FIG. 8, (A) indicates the result obtained when the scanning signal G0 inherent in the dummy scanning line 30 was input. (D) shows the result obtained when no signal was input to the dummy scanning line 30.

It was found from these results that, when the scanning signal G0 shown in FIG. 2 was input to the dummy scanning line 30, such a phenomenon that only the topmost line appears as a bright line did not occur at all on the contrary to the case in which any signal was not input to the dummy scanning line 30.

However, when the dummy scanning line 30 is not provided though this structure is not shown in FIG. 8, since the parasitic capacitance ratio certainly varies, the rate of occurrence of bright line becomes much higher than that in the above-mentioned case, (D), in which the dummy scanning line 30 is just provided. It was thus found that, even if a signal is not input to the dummy scanning line 30, the rate of occurrence of bright line can be lowered to some degrees by just providing the dummy scanning line 30.

[Embodiment 2]

The following description will discuss another embodiment of the present invention. The members having the same function as in Embodiment 1 above will be designated by the same code and their description will be omitted.

Like Embodiment 1, in a liquid crystal display device of this embodiment, as shown in FIG. 3, the dummy scanning line 30 for forming a capacitance is arranged outside of the topmost scanning line, 31 on the scanning start side of scanning signal so that the pixel electrode 6 connected to the TFT 5 connected to the scanning line 31 is located between the dummy scanning line 30 and the scanning line 31.

However, in this embodiment, unlike Embodiment 1 above, the dummy scanning line 30 is connected to the lowest scanning line, 3i, through a coupling line 14. As a result, as shown in FIG. 4, a scanning signal Gi output to the lowest scanning line 3i from the scanning drive circuit K is directly input to the dummy scanning line 30 through the coupling line 14.

In this case, since the scanning signal G0 input to the dummy scanning line 30 is the scanning signal Gi output to the scanning line 3i, the scanning signal G0 certainly has the same waveform and the same time difference ΔT as the normal scanning signals G1, G2, G3, . . . input to the scanning lines 31, 32, . . . by the scanning drive circuit K. Consequently, there is no need to newly generate the scanning signal G0 to be input to the dummy scanning line 30. Namely, the scanning drive circuit K functions as the signal input means for inputting a signal to the dummy scanning line 30.

Therefore, in this structure, unlike Embodiment 1, the existent scanning signal Gi can be used without newly generating the scanning signal G0 inherent in the dummy scanning line 30 by changing a part of the scanning drive circuit K. Moreover, since the time difference between the output of the scanning signal Gi and the output of the scanning signal G1 to be applied to the topmost scanning line 31 is the smallest, the pixels driven by the topmost scanning line 31 have substantially the same conditions as the pixels driven by other scanning lines 32, 33, . . . , thereby reducing defects, such as the phenomenon in which a line of pixels appear as a bright line, to a sufficient level.

Thus, when the scanning signal Gi to be applied to the lowest scanning line 3i is input to the dummy scanning line 30, as shown in (A) of FIG. 8, the rate of occurrence of bright line becomes zero. This means that the phenomenon in which only the topmost line appears as a bright line is completely eliminated.

However, in this embodiment, since the display mode of the liquid crystal display device is the SVGA mode, the vertical blanking period is about 10% of one field. Therefore, the output of a scanning signal to each scanning line is shifted from each other by about one tenth of a field as shown in FIG. 4.

[Embodiment 3]

The following description will discuss still another embodiment of the present invention. The members having the same function as in Embodiment 1 will be designated by the same code and their description will be omitted.

Like Embodiment 1 above, in a liquid crystal display device of this embodiment, as shown in FIG. 5, the dummy scanning line 30 for forming a capacitance is arranged outside of the topmost scanning line, 31, on the scanning start side of scanning signal so that the pixel electrode 6 connected to the TFT 5 connected to the scanning line 31 is placed between the dummy scanning line 30 and the scanning line 31.

However, in this embodiment, unlike Embodiment 1, the dummy scanning line 30 is connected to the common line 9 through a coupling line 15. As a result, as shown in FIG. 6, a common signal Vcom to be applied to the common line 9 is directly input to the dummy scanning line 30 through the coupling line 15. Namely, means for generating the common signal Vcom functions as the signal input means for inputting a signal to the dummy scanning line 30.

More specifically, since the common signal Vcom which switches its level every horizontal scanning period (1H) is input through the common line 9 to the common electrode 7 and the additional capacitance line 10 in order to drive the liquid crystals 2 by the AC drive method, the common signal Vcom is simultaneously input to the scanning lines and the dummy scanning line 30.

Therefore, in this structure, the existent common signal Vcom can be used without newly generating the scanning signal G0 inherent in the dummy scanning line 30 by changing a part of the scanning drive circuit K like Embodiment 1.

Moreover, the rate of occurrence of bright line when the common signal Vcom (see FIG. 6) was input to the dummy scanning line 30 is the one shown in (C) of FIG. 8. It was found from this result that, when the common signal Vcom is input to the dummy scanning line 30, the rate of occurrence of bright line can be reduced to about a half of the rate (shown in (D) of FIG. 8) measured when any signal was not input to the dummy scanning line 30.

[Embodiment 4]

The following description will discuss yet another embodiment of the present invention. In this embodiment, a liquid crystal display device having the same circuit structure as in Embodiment 1 is used.

In this embodiment, as shown in FIG. 7, the scanning signal G0 of a low level that cannot turn on the TFT 5, for example, in a range of −7.5 V to −2.5 V, is input to the dummy scanning line 30. This low level scanning signal G0 is generated in the scanning drive circuit K. Namely, means for inputting a signal to the TFT 5 functions as the signal input means for inputting a signal to the dummy scanning line 30.

Therefore, the rate of occurrence of bright line when the scanning signal G0 shown in FIG. 7 was input to the dummy scanning line 30 is the one shown in (B) of FIG. 8. It was found from this result that, when the scanning signal G0 is input to the dummy scanning line 30, the rate of occurrence of bright line can be reduced to about a half of the rate (shown in (D) of FIG. 8) measured when any signal was not input to the dummy scanning line 30.

[Embodiment 5]

The following description will discuss another embodiment of the present invention. In this embodiment, a liquid crystal display device having the same circuit structure as in Embodiment 1 is used.

In this embodiment, in the above-mentioned liquid crystal display device, any one of the scanning signals to be input to the scanning lines 31, 32, . . . is input as the scanning signal G0 to the dummy scanning line 30. In this case, like Embodiment 2, the scanning drive circuit K functions as the signal input means for inputting a signal to the dummy scanning lines 30.

For example, the rate of occurrence of bright line was measured when the scanning signal G2 to be input to the scanning line 32 in the second row was input as the scanning signal G0 to the dummy scanning line 30. It was found from this result that the rate of occurrence of bright line becomes zero as shown in (A) of FIG. 8. Namely, a phenomenon in which only the topmost line appears as a bight line is completely eliminated.

[Embodiment 6]

The following description will discuss another embodiment of the present invention. The members having the same function as in Embodiment 1 above will be designated by the same code and their description will be omitted.

Unlike the liquid crystal display device of Embodiment 1, in a liquid crystal display device of this embodiment, as shown in FIG. 13, the pixel electrode 6 is formed so that the pixel electrode 6 partly overlaps the dummy scanning line 30, the scanning line 31, the signal lines 41 and 42.

For example, as illustrated in FIG. 14, an inter-layer insulating film 21 is formed by an insulating resin or the like to cover the TFT 5 on the lower glass substrate 1a, the scanning line connected to the gate electrode 5g of the TFT 5, and the signal line connected to the source electrode 5s of the TFT 5. A contact hole 21a is formed in the inter-layer insulating film 21 at a position corresponding to the drain electrode 5d of the TFT 5.

The pixel electrode 6 is formed on the inter-layer insulating film 21 so that the pixel electrode 6 is electrically connected to the drain electrode 5d of the TFT 5 through the contact hole 21a, and partly overlaps the dummy scanning line 30, the scanning line 31, the signal lines 41 and 42. Similarly, the pixel electrodes 6 connected in the vicinity of the intersections of other scanning lines and signal lines partly overlap the dummy scanning lines, the scanning lines and the signal lines.

By forming the inter-layer insulating film 21 on the dummy scanning line 30, the scanning lines 31, . . . and the signal lines 41, 42, . . . and successively forming the pixel electrodes 6 on the inter-layer insulating film 21 so that the pixel electrodes 6 overlap the respective lines, it is possible to increase the aperture ratio and reduce alignment defects of liquid crystals, resulting in improved quality.

Moreover, in the structure in which the pixel electrodes 6 overlap the respective lines, the parasitic capacitance between a pixel and adjacent scanning line is increased to a value which is about twice that of a structure having no inter-layer insulating film 21, i.e., a structure in which the pixel electrodes 6 do not overlap the respective lines (for example, the structure shown in FIG. 9), and defects, such as the phenomenon in which the topmost scanning line 31 appears as a bright line, tend to increase.

However, in this embodiment, the dummy scanning line 30 is arranged outside of the topmost scanning line, 31, parallel to the scanning line 31, and the pixel electrode 6 overlaps the dummy scanning line 30 with the inter-layer insulating film 21 therebetween. Therefore, even if the parasitic capacitance is increased to a value which is about twice that of the structure shown in FIG. 9, all of the pixels are geometrically symmetrical about the additional capacitance line 10. As a result, the parasitic capacitance ratio is equalized in all of the pixels, thereby certainly preventing defects, such as the occurrence of bright line due to different parasitic capacitance ratios.

Thus, in the liquid crystal display device of this embodiment, it is possible to increase the aperture ratio, restrain the alignment defects of liquid crystals, reduce the occurrence of defects such as the appearance of bright line, and achieve improved quality.

In addition, the rate of occurrence of bright line can further be reduced by inputting some signal to the dummy scanning line 30 of the liquid crystal display device of the above-mentioned structure. For instance, by inputting the scanning signal G0 shown in FIG. 2 of Embodiment 1, it is possible to completely prevent the occurrence of bright line. Even when the scanning signal G0 described in other embodiment is input, it is possible to completely prevent or reduce the occurrence of bright line.

In the above-mentioned embodiments, 1 to 6, a line of pixels corresponding to the topmost scanning line 31 may be hidden with a light blocking pattern, instead of providing the dummy scanning line 30, so as to prevent this line of pixels from affecting the display. However, in this state, if a current continues to be supplied over a long time, the appearance of bright line in the first row may gradually spread to the second row. Thus, this structure is not an appropriate measure to prevent the defects.

Therefore, in the structure where the first line of pixels is shaded from light, if the dummy scanning line 30 is provided like the present invention, it is possible to prevent the second line of pixels from appearing as a bright line.

Furthermore, in Embodiments 1 to 6, the dummy scanning line 30 is arranged outside of the topmost scanning line 31. However, the present invention is not limited to this structure. For instance, when the scanning of scanning signal starts from the lowest scanning line 3i, a dummy scanning line 3i+1 is arranged outside of the lowest scanning line 3i.

In the liquid crystal display device of the present invention, an inter-layer insulating film covering the top of switching elements, scanning lines and signal lines is formed, and pixel electrodes are formed so that the pixel electrodes overlap the dummy scanning line and the adjacent scanning line corresponding to the pixel electrodes with the inter-layer insulating film therebetween.

Consequently, since the aperture ratio is improved and the alignment defect of liquid crystals is reduced as described above, it is possible to achieve a highly reliable liquid crystal display device.

Moreover, a drive method of the liquid crystal display device of the present invention includes the step of inputting a signal to the dummy scanning line formed outside of the outermost scanning line on either the scanning start side or the scanning end side of scanning signal.

Thus, by providing a dummy scanning line and inputting a signal to the dummy scanning line, the symmetry of the scanning line located on the outermost position on the scanning start side of scanning signal and the dummy scanning line about the additional capacitance line and the symmetry of other adjacent scanning lines about the additional capacitance line are substantially equalized, thereby ensuring higher display quality.

Additionally, the liquid crystal display devices of Embodiments 1 to 6 have a so-called Cs on Com structure in which the additional capacitance Cs between the pixel electrode 6 and the additional capacitance line 10 is formed on the common line 9. Hence, such a liquid crystal display device can be easily driven. Furthermore, in the Cs on Com structure, since the parasitic capacitance between the gate and source lines is reduced, it is possible to decrease shadowing (particularly in a lateral direction (scanning direction)). Consequently, the present invention can achieve a liquid crystal display device which is easily driven and has high display quality as well as the effect (an improvement of reliability) produced by the above-mentioned dummy scanning line.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

1. A liquid crystal display device comprising:

a pair of substrates sandwiching liquid crystals therebetween;
a plurality of scanning lines to which scanning signals are successively applied;
a plurality of signal lines to which data signals are successively applied, said signal lines intersecting said scanning lines at right angles;
a switching element which is arranged in a vicinity of each of intersections of said scanning lines and said signal lines, and electrically connected to both of said scanning and signal lines;
a pixel electrode connected to each of said switching elements;
said scanning lines, signals lines, switching elements and pixel electrodes being formed on one of said substrates,
a common electrode formed on the other of said substrates so that said common electrode faces said pixel electrode with said liquid crystals therebetween;
a common line for supplying a common signal to said common electrode;
a pixel capacitance, one of electrodes of said pixel capacitance formed by said pixel electrode being connected to said common line; and
a dummy scanning line formed outside of one of said scanning lines located at an outermost position on either a scanning start side or a scanning end side of scanning signal, for producing a parasitic capacitance between said dummy scanning line and the pixel electrode connected to the scanning line located at the outermost position.

2. The liquid crystal display device according to claim 1,

wherein said dummy scanning line is arranged at a pitch equal to a pitch of other adjacent scanning lines so that said pixel electrode is located between said dummy scanning line and the scanning line located at the outermost position.

3. The liquid crystal display device according to claim 1,

wherein an inter-layer insulating film is formed over said switching elements, scanning lines and signal lines, and
each of said pixel electrodes overlaps said dummy scanning line and adjacent scanning line corresponding to said pixel electrode with said inter-layer insulating film therebetween.

4. The liquid crystal display device according to claim 1, further comprising signal input means for inputting a signal to said dummy scanning line.

5. The liquid crystal display device according to claim 4,

wherein said signal input means inputs a signal to said dummy scanning line before an output of a scanning signal to be input to the scanning line located at the outermost position on the scanning start side of scanning signal.

6. The liquid crystal display device according to claim 4,

wherein said signal input means inputs a signal to said dummy scanning line after an output of a scanning signal to be input to the scanning line located at the outermost position on the scanning end side of scanning signal.

7. The liquid crystal display device according to claim 4,

wherein said signal input means inputs a scanning signal generated exclusively for said dummy scanning line to said dummy scanning line.

8. The liquid crystal display device according to claim 4,

wherein said signal input means inputs to said dummy scanning line a scanning signal to be input to the scanning line located at the outermost position on either the scanning start side or the scanning end side of scanning signal.

9. The liquid crystal display device according to claim 4,

wherein said signal input means inputs to said dummy scanning line the common signal to be input to said common electrode.

10. The liquid crystal display device according to claim 4,

wherein said signal input means inputs to said dummy scanning line a scanning signal of a level which does not turn on said switching elements formed on said substrate.

11. A method of driving a liquid crystal display device including a plurality of scanning line to which scanning signals are successively applied, a plurality of signal lines to which data signals are successively applied, a switching element which is arranged in a vicinity of each of intersections of the scanning lines and the signal lines and connected to both of the scanning and signal lines, a pixel electrode connected to each of the switching element, a pixel capacitance formed by the pixel electrode, a common electrode which is arranged to face the pixel electrode, liquid crystals placed between the pixel electrode and the common electrode, and a dummy scanning line formed outside of one of the scanning lines located at an outermost position on either a scanning start side or a scanning end side of scanning signal to produce a parasitic capacitance between the dummy scanning line and the pixel electrode connected to the scanning line located at the outermost position, said method comprising the steps of:

supplying the scanning signal and the data signal to the switching element and supplying a common signal to one of electrodes of the pixel capacitance so as to change an electric potential between the pixel electrode and the common electrode and vary a transmittance of the liquid crystals; and
inputting a signal to the dummy scanning line.

12. The method of driving the liquid crystal display device according to claim 11,

wherein the signal to be input to the dummy scanning line is output before an output of a scanning signal to be input to the scanning line located at the outermost position on the scanning start side of scanning signal.

13. The method of driving the liquid crystal display device according to claim 11,

wherein the signal to be input to the dummy scanning line is output before an output of a scanning signal to be input to the scanning line located at the outermost position on the scanning end side of scanning signal.

14. The method of driving the liquid crystal display device according to claim 11,

wherein the signal to be input to the dummy scanning line is a scanning signal generated exclusively for the dummy scanning line.

15. The method of driving the liquid crystal display device according to claim 11,

wherein the signal to be input to the dummy scanning line is a scanning signal to be input to the scanning line located at the outermost position on either the scanning start side or the scanning end side of scanning signal.

16. The method of driving the liquid crystal display device according to claim 11,

wherein the signal to be input to the dummy scanning line is the common signal to be applied to the common electrode.

17. The method of driving the liquid crystal display device according to claim 11,

wherein the signal to be input to the dummy scanning line is a scanning signal of a level which does not turn on the switching elements.

18. A pair of substrates sandwiching liquid crystals therebetween;

a plurality of scanning lines to which scanning signals are successively applied;
a plurality of signal lines to which data signals are successively applied, said signal lines intersecting said scanning lines at right angles;
a switching element which is arranged in a vicinity of each of intersections of said scanning lines and said signal lines, and electrically connected to both of said scanning and signal lines;
a pixel electrode connected to each of said switching elements;
said scanning lines, signal lines, switching elements and pixel electrodes being formed on one of said substrates,
a common electrode formed on the other of said substrates so that said common electrode faces said pixel electrode with said liquid crystals therebetween; a common line to which a common signal is applied;
a pixel capacitance, one of electrodes of said pixel capacitance being connected to said common line; and
a dummy scanning line formed outside of one of said scanning lines located at an outermost position on either a scanning start side or a scanning end side of scanning signal, for producing a parasitic capacitance between said dummy scanning line and the pixel electrode connected to the scanning line located at the outermost position.

19. The liquid crystal display device according to claim 18,

wherein said dummy scanning line is arranged at a pitch equal to a pitch of other adjacent scanning lines so that said pixel electrode is located between said dummy scanning line and the scanning line located at the outermost position.

20. The liquid crystal display device according to claim 18,

wherein an inter-layer insulating film is formed over said switching elements, scanning lines and signal lines, and
each of said pixel electrodes overlaps said dummy scanning line and adjacent scanning line corresponding to said pixel electrode with said inter-layer insulating film therebetween.

21. The liquid crystal display device according to claim 18, further comprising signal input means for inputting a signal to said dummy scanning line.

22. The liquid crystal display device according to claim 21,

wherein said signal input means inputs a signal to said dummy scanning line before an output of a scanning signal to be input to the scanning line located at the outermost position on the scanning start side of scanning signal.

23. The liquid crystal display device according to claim 21,

wherein said signal input means inputs a signal to said dummy scanning line after an output of a scanning signal to be input to the scanning line located at the outermost position on the scanning end side of scanning signal.

24. The liquid crystal display device according to claim 21,

wherein said signal input means inputs a scanning signal generated exclusively for said dummy scanning line to said dummy scanning line.

25. The liquid crystal display device according to claim 21,

wherein said signal input means inputs to said dummy scanning line a scanning signal to be input to the scanning line located at the outermost position on either the scanning start side or the scanning end side of scanning signal.

26. The liquid crystal display device according to claim 21,

wherein said signal input means inputs to said dummy scanning line the common signal to be input to said common electrode.

27. The liquid crystal display device according to claim 21,

wherein said signal input means inputs to said dummy scanning line a scanning signal of a level which does not turn on said switching elements formed on said substrate.
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Other references
  • First Preliminary Pleading by Obligor in Tokyo District Court Civil 46th Section, Creditor: Sharp Kabushiki Kaisha; Obligor: Iyama Co., Ltd., Sep. 24, 2002 and translation thereof.
  • Otu Document 16, In Tokyo District Court, Civil 46th Section, Second Copy, Aug. 26, 2002 and translation thereof.
  • Second Pleading by Defendants in Tokyo District Court Civil 46th Section, Claimant: Sharp Kabushiki Kaisha; Defendants: Iyama Co., Ltd. and one other, Dec. 13, 2002.
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  • Defendants' Reference 37 in Tokyo District Court 46th Section, Dec. 5, 2002 (Product Analysis Report).
  • English Translation of Second Pleading by Defendants in Tokyo District Court Civil 46th Section, Claimant: Sharp Kabushiki Kaisha; Defendants: Iyama Co., Ltd. and one other, Dec. 13, 2002.
  • English Translation of Defendants' Reference 36 in Tokyo District Court Civil 46th Section, Dec. 5, 2002.
Patent History
Patent number: RE40771
Type: Grant
Filed: Feb 2, 2001
Date of Patent: Jun 23, 2009
Assignee: Sharp Kabushiki Kaisha (Osaka)
Inventors: Shinya Tanaka (Matsuzaka), Takayuki Shimada (Yamatokoriyama), Takashi Ochi (Tenri), Yuzuru Kanemori (Yamatokoriyama), Mikio Katayama (Nara)
Primary Examiner: Vijay Shankar
Attorney: Nixon & Vanderhye, P.C.
Application Number: 09/773,870