Abstract: Bi-state ferroelectric-MOS (FMOS) capacitors are adapted for use in memory cells of a memory device. Bi-state ferroelectric memory cells have a bottom plate of a capacitor coupled to a first source/drain region of a pass transistor, a gate of the pass transistor coupled to a word line, and a second source/drain region of the pass transistor coupled to a bit line. A plate line is coupled to the top plate of the capacitor to facilitate programming of the polarization state of a ferroelectric portion of the capacitor. The polarization state of the ferroelectric portion of the capacitor causes a depletion or accumulation of electrons in the bottom plate of the capacitor, thus altering its capacitance value. The resulting capacitance value may be sensed without causing a polarization reversal of the ferroelectric portion of the capacitor. Accordingly, bi-state ferroelectric memory cells of the various embodiments function as non-volatile memory cells.

Abstract: An integrated cell for extracting a binary value based on a value difference between two resistors values, comprising: connection means for a binary reading of the sign of the difference between said resistors; and connection means for a modification of the value of one of said resistors to make said sign of the difference invariable.

Abstract: A folded bitline type sense amplifier circuit is disposed at an outer side of an end memory cell array in which 2Tr1C type cells each composed of a data storage capacitor, an A port access transistor and a B port access transistor are arranged in the form of a matrix, and two word lines used for cell selection are connected to corresponding gates of the A and B port access transistors. The drain of the A port access transistor is connected to one bit line of an open bitline type sense amplifier circuit, and the drain of the B port access transistor is connected to one bit line out of a bit line pair of the folded bitline sense amplifier circuit.

Abstract: A magnetic switching element includes: a ferromagnetic layer which is substantially pinned in magnetization in one direction; and a magnetic semiconductor layer provided within a range where a magnetic field from the ferromagnetic layer reaches, where the magnetic semiconductor layer changes its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto, and a magnetization corresponding to the magnetization of the ferromagnetic layer is induced in the magnetic semiconductor layer by applying a voltage to the magnetic semiconductor layer.

Abstract: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell array. Bit lines are each coupled to drains of the memory cells which are arranged on a corresponding one of the columns in the memory cell array. An external voltage is supplied from the exterior to an external voltage input terminal. A first voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the word line coupled to the control gates. A second voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the bit line coupled to the drains.

Abstract: If forward write is performed to a nonvolatile memory cell, a switch signal output circuit outputs a switch signal to a plurality of switch circuits. As a result, corresponding potentials are supplied to a plurality of bit lines, respectively. A potential supply circuit supplies a write potential and a ground potential to the corresponding bit lines, respectively. Therefore, this nonvolatile semiconductor memory device can suppress an unnecessary current generated during data write.

Abstract: At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register.

Abstract: Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.

Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract: The number of times of rewriting of memory cells is stored by number of rewrite (EW) times storage section. In data rewriting to memory cells, number of rewriting times data of a selected memory cell is transferred to and latched in a number of EW times sense latch section and transferred to a number of EW times counter. Controlling processor (CPU) sets a condition on a write pulse on the basis of a value obtained by updating a count value of the number of EW times counter and controls the operation of rewriting. In data rewriting, a count value after update of the number of EW times counter is transferred to the number of EW times sense latch section. The updated number of rewritings is transferred to a corresponding number of EW times storage section, in parallel to data rewriting to a memory cell. With such a construction, rewrite time of a non-volatile semiconductor memory device can be reduced and degradation in reliability of a tunnel insulating film of a non-volatile memory cell can be suppressed.

Abstract: A semiconductor nonvolatile memory in which read operations are carried out during write operations, includes: a core having a plurality of cell transistors for storing data; and a write verify circuit for detecting change in a core cell transistor's characteristic during a write operation in which the gate voltage/drain current characteristic of the cell transistor is changed to a condition corresponding to stored data by injecting a charge into or extracting a charge from the core cell transistor; and further includes a write verify inhibition signal generation circuit for generating a write verify inhibition signal in order to deactivate the write verify circuit during a read operation to the core cell transistor. The generation of a mistaken verify decision by the write verify circuit, due to a change in the power supply potential accompanying large current during a read operation, is prevented, as is malfunction of the write verify.

Abstract: An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: An input/output buffer circuit is capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to a halt. The input/output buffer circuit has an input/output terminal (10) for performing the input/output of data. When a write enable signal WR is in an active state, the input/output buffer circuit outputs a signal to the input/output terminal (10). When a read enable signal RD is in an active state, the input/output buffer circuit receives data from the input/output terminal (10). When the write enable signal RD and the read enable signal WR are both in a non-active state, the input/output buffer circuit outputs a signal based on any of signals supplied thereto.

Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.

Abstract: Systems and methods are provided for a temperature-compensated threshold voltage VT. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated VTN. According to one embodiment, a temperature-based modulation of a VBB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a VT-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

Abstract: A method of operating a memory includes generating a first reference voltage and detecting an active mode of operation of the memory. Upon detection of the active mode, commencing the charging of a node to develop a second reference voltage having a desired value on the node. The word line drive voltage is generated using the first reference voltage while the node is charging the second reference voltage to the desired value. The word line drive voltage is generated using the second reference voltage once the second reference voltage on the node has been charged to the desired value. A standby mode of operation of the memory is detected, and upon detection of the standby mode, the charging of the node is terminated and the word line drive voltage is generated using the first reference voltage.

Abstract: A semiconductor memory device performs a normal boost operation and increases access speed of the operation. The semiconductor memory device includes: a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder that selects one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit that outputs an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit. The first booster circuit is connected to the decoder and supplies boosted voltage to a selected word line based on the activated control signal. The second booster circuit is input the deactivated control signal.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

Abstract: A semiconductor memory device includes an internal voltage generation circuit controlling an internal voltage supplied to an internal circuit in accordance with a reference voltage, a reference voltage generation circuit generating the reference voltage, a plurality of signal terminals for transmitting and receiving a signal to and from an outside of the semiconductor memory device, and a reference voltage change indication circuit for indicating a change of the reference voltage on the basis of a binary input signal to each of the signal terminals with respect to the reference voltage generation circuit during a test.

Abstract: A semiconductor integrated circuit device comprises a control unit for switching a mode about the trimming or estimation in an internal circuit, the control unit including a controller capable of realizing the mode switching control about the trimming or estimation by the JTAG method. The controller includes an instruction decoder for decoding an input instruction, a shift scan register circuit for enabling a boundary scan based on the decoded result of the instruction decoder, and an operation controller for controlling the operations of the instruction decoder and the shift scan register circuit. Therefore, the trimming becomes possible after sealing a semiconductor chip into a package.

Abstract: An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.

Abstract: The present invention provides a semiconductor memory device and control method capable of effectively suppressing the generation of operating current originating in noise of address signals provided from the outside without impairing the operating speed during reading and writing. This semiconductor memory device is provided with a filter circuit (102) for removing noise contained in address signals provided from the outside, a circuit system containing an ATD circuit (311) for generating a first address transition detection signal (&phgr;ATD1) by detecting a change in an address signal prior to passing through the filter circuit (102), and a circuit system containing an ATD circuit (321) for generating a second address transition detection signal (&phgr;ATD2) by detecting a change in an address signal after passing through the filter circuit (102).

Abstract: A refresh initiated precharge technique using look-ahead refresh eliminates the need to close banks in a dynamic random access memory (“DRAM”) array prior to executing a “refresh” command by taking advantage of the fact that the actual initiation of an internal “refresh” operation is delayed by at least one clock cycle from the execution of the external “refresh” command. The technique is effectuated through the issuance of a “refresh” command to cause all banks within the DRAM array to precharge. This precharge occurs prior to the n-cycle delay (where N=1 or more clock cycles) of the internal “refresh” operation.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: To provide a power-source controller for reducing the current consumption while a DRAM is standby. The power-source controller is constituted by a mode detection circuit 4 for inverting an L-level disable signal under the enable state and inverting a disable signal into H-level under the disable state, an internal-power-source driver circuit 6 having Pch-Tr 6a and Pch-Tr 6b, and an internal-power-source reference circuit 5 for setting a first driver control signal to L-level and a second driver control signal to H-level when an L-level disable signal is input to turn on Pch-Tr 6b and turn off Pch-Tr 6a, supplying an external-power-source voltage VCC as an internal-power-source voltage IVC, setting a first driver control signal to H-level when an H-level disable signal is input, controlling the level of a second driver control signal to turn off Pch-Tr 6b and control Pch-Tr 6a, and supplying an internal power-source voltage IVC1 lower than the external-power-source voltage VCC.

Abstract: A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length.

Abstract: In a semiconductor memory device for performing a memory operation by controlling an internal voltage and a memory operation voltage, a cycle of an internal clock signal is varied in accordance with operation time characteristics of the memory operation.

Abstract: A container for storing and transporting field controllable fluid is disclosed. The field controllable material may be mixed and remixed in the container and the field controllable material may be flowed into or discharged from the container chamber without opening the container.

Abstract: A marine acoustic source system has relativley densely packed energy sources arrayed in a tandem-like fashion along a horizontal plane. Preferably, a longitudinal axis of each source lies orthogonal to a pre-determined towing direction. The system includes protective tubes that encloses supply lines and auxiliary equipment, and a harness. The harness provides the primary mechanical connection for towing the sources through the water. To minimize bending of the supply lines, connectors having angular portions connect the sources to the supply lines. Further, the sources can be arranged such that source connection interfaces for receiving power, hydraulic fluid, or data point alternately in opposing directions. During use, the sources, e.g., air guns, are supported at a predetermined depth beneath the water's surface by a floatation buoy. Upon activation, the sources of a cluster each release individual air bubbles into the water.

Abstract: The present invention is a method of estimating formation properties by analyzing acoustic waves that are emitted from and received by a bottom hole assembly.

Abstract: A method of applying an effective velocity model to vertical seismic profile (VSP) seismic data comprises correcting for offset using a non-hyperbolic effective velocity model so as to take account of the earth's layering and anisotropy. One preferred non-hyperbolic model for the relationship between offset and travel time is: formula (I) where t is the travel time of seismic energy from the source to the receiver, x is the offset between the source and the receiver, and z is the depth of the receiver.

Abstract: The present disclosure provides several methods for selecting and transmitting information from downhole using more than one channel of communication wherein data streams transmitted up each communications channel are each independently interpretable without reference to data provided up the other of the communications channels. Preferred embodiments incorporate the use of a combination of at least two of mud-based telemetry, tubular-based telemetry, and electromagnetic telemetry to achieve improved results and take advantage of opportunities presented by the differences between the different channels of communication.

Abstract: A method and system for telemetry through a drilling fluid during drilling is disclosed. A reflector (110) is positioned downstream from the drilling mud pumps (80) and causes reflected pressure waves having the same pressure polarity as incident pressure waves traveling upwards. At least one pressure sensor (92) is positioned below the reflector (110) to sense pressure in the drilling fluid. The reflector can be a fixed orifice plate or an adjustable aperture.

Abstract: The invention relates to a device forming a mouthpiece for a snorkel or diving regulator, adapted to fit in the mouth of a diver or swimmer and comprising a body (20) provided with an air intake and extended by two lateral branches (21) each provided with a bite tab (22), and at least one transducer buzzer positioned in one of the branches (21) and comprising a piezoelectric membrane (3, 4). According to the invention, each transducer buzzer comprises a peripheral weight (6) fixed to the periphery of the piezoelectric membrane (3, 4), and means (5, 30) for transmitting the vibrations of said membrane towards the teeth of the diver or swimmer. Furthermore, each transducer buzzer is positioned in the branch (21) in such a way that the piezoelectric membrane (3, 4) is totally isolated from the external environment, and that the transmission means (5, 30) form a contact interface with the teeth at the bite tab (22).

Abstract: A color referenced multi-time keeping timepiece includes at least two clocks on the same watch. These at least two clocks may be positioned one above the other, at a diagonal angle relative to each other, or side by side. The lens of one or both clocks is tinted and the minute and hour hands of each clock are brightly colored. The colored hands are fluorescent, making them easy to see, and also causing them to contrast with the color of the tinted lens. The face of each clock is phosphorescent, making the clock easy and convenient to read in low-light conditions. The tinting of one or both lenses provides a mental reference point for different time zones while the contrasting colors of the watch hands relative to the tinted lenses make it easy to see the necessarily smaller watch hands.

Abstract: This annual date mechanism comprises a correction cam (1a) in kinematic connection with a date indicating runner (1), a correction rocker (8) engaged on the one hand with said correction cam (1a) and, on the other hand, with an annual cam (18). A spring (9) presses the correction rocker (8) against the cams (1a, 18). The correction cam (1a) comprises a portion (1a′) for arming said spring (9), followed by a portion (1a*) sized to cause said date runner (1) to move by one step between “31” and “1”, under the pressure of said spring (9).

Abstract: The present invention is an apparatus and method for synchronizing and updating the memory of an external digital device, such as a personal digital assistant, and the memory of a watch via a two way communication link providing for the synchronous transfer of data between the devices. The data transfer is accomplished by placing the external digital device and watch into an alignment device which secures and positions each device in an appropriate spatial relationship allowing data to be transferred between devices. A separate integrated display controller provides for operation of the watch display thereby conserving power required to operate the device.

Abstract: The present invention is concerned with an operating unit adapted to be incorporated into a watch with a main setting device, which comprises at least two engagement positions, namely one rest position and at least one pulled position, and with at least one auxiliary setting device. The invention is also concerned with all types of watches suitable for the integration of such an operating unit and comprising said unit, in particular a world time watch with an analogue indication of the time of the day and of a corresponding location for different time zones with an offset relative to the local time by a multiple of an hour or of half an hour and thus allowing a simultaneous and reliable reading of the time of the day for the indicated time zones and a simple, fast and reliable operation and setting of the watch.

Abstract: The present invention is concerned with a control mechanism adapted to be incorporated into a watch with a main setting device, which comprises at least two engagement positions, namely one rest position and at least one pulled position, and with at least one auxiliary setting device. The invention is also concerned with all types of watches suitable for the integration of such a control mechanism and comprising said mechanism, in particular a world time watch with an analogue indication of the time of the day and of a corresponding location for different time zones with an offset relative to the local time by a multiple of an hour or of half an hour, which thus allows a simultaneous and reliable reading of the time of the day for the indicated time zones and which, in particular, avoids inadvertent modification of the settings of the watch.

Abstract: A timing device for visually indicating the passage of a duration of time is disclosed. The timing device and system, in accordance with the embodiments of the invention, is sectioned into zones with different rates of reactivity and/or sensitivity, such that the zones change color or darken over a range of times. The timing device, in accordance with further embodiments of the invention, comprises a film, that is a color film, a black and white film or a combination thereof, with a photographic layer and a developer layer, which when brought together activate the device. The photographic film can be pre-exposed to light or heat to control the rate that the film changes color or darkens after being activated. Pieces of timing film, in accordance with further embodiments of the invention, have adhesion layers for attaching the pieces of timing film to perishable articles or packages containing perishable articles and are preferably configured to be dispensed from a roll or stack of the timing film.

Abstract: A disk apparatus includes a stock section for storing a plurality of stacked disks, a disk transfer mechanism for withdrawing a selected disk out of the stock section, a selection mechanism for causing the selected disk and the disk transfer mechanism to face each other, a rotating section for driving the disk, a common motor, a power transmission mechanism for selectively transmitting the power of the motor to the selection mechanism and to the disk transfer mechanism, and a switching mechanism for switching between a first switching state in which the power of the motor is transmitted to the disk transfer mechanism and a second switching state in which the power of the motor is transmitted to the selection mechanism. The switching mechanism is switched between the states by the moving force of the disk transfer mechanism moving between a transfer-force transmitting position and a transfer-force interrupting position.

Abstract: A tracking control apparatus comprises an signal processing section, a lens characteristic measuring section and an optimum lens position searching section. The lens characteristic measuring section acquires a first address and second address of an optical disk. The lens characteristic measuring section successively generates offset set values so that the position of a converging lens is moved by an actuator at predetermined spatial intervals and counts the number of times both the first address and the second address are acquired. The optimum lens position searching section searches for a maximum value of the acquisition count and moves the converging lens using the actuator based on the offset set value when the acquisition count reaches a maximum value.

Abstract: A method and an apparatus are provided which are capable of evaluating a state of a signal with a fewer number of samples compared with an error rate. A reproducing signal obtained from a magneto-optical disk is subjected to maximum-likelihood decode in a maximum-likelihood decoder, paths coupling with each other in the maximum-likelihood decode is detected by an evaluation index generation unit and, at the same time, a difference of likelihoods (path metrics) of those paths is obtained to adjust a parameter of a recording and reproducing signal or a control signal of an optical pickup based on the likelihood difference. The parameter is, for example, auto-tracking, a gain of an auto-focusing loop, or an offset value, or a gain value of a reproducing signal, a recording power, or a reproducing power intensity.

Abstract: An optical information processing apparatus is designed to generate a tracking error signal based on reflected light from a storage medium. The apparatus is a 3-beam type, in which the storage medium is irradiated by a main beam and two sub-beams offset from the main beam in the tracking direction of the storage medium. Each of the two sub-beams is, as viewed on the storage medium, smaller in size in the tracking direction than the main beam.

Abstract: A pickup control circuit 5) for performing a control operation of an optical pickup 3) and an error detection circuit 14) for detecting an error signal from a servo signal obtained from the pickup control circuit 5) are provided. During an operation to change to a faster recording speed, a playback operation for an already recorded signal is performed at the recording speed after the change, and an error detection level is set on the basis of characteristics of the servo signal in the playback operation state.