Patents Issued in July 1, 2004
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Publication number: 20040124866Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed therein at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.Type: ApplicationFiled: October 16, 2003Publication date: July 1, 2004Applicant: FUJITSU LIMITEDInventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Makoto Haseyama, Futoshi Fukaya
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Publication number: 20040124867Abstract: A method for testing external connections to semiconductor devices. The method includes providing an external electrical path between selected external connections on the semiconductor devices.Type: ApplicationFiled: January 26, 2004Publication date: July 1, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gobinda Das, Franco Motika
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Publication number: 20040124868Abstract: A bump structure for testing a liquid crystal display panel includes a plurality of pads arranged at a pad region along an edge portion of a liquid crystal display panel and connected to one of a gate line and a data line, a driver IC arranged to be electrically connected to the plurality of pads, and a test bump electrically connected to at least one of the plurality of pads and arranged at the pad region except within a region where the driver IC is mounted.Type: ApplicationFiled: April 22, 2003Publication date: July 1, 2004Applicant: LG.PHILIPS LCD CO., LTD.Inventor: Joo Soo Lim
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Publication number: 20040124869Abstract: A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.Type: ApplicationFiled: November 13, 2003Publication date: July 1, 2004Inventors: Sang-Kyoung Lee, Dong-Gyu Kim, Min-Hyung Moon
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Publication number: 20040124870Abstract: A method and apparatus for testing an electric motor is provided. A voltage generator is configured to pulse a voltage into a motor. The current associated with the motor is measured and compared to the voltage pulses to determine a phase angle. The operability of the motor is determined based on the phase angle.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventor: Kurt Raichle
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Publication number: 20040124871Abstract: In apparatuses (1, 2, 3) controlled or operated via an I2C bus, it may be necessary to take measures to suppress interference signals at the data signal input/output of the respective apparatus without impairing the data transport at the same time. The data line (SDA) at the data signal input/output contains an RC element (RS, C), in the form of a low-pass filter, with a diode (D) connected in parallel with the RC element (RS, C), the low-pass filter action allowing said arrangement to be used to suppress interference signals acting on the data signal input/output, and, secondly, the transmissive action of the diode (D) meaning that said arrangement does not impair a data signal (ACK) leaving the data signal input/output.Type: ApplicationFiled: January 9, 2004Publication date: July 1, 2004Inventors: Alfred Selz, Veit Armbruster
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Publication number: 20040124872Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Theodore Z. Schoenborn, Andrew W. Martwick
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Publication number: 20040124873Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Theodore Z. Schoenborn, Andrew W. Martwick
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Publication number: 20040124874Abstract: A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Tsvika Kurts, Zelig Wayner, Tommy Bojan
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Publication number: 20040124875Abstract: A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Inventors: Sanjay Dabral, Santanu Chaudhuri
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Publication number: 20040124876Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Applicant: Actel CorporationInventor: William C. Plants
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Publication number: 20040124877Abstract: An improved integrated circuit and a related system apparatus and method. The integrated circuit includes a plurality of logic area or user logic areas; and an actively switchable network capable of selectively connecting at least one logic area with another logic area. In particular, the plurality of logic areas include an array of logic-gates or logic-blocks or custom logic which form functional blocks. The integrated circuit can provide a chip-architecture where the functional blocks are specific hardware functional blocks, hardware functional blocks that are parameterized, and/or programmable functional blocks including programmable processors.Type: ApplicationFiled: October 6, 2003Publication date: July 1, 2004Inventor: Stephen Maxwell Parkes
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Publication number: 20040124878Abstract: Embodiments of the present invention relate to a voltage clamp circuit including a transistor and a switch. The switch is coupled between a gate of the transistor and a source or a drain of the transistor. Embodiments of the present invention can quickly raise and lower a voltage level supplied to a memory device.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventor: Hemmige D. Varadarajan
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Publication number: 20040124879Abstract: An improved low voltage to high voltage translator for digital electronic circuits providing reduced rise times, fall times and transition times that remain independent of operating conditions. This is accomplished by modifying a conventional low-to-high voltage translator to include a switched active pull-up at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the output from the low-to-high-voltage translator and a switched active pull-down at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the complement of the output from the low-to-high-voltage translator, so as at to provide regenerative pull-up and pull-down that also counteracts the bootstrap capacitance at the output of the first high-voltage switch.Type: ApplicationFiled: September 29, 2003Publication date: July 1, 2004Inventor: Rajesh Narwal
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Publication number: 20040124880Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Vivek K. De
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Publication number: 20040124881Abstract: According to some embodiments, scan cell designs are provided for a double-edge-triggered flip-flop.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Paul J. Thadikaran, Nasser A. Kurd
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Publication number: 20040124882Abstract: A complementary metal oxide semiconductor (CMOS) low-power, high speed logic circuit consisting of a cascaded chain of stages. The first stage is a pulsed domino logic circuit having one or more logic signal inputs for receiving data signals, and a timing input for receiving a clocking pulse that conditions the input pulse domino stage for evaluation during a brief window of time. The output of the pulsed domino circuit is connected to a chain of series-connected skewed static logic gates, each having the channel sizes of its pull-up and pull-down transistors ratioed to a produce, from gate-to-gate in the static logic chain, alternating fast high-to-low and low-to-high transitions for the information carrying leading edge of said input data signals. The use of a pulsed domino first stage driving a chain of skewed logic static gates reduces power consumption but retains the speed of conventional domino logic circuits.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Applicant: Intel CorporationInventors: Sudarshan Kumar, Jiann-Cherng Lan, Snehal Jariwala, Wenjie Jiang
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Publication number: 20040124883Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Dejan Markovic, James W. Tschanz, Vivek K. De
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Publication number: 20040124884Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
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Publication number: 20040124885Abstract: A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first cycle, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second cycle, and outputs a digital peak signal. The time of the first cycle is shorter than the time of the second cycle. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.Type: ApplicationFiled: December 18, 2003Publication date: July 1, 2004Inventors: Tse-Hsiang Hsu, Yung-Yu Lin, Chih-Cheng Chen
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Publication number: 20040124886Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)-, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).Type: ApplicationFiled: September 10, 2003Publication date: July 1, 2004Applicant: Infineon Technologies AGInventors: Andre Schaefer, Johann Pfeiffer, Kazimierz Szczypinski
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Publication number: 20040124887Abstract: The invention refers to a circuit device (1) with at least one connection (3b), to which a clock pulse (/CLK, /CLKT) can be applied, whereby the circuit device (1) also comprises a clock pulse detection facility (2) for detecting whether there is a clock pulse (/CLK, /CLKT) present at the connection (3b), or whether there is no clock pulse (/CLK, /CLKT) present at the connection (3b).Type: ApplicationFiled: September 23, 2003Publication date: July 1, 2004Inventors: Andre Schaefer, Johann Pfeiffer, Kasimierz Szczypinski, Joachim Schnabel
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Publication number: 20040124888Abstract: A Low Voltage Differential Signaling [LVDS] Driver with Pre-emphasis and comprising a primary stage (MP3-MP6, MN3-MN6) having a first switching circuit (MP5, MP6, MN5, MN6) arranged to provide a sequence of pulses (OUT1; OUT2) at a predetermined current level (I1), a secondary stage (MP7-MP9, MN7-MN9) having a second switching circuit (MP8, MP9, MN8, MN9) arranged to provide an additional current level (I2) for the pulses, and a control circuit arranged to provide control signals (A,{overscore (A)},B,{overscore (B)}) for controlling the first and second switching circuits. The control circuit is adapted to detect a difference in level between two consecutive pulses of the sequence and to provide accordingly control signals (A,{overscore (A)},B,{overscore (B)}) to the first (MP5, MP6, MN5, MN6) and second (MP8, MP9, MN8, MN9) switching circuits.Type: ApplicationFiled: December 17, 2003Publication date: July 1, 2004Applicant: ALCATELInventor: Andrzej Gajdardziew Radelinow
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Publication number: 20040124889Abstract: A drive circuit for LEDs or other light-emitting elements with which the influence of the changes in temperature or power supply voltage and the element variations can be restrained in order to output a pulse current with a constant level. When n-type MOS transistor 10 is on, power is supplied from switching power supply 60 to the LED, and the current of LED is detected by resistor 20. The error signal Serr between said detection signal Sfb and setpoint signal Sref is generated by error signal generating unit 30 and is averaged by signal holding unit 40. The power supplied to the LED is controlled corresponding to the averaged error signal SerrA. When n-type MOS transistor 10 is turned off from the on state, the power supplied to the LED is stopped, and error signal SerrA is held in signal holding unit 40. When n-type MOS transistor 10 is turned on from the off state, the averaging of error signal Serr is started with the signal level of the held error signal SerrA used as the initial level.Type: ApplicationFiled: October 8, 2003Publication date: July 1, 2004Inventors: Yoshitaka Koharagi, Masashi Nogawa
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Publication number: 20040124890Abstract: The invention relates to a driver circuit withType: ApplicationFiled: September 29, 2003Publication date: July 1, 2004Applicant: Infineon Technologies AGInventors: Christian Muller, Henrik Icking, Martin Glas
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Publication number: 20040124891Abstract: A method for amplifying a digital signal representative of data to be transmitted by a line driver with pre-emphasis over an output line is provided. The gain of the line driver is varied between an upper value to coincide with switching of the digital signal and a lower value in absence of the digital signal switching. In particular, the varying includes amplifying the digital signal with a first gain for generating an amplified digital signal, delaying the digital signal with a predetermined delay for generating a delayed digital signal, and amplifying the delayed digital signal with a second gain for generating a delayed and amplified digital signal. An ouput signal corresponding to a difference between the amplified digital signal and the delayed and amplified digital signal is output over the output line.Type: ApplicationFiled: October 6, 2003Publication date: July 1, 2004Applicant: STMicroelectronics S.r.l.Inventors: Pierpaolo De Laurentiis, Luciano Tomasini, Claudio Cattaneo
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Publication number: 20040124892Abstract: Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.Type: ApplicationFiled: October 7, 2003Publication date: July 1, 2004Applicant: Impinj, Inc., a Delaware CorporationInventors: Christopher J. Diorio, Todd E. Humes, Michael Thomas
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Publication number: 20040124893Abstract: A source synchronous bus system is provided with a bus; a first device connected to the bus, having a driver to drive data and strobe signals, via the bus; and a second device connected to the bus, having a receiver to receive data and the strobe signals from the bus, and to select one of rising and falling edges of the strobe signals to latch a corresponding one of rising and falling edges of the data received from the bus, for subsequent data processing functions in order to compensate for systematic differences between rising and falling edges of the data received, via the bus.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Maynard C. Falconer, Zane A. Ball
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Publication number: 20040124894Abstract: A power-up detection apparatus comprises a voltage divider, a potential detector and a buffer. The voltage divider divides an inputted power voltage in a predetermined ratio. The potential detector compares a predetermined potential with a potential outputted from said voltage divider, and outputs the comparison result. The buffer changes the level of said comparison result when said comparison result outputted from said potential detector is maintained at a predetermined potential for a predetermined period. As a result, a semiconductor device can be stably initialized because a power-up signal is generated only when an externally inputted power voltage is maintained at a current state over a predetermined period although the state of the external power voltage is toggled by noise.Type: ApplicationFiled: June 30, 2003Publication date: July 1, 2004Inventors: Chang Seok Kang, Jae Jin Lee
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Publication number: 20040124895Abstract: A signal delay compensating circuit which is a digital circuit includes: a first semiconductor circuit device (100) having a clock-signal generating circuit (1) and a data processing circuit (2) and adapted to output a data signal in synchronism with a clock signal; and a second semiconductor circuit device (4) to which the output data signal is inputted and which processes the input data signal in synchronism with the clock signal. The clock signal to be supplied from the first semiconductor circuit device (100) to the second semiconductor circuit device (4) is fed back to the data processing circuit (2), and the fed-back clock signal is used as a clock signal at the time of outputting the data signal. A signal delay compensating circuit which effects compensation by following the delay of a reference signal is thereby provided.Type: ApplicationFiled: October 10, 2003Publication date: July 1, 2004Applicant: Yamaha CorporationInventor: Masahiro Ito
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Publication number: 20040124896Abstract: In a delay locked loop (DLL) of a semiconductor memory device capable of compensating for delay of an internal clock signal by variation of driving strength of an output driver, a replica output driver exhibits the same delay amount as the delay amount as an output driver whose driving strength varies. A phase detector detects a phase difference between an internal clock signal which is delayed by the replica output driver, and an external clock signal. A control circuit generates a control signal in response to the output signal of the phase detector. A variable delay circuit, in response to the control signal, delays the external clock signal and generates the internal clock signal in synchronization with the external clock signal. Since the DLL has a replica output driver which can accurately track the delay of an internal clock signal by variation of the driving strength of an output driver in the feedback loop, output data can be accurately synchronized with an external clock signal.Type: ApplicationFiled: November 6, 2003Publication date: July 1, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Gyung-su Byun, Nak-won Heo
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Publication number: 20040124897Abstract: The present invention discloses a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, comprising a first time hysteresis unit, a second time hysteresis unit and an inverter. The first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level. The second time hysteresis unit has the characteristic of time hysteresis connected to the first hysteresis in series when the input signal transits from the second level to the first level.Type: ApplicationFiled: June 30, 2003Publication date: July 1, 2004Inventor: Sang Sic Yoon
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Publication number: 20040124898Abstract: An integrated circuit comprising a circuit block whose power supply is controlled by waiting operation, is supplied which is able to prevent the occurrence of penetrating electricity caused by unstable signals output from the circuit block whose power supply was broken. In the integrated circuit, a mask signal is set at “L” level before a power in the circuit block is broken, a latch circuit formed by a NAND and an inverter keeps a node in “L” state, then when the power supply is broken and drops into “L” level, the output signal of the NAND is fixed in “H” level. Thus, from the circuit block, even if a unstable mask signal is output, the node keeps in “L” level, so that gate circuits become off.Type: ApplicationFiled: June 20, 2003Publication date: July 1, 2004Inventor: Hidetaka Kodama
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Publication number: 20040124899Abstract: A synchronizer eliminates metastability due to violation of either the setup time or the hold time of a circuit. The input of a first flip-flop (12a) is tied to a constant logic level (VDD or ground). The first flip-flop receives an asynchronous signal into the reset (preset or clear) input of the flip-flop. No violation of the setup or hold times of the flip-flop can occur. The second flip-flop (12c) receives the output of the first flip-flop as its clock input. The second flip-flop (12c) is configured as a toggler. The second flip-flop produces a synchronized partial signal (18a) of the original asynchronous signal (10a). Third and fourth flip-flops (12b,12d) may similarly be configured to produce a second synchronized partial signal (18b) of the asynchronous signal recovery and may prevent runt pulses from being received by the flip-flops.Type: ApplicationFiled: February 12, 2003Publication date: July 1, 2004Inventors: Jose Alberto Cavazos, Robert Maurise Simie
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Publication number: 20040124900Abstract: The invention relates to a digital signal delay device (101) for converting a signal (IN) into a corresponding delayed signal (OUT), comprising a plurality of signal delay elements (103a, 103b, 103c) connected in series, wherein, as a function of the desired delay of the delayed signal (OUT), the output signal of a particular signal delay element (103a, 103b, 103c) is used for generating the delayed signal (OUT), and wherein the signal delay elements (103a, 103b, 103c) each comprise one single inverter (105, 106, 107) only.Type: ApplicationFiled: September 10, 2003Publication date: July 1, 2004Applicant: Infineon Technologies AGInventor: Martin Brox
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Publication number: 20040124901Abstract: A level shift circuit which realizes a high-speed and power-saved operation particularly when the input voltage is at a low level is provided. The level shift circuit of the present invention comprises a first gate voltage control circuit controlled by a inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from “H” to “L”, the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and then the voltage of the second output terminal goes down.Type: ApplicationFiled: October 9, 2003Publication date: July 1, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Seiji Yamahira, Norio Hattori, Ken Arakawa
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Publication number: 20040124902Abstract: The present invention relates to a resistance calibration circuit to correct a resistance variation in an output terminal of a semiconductor device. The resistance calibration circuit according to the present invention includes: a correction code generator for generating a plurality of push-up code signals and a plurality of pull-down code signals based on an external reference resistor, wherein a reference voltage is applied to the correction code generator; a push-up decoder for decoding the plurality of push-up code signals from the correction code generator; a pull-down decoder for decoding the plurality of pull-down code signals from the correction code generator; and a resistance adjustor for receiving a push-up signal from the push-up decoder and a pull-down signal from the pull-down decoder and for turning on/off a plurality of inner transistors.Type: ApplicationFiled: July 22, 2003Publication date: July 1, 2004Inventor: Seong-Min Choe
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Publication number: 20040124903Abstract: A method, apparatus, and system for determining or observing internal state information in a chip.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventor: Sunil Chaudhari
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Publication number: 20040124904Abstract: A current mirror circuit is provided. The circuit includes a resistor having a first terminal connected to a current source, a first transistor having a substrate electrode connected to a drain electrode thereof, a second transistor having a substrate electrode connected to the substrate electrode of the first transistor, a third transistor having a substrate electrode connected to the substrate electrode of the first transistor, and a fourth transistor having a drain electrode for providing an output current.Type: ApplicationFiled: September 24, 2003Publication date: July 1, 2004Applicant: Winbond Electronics Corp.Inventor: Li-Te Wu
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Publication number: 20040124905Abstract: A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier unit and an output stage, driven by the latter, having a power transistor circuit for transmitting an antiphase signal using a two-wire line. A control circuit is connected to one of the driver paths and controls the turn-on resistance of the power transistor circuit in this driver path such that the power transistor circuits in the two driver paths have the same turn-on resistance.Type: ApplicationFiled: October 30, 2003Publication date: July 1, 2004Inventors: Ordwin Haase, Eric Pihet
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Publication number: 20040124906Abstract: A method and apparatus for generating a reference voltage potential, also known as an input switching reference, using differential clock signals or other differential signals that ideally have a 180 degree phase shift is provided. The differential signals are generated by a transmitting circuit. The reference voltage potential is dependent on the differential signals. The voltage potentials of the differential signals are averaged and low-pass filtered. Comparators in a receiving circuit compare an input signal's voltage potential to the reference voltage potential to determine if the transmitted input signal is a binary one or binary zero.Type: ApplicationFiled: December 26, 2002Publication date: July 1, 2004Inventor: William B. Gist
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Publication number: 20040124907Abstract: A voltage multiplier circuit in particular for programmable memories is supplied by a low voltage. This circuit includes an oscillator which generates a clock signal and a charge pump circuit controlled by the clock signal. The charge pump boosts a DC supply voltage to a high voltage which is looped back to a voltage feedback regulator. A multiplexer which is placed between the oscillator and the charge pump, receives a gating signal from the regulator which depends on the comparison of the high output voltage to a determined regulation voltage.Type: ApplicationFiled: February 13, 2004Publication date: July 1, 2004Inventor: Dean Allum
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Publication number: 20040124908Abstract: A low voltage constant current source is composed of a reference current circuit being insensitive to temperature variation, and multiple current output units in response to the reference current circuit to individually output a stable current. Each current output unit is individually controlled to be activated or not, and each output current is amplified in any desired ratio to a reference current generated by the reference current circuit. Moreover, since each current unit is operated independently, the interference among each other is avoided when each output unit is applied in the open-collector.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Inventor: Chia-Cheng Lei
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Publication number: 20040124909Abstract: Arrangements (methods, apparatus, etc.) providing safe component biasing.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Nazar Syed Haider, Ahmad Siddiqui, Sooseok Oh
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Publication number: 20040124910Abstract: An automatic adjustment system for source current and sink current mismatch. The system includes a startup compensation/setup device to perform initialization current compensation and accordingly implement a control reference table, a determination device to output a control signal according to the control reference table, and a current compensation device to switch corresponding internal switches on and off according to the control signal and complete the desired compensation for source current and sink current mismatch.Type: ApplicationFiled: December 3, 2003Publication date: July 1, 2004Applicant: Airoha Technology Corp.Inventors: Chao-Hsi Chuang, Yu-Hua Liu
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Publication number: 20040124911Abstract: An adjustable filter, particularly for use as an antialiasing filter in digital telecommunications networks, includes adjustable capacitors which determine frequency response for the purpose of accurate alignment with a particular cut-off frequency. The active filter includes, in line with the invention, a control device with a measuring device for ascertaining the actual cut-off frequency of the filter. On the basis of the ascertained actual cut-off frequency of the filter and the information about the nominal cut-off frequency which is to be set, an adjustment parameter for the adjustable capacitor is selected from a memory arrangement. This adjustment parameter is used to adjust the adjustable capacitor such that the desired nominal cut-off frequency is obtained and, at the same time, the alignment is performed to achieve the nominal cut-off frequency with sufficient accuracy.Type: ApplicationFiled: October 30, 2003Publication date: July 1, 2004Inventors: Christian Fleischhacker, Gunter Koder, Francesco Labate, Michael Staber, Hubert Weinberger
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Publication number: 20040124912Abstract: A remote signaling receiver system includes a receiver that operates in two different modes of demodulation to accommodate different types of signals from different types of transmitting devices. A first demodulator, preferably an ASK demodulator, is adapted to process signals from a signal transmitter that generates a first type of signal. A second demodulator, preferably one that is not sensitive to amplitude modulation such as a FSK demodulator, is adapted to process signals received from at least one other type of device, which provides a second type of signal. A system designed according to this invention is particularly useful as a remote keyless entry system for a vehicle where one or more sensors are provided on the vehicle to provide an indication of a chosen condition of one or more of the vehicle components.Type: ApplicationFiled: August 22, 2001Publication date: July 1, 2004Inventors: Tejas B. Desai, Michael Thomas
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Publication number: 20040124913Abstract: A power amplifier circuit for receiving a variable envelope input signal and for producing an amplified output signal is provided. The power amplifier circuit includes an envelope approximation circuit, an envelope amplifier circuit, a phasor approximation circuit, a quadrature modulation circuit, and a power amplifier. The envelope approximation circuit receives the variable envelope input signal and produces a bandlimited estimated envelope signal, corresponding to the amplitude of the variable envelope input signal. The bandlimited estimated envelope signal is then amplified by an envelope amplifier circuit. The amplified envelope signal is then coupled to the supply input of the power amplifer. The phasor approximation circuit receives the variable envelope input signal and produces a bandlimited estimated phasor signal. The quadrature modulation circuit receives the estimated phase signal and produces a modulated phase signal.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Pallab Midya, John Grosspietsch, Michael Washington
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Publication number: 20040124914Abstract: To provide a new switching amplifier in which power supply switching noise is reduced to improve the quality. The switching amplifier is provided with a power amplifier (1) that has a modulator which modulates an analog signal or a multi bit digital signal into a two-level signal, and supplies an output pulse signal from this modulator to a power switching element (3); and a &Dgr;&Sgr; power supply (5) which is provided with a &Dgr;&Sgr; modulating device, and the construction is such that the output pulse signal from the modulator of the power amplifier (1) is supplied to the &Dgr;&Sgr; power supply (5), and also the construction is such that the &Dgr;&Sgr; power supply (5) receives the pulse signal as an operating clock, &Dgr;&Sgr; modulates the received pulse signal, and supplies the &Dgr;&Sgr; modulated pulse signal to the power switching element (3).Type: ApplicationFiled: June 10, 2003Publication date: July 1, 2004Inventor: Atsushi Mitamura
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Publication number: 20040124915Abstract: Disclosed is an Amplifier (7) comprising an output driver with a first output stage (4) and a second output stage (5), where an input signal is applied non-inverted to the first output stage and inverted to the second output stage, characterized in that said input signal is applied with delay to one of the output stages (4, 5).Type: ApplicationFiled: August 14, 2003Publication date: July 1, 2004Inventors: Alexandre Heubi, Christian Caduff