Abstract: A method and apparatus for controlling a power supply, having a power switching unit, in an electronic machine using a host connected to the electronic machine. Received alternating current (AC) power is transmitted to the power switching unit and simultaneously transformed into direct current (DC) power. Next, it is determined whether the host requests provision of the DC power to the electronic machine. Then, the power switching unit is driven using the AC power when it is determined that provision of the DC power to the electronic machine is requested. Thus, even when a power switching unit is not supplied with power immediately after interruption of power from an AC power supply source, charges stored in an electrolytic capacitor are not discharged so that incorrect operation of the electronic machine is prevented.

Abstract: A programmable photo-coupler-isolated wide band modulator for high voltage power supply is disclosed, which utilizes a high voltage module to step up the input voltage and utilizes a wide band modulator connected with the high voltage module to modulate the high voltage output from the high voltage module for outputting a wide band high voltage, wherein the wide band modulator receives a modulator signal generated by a computer for modulating.

Abstract: A flexible integrated power converter system that connects various types of electrical power sources together and supplies a defined type of electrical energy to a load, such as a standard household mains voltage supply, is provided. Each of the electrical power sources is electrically isolated from the load, as well as each other. A respective input converter is coupled to each power source. Each input converter may include a small high-frequency transformer driven by an efficient soft-switched dc-dc converter. The voltages produced by each of the input converters are combined in parallel and delivered to a single output inverter. The output inverter converts the combined voltages to an ac voltage that may be delivered to a load.

Abstract: A pulse width modulated soft-switching power converter, having a transformer with a primary winding and a secondary winding, a secondary circuit coupled to the secondary winding, and a pair of main switches and a pair of auxiliary switches coupled to the primary winding. The main switches and auxiliary switches intermittently conduct an input voltage source to the primary winding of the transformer to operate the soft-switching power converter in four operation stages in each switching cycle. The main switches conduct the input voltage source to the transformer in a first operation stage. In a second operation stage, the conduction is cut off. The transformer operates as an inductor with the auxiliary switches switched on under zero-voltage or zero-current switching mode in a third operation stage. In the fourth operation stage, the auxiliary switches are switched off to achieve zero-voltage transition.

Abstract: The present invention provides a switching power supply which reduces power consumption in a standby state and improves power supply efficiency. At the time of starting a standby mode in which the output voltage VFB of the IV converter exceeds a standby detection upper limit voltage from a reference voltage source, the switching operation of the switching element is stopped. This stopping reduces the output voltage VFB of the IV converter along with a power supply voltage VO. When the output voltage VFB is lower than a standby detection lower limit voltage from the reference voltage source, the switching operation of the switching element is resumed.

Abstract: A flyback power converter has a transformer, a primary circuit and a secondary circuit. A switching device controlled by a switching signal is disposed in the primary circuit to control the switching of the transformer. The secondary circuit further has an output capacitor connected at the output of the power converter and a synchronous rectifier connected in between the transformer and the output capacitor. A controller is connected to the synchronous rectifier to control on/off status of thereof in response to a secondary current and a synchronous detection signal for both discontinuous and continuous operation mode, wherein the secondary current is generated in the secondary circuit and the synchronous detection signal is produced by detecting the switching signal through the secondary winding of the transformer. In one embodiment, the equivalent series resistance (ESR) of the output capacitor is used as a sensor to detect the secondary current.

Abstract: A current detection unit of an inverter outputs currents to a load, such as a motor includes a device for measuring a DC current flowing in the inverter. The current detection unit also includes a measurement time setting device for setting a measurement time of power source currents at at least one of an uppermost point and a lowest point of a reference chopping wave with a predetermined frequency, and a current phase detection means for detecting at least two phase currents from respective power source currents measured at two or more measurement times sequential to each other. A phased current output from the inverter to a load, such as a motor, may be detected with a high degree of accuracy and at a constant period.

Abstract: A pulse width modulation voltage regulator comprises a pulse width modulation circuit and a control circuit. The control circuit is operable to reduce a pulse modulation frequency of the pulse width modulation circuit when a load current increases and to increase the pulse modulation frequency of the pulse width modulation circuit when the load current decreases.

Abstract: Two proposals are made for power supply systems comprising at least one resonant inverter and one control unit. According to the first proposal the power supply system comprises two inverters and produces two output voltages, the control circuit processing as an actual value on the one hand the sum of and on the other hand the difference between the two output voltages. According to the second proposal a control circuit does not directly process the controlled variables for a power supply system comprising at least one inverter, but difference units for controlled variables determine the deviations from a preceding sampling instant and these difference values are processed. Also the correcting variable calculated in this way is a difference value which is converted into a correcting variable value by a correcting variable summing unit. The two proposals can be advantageously combined.

Abstract: An apparatus for controlling the power supplied from an AC power supply to an ohmic load, includes a switch for connecting the load to the AC power supply, a controller for providing a control signal to the switch, and a rectifier bridge having an input and an output. The input is adapted for connection to the AC power supply and the output is connected to a series connection of a first inductor, the load and the switch. The controller provides a control signal with a frequency which is at least 500 times higher than the frequency of the AC power supply. The switch is switched on and off by the control signal. The controller comprises a control element for varying the duty cycle of the control signal.

Abstract: A boost circuit is connected to a rechargeable battery and a switch is connected between a rectification circuit and a power factor correction converter. In the power failure state, the switch is turned on to activate the boost circuit and energy of the rechargeable battery is supplied to a load by rasing the voltage at two steps in the path from the boost circuit, switch, and to power factor correction converter. Since the voltage of the battery can be lowered, the number of serially connected cells can be made small. The volume of UPS can be reduced and a low cost can be realized. Since the number of serially connected cells is reduced, the reliability against failure of battery cells can be improved.

Abstract: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Abstract: A high frequency power inductance element capable of remarkably reducing a leakage by remarkably reducing an interwinding capacity, remarkably increasing heat radiation from coils, and remarkably improving productivity and a cost, comprising coils formed of a band-shaped conductor spirally wound in a cylindrical shape so that the wider surfaces thereof come flush with each other, an electrically insulated bobbin for installing the coils thereon, and cores inserted into the bobbin to form a closed magnetic circuit.

Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.

Abstract: A method and apparatus for automatically providing a Next Free Address (NFA) within a Content Addressable Memory (CAM) is disclosed. The NFA can be determined simultaneously with a search process for a matching address, thereby expediting the NFA search.

Abstract: An apparatus and method is disclosed for a CAM priority match detection circuit that identifies one or more CAM words from a group of CAM words having a “longest match” that matches the bits in a corresponding comparand register. A decoder is further disclosed, wherein the decoder uses n input lines and m complement lines to generate 2n outputs, wherein only one of the outputs will be active. A priority setting circuit and a priority resolving circuit are also disclosed, wherein the priority setting circuit resolves an initial matching operation to supply priority values to CAM words, and the priority resolving circuit processes the priority values to determine an overall priority for a group of CAM words.

Abstract: An apparatus and method is disclosed for detecting CAM words having a “near match” condition, where “near match” is defined by a CAM word having one or more mismatching bits. Each cell in a CAM word is connected to a match line, where a small known current is impressed upon the line each time a bit does not match with search data. The total current is sensed to establish a priority for each respective CAM word. Each priority for each CAM word is then decoded to determine the Cam word having the highest priority. Under an alternate embodiment, a minimum priority level select circuit is disclosed, where a user may specify an acceptable priority level that is generated from a CAM word search.

Abstract: A priority encoder includes a highest priority indicator configured to receive data on multiple content addressable memory (CAM) match lines and flag a highest priority active match line. A multiple match detector detects the presence of multiple simultaneously active match lines. Logic circuitry disables an active match line flagged by the highest priority indicator. The highest priority indicator successively cycles so long as the multiple match detector detects the presence of multiple simultaneously active CAM match lines.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A memory system has a circuit board provided with a first slot connector into which a first memory module is inserted. A second slot connector is provided into which a second memory module is inserted. The first and the second memory modules are connected via a flexible bridge. The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge provides a signal bus between the memory modules.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the corresponding CMOS transistor) will be at a logical value which turns off the corresponding CMOS transistor is determined. A CMOS transistor with a high threshold voltage may be connected to receive an input signal with a high probability to reduce the aggregate leakage current in the circuit. The approach may be used in any environments such as synthesis tools and also manual design methodologies.

Abstract: An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.

Abstract: An optical memory plate particularly suitable for identification purposes or protection against forgery and counterfeiting radiation provides inscription of data and read-out of thus stored inscription data, comprises a europium doped alkali metal halide storage phosphor layer, and, more preferably, a stimulable CsBr:Eu phosphor substantially free of alkaline earth metals.

Abstract: The present invention provides a semiconductor memory device for reducing power consumption by turning off a DLL clock tree in stand-by mode. The synchronous semiconductor memory device in accordance with the present invention includes a clock synchronization means for synchronizing a data output with a external clock; and a clock tree on/off control means for delaying an enable timing of a RAS idle signal for a predetermined time after a row inactive instruction is supplied, turning on/off a clock tree of the clock synchronization means in response to the RAS idle signal.

Abstract: An interleave control device using a nonvolatile ferroelectric memory is disclosed. More specifically, a memory interleave structure using a nonvolatile ferroelectric register configured to individually control interleaves of banks is disclosed. In an embodiment of the present invention, interleaves of each bank can be individually controlled using a single nonvolatile ferroelectric memory chip, a multi-bank nonvolatile ferroelectric memory chip or a multi-bank interleave nonvolatile ferroelectric memory chip.

Abstract: A ferroelectric memory device includes memory cells, a memory cell block, a sense amplifier, a precharge circuit, a bit line drive circuit, and a plate line drive circuit. Each of the memory cells has a cell transistor and a ferroelectric capacitor in between a source and drain of the cell transistor. The memory cell block includes the memory cells that are series connected between a bit line via a block select transistor and a plate line. The sense amplifier amplifies data read out from the memory cell, and generates one of a first potential and a second potential higher than the first potential in accordance with the read-out data. The precharge circuit precharges the bit line at a third potential that is higher than the first potential and lower than the second potential. The bit line drive circuit sets the bit line at a fourth potential.

Abstract: The present invention relates to a nonvolatile memory, device, and more specifically, to a programmable nonvolatile logic switch memory (register) device using a resistive memory device. The programmable nonvolatile register uses a logic switch or a nonvolatile resistive memory device whose resistive state can be set by flowing a controlled current through it.

Abstract: Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are provided for reading non-volatile data states from a non-volatile portion of a memory cell into a volatile portion.

Abstract: The invention provides technologies which can restrict damage due to static electricity to a gate insulating film of a transistor inside a semiconductor device forming an oscillating circuit. In particular, an oscillating circuit can include an oscillator and a semiconductor device which utilizes the oscillator. The semiconductor device can include an inverting amplifier which is provided in parallel with the oscillator and comprises an insulated gate type field effect transistor; a buffer circuit which includes an insulated gate type field effect transistor and is used to send out a signal output from the inverting amplifier to another circuit, and a transmission gate which is provided between the output terminal of the inverting amplifier and the input terminal of the buffer circuit, and includes an insulated gate type field effect transistor.

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract: A memory cell comprises a magneto-resistive element of which electrical resistance value varies with magnetism. A sub-bit line is connected to one end of the memory cell. A main-bit line is connected to the sub-bit line via a first selection circuit. A sense-amplifier is connected to the main-bit line via a second selection circuit. A wiring line is connected to the other end of the memory cell and arranged in a first direction. A first operation circuit is connected to one end of the wiring line via a third selection circuit. A second operation circuit is connected to the other end of the wiring line. A word line passes over an intersection between the memory cell and the wiring line and is arranged in a second direction perpendicular to the first direction.

Abstract: A magnetic random access memory having a memory cell array in which one block is formed from a plurality of magnetoresistive elements using a magnetoresistive effect, and a plurality of blocks are arranged in row and column directions, includes a plurality of first magnetoresistive elements arranged in a first block, a plurality of first word lines each of which is independently connected to one terminal of a corresponding one of the first magnetoresistive elements and runs in the row direction, a first read sub bit line commonly connected to the other terminal of each of the first magnetoresistive elements, a first block select switch whose first current path has one end connected to one end of the first read sub bit line, and a first read main bit line which is connected to the other end of the first current path and runs in the column direction.

Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Abstract: Each memory cell row is associated with access transistors having their source regions electrically connected together by an n+ diffusion node extending in the direction of the row. The n+ diffusion node is connected to a main word line set to have the low level (a ground voltage) in selecting a corresponding memory cell row. When the main word line is set low, responsively in a data read operation a selected row's word line is set high and in a data write operation a selected row's digit line is set high.

Abstract: One sub-data circuit is disposed for one selected bit line in a 4-level memory. The sub-data circuit has first and second latch circuits for serial accessing. In reading, an upper bit is latched through a sense latch in the first latch circuit. A reading operation of a lower bit is controlled to a value of the upper bit latched in the first latch circuit. In programming, an upper bit is latched in the first latch circuit. A program operation of a lower bit is controlled to a value of the upper bit latched in the first latch circuit.

Abstract: A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

Abstract: A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.

Abstract: A method for programming a memory cell is provided that includes detecting a program command at the memory device and detecting an external voltage applied to the memory device that exceeds a predetermined value. The method includes, in response to the program command and the detected external voltage, applying an internally generated programming voltage to a control gate of the memory cell. Applying a voltage pulse to a drain of the memory cell while the control gate is at the internally generated programming voltage is also included in the method.

Abstract: A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.

Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: A nonvolatile semiconductor memory device includes a memory array, a selecting circuit, a storage device, a power generator, a connecting circuit, and a write or erase controller. The selecting circuit selects one of memory cells from the memory array. A sequence for controlling write and erase operations for the memory cells is stored in the storage device. The power generator is able to generate certain voltage higher than requirement voltage for write or erase operation. The sequence includes a plurality of sub-sequences in which write or erase operation to the memory cell is implemented. Each of the sub-sequences includes before the end: a voltage resetting step of resetting a voltage impressed on the selecting circuit to the power voltage or grounding; and a route resetting step of resetting a switch of a transistor of the selecting circuit to last status just before write or erase operation.

Abstract: A memory module is described having a memory array storing data, an ID information output circuit for outputting ID information for identifying memory modules, and output switching means for selectively switching between output from the memory array and output from the ID information output circuit, and output from the ID information output circuit will be selected instead of output from the memory array until the memory module is initially written after the power supply to the memory module has been started. This enables a memory module to be identified without having to add parts to a computer system unit or providing a ROM storing a specification or the like to the memory module.

Abstract: A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.

Abstract: A switch section for changing the function of an FPGA is provided with a data latch circuit used for connection control. The data latch circuit includes program sections in which program data is stored in advance, and latch unit. At the time of changing the function, control signals are selectively inputted, whereby latch unit and program section are electrically coupled to each other, and a data signal stored in program section is outputted from the data latch circuit. With this arrangement, it is possible to easily change the function of an FPGA without rewriting program data.

Abstract: An output buffer circuit that compensates for ambient temperature changes facilitates more consistent current drive capacity across a range of ambient temperatures. The number of output buffer stages utilized to generate the data output signal is varied in response to changes in ambient temperature.

Abstract: A semiconductor memory device having a bitline coupling scheme capable of preventing sensing speed from lowering due to variations in an external power supply is provided. The semiconductor memory device includes a memory cell array which includes a plurality of memory cells, a bitline and a complementary bitline which are connected to the memory cell array, a coupling capacitor one end of which is connected to either the bitline or the complementary bitline and the other end of which a control signal is applied to, a bitline sensing amplifier which senses and amplifies a difference in the voltage between the bitline and the complementary bitline, and a control circuit which generate the control signal. Here, an internal power supply generated by dropping an external power supply applied from the outside of the semiconductor memory device is used as a power supply of the control circuit.

Abstract: A regulated charge pump, regulated by a plurality of capacitor boost stages and separate from the memory device supply voltage (Vcc), generates a regulated voltage (VSA) over a range of supply voltages. The regulated charge pump powers sense amplifier and differential amplifier circuits of the memory device to permit a low bit line bias voltage. The differential amplifier circuit generates a logical output to indicate a memory cell programmed state that is detected by the sense amplifier circuit.

Abstract: A semiconductor memory device minimizes a data accessing time. For the purpose, it includes a first control signal generator for producing a first control signal by logically combining a pipelatch-in signal and a start-odd start-even data output control signal, a second control signal generator for producing an odd control signal by logically combining an odd data enable signal for outputting odd-numbered data and a control signal for accessing the odd-numbered data in response to a start address, and generating an even control signal by logically combining an even data enable signal for outputting even-numbered data and a control signal for accessing the even-numbered data in response to the start address, a first accessing unit for accessing input data in response to the first control signal, a latch for temporarily storing data outputted from the first data accessing unit, and a second accessing unit for secondly accessing the data stored at the latch, thereby outputting secondly accessed data.

Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.