Abstract: An ion implantation system contains, in the ion implantation chamber, a workpiece holder that scans vertically while tilting a wafer at an angle of rotation that is rotated out of a perpendicular orientation with respect to the axis of projection in an ion beam. The implant angle into an implant surface on wafer that is retained by the workpiece holder is adjusted by selective rotation of the workpiece holder about its path of motion. A Faraday cup scans the ion beam along the intended location of the implant surface to form a setup measurement plane. The ion beam quality is adjusted to enhance beam uniformity along the setup plane according to these tilt-angle measurements. A charge neutralizing device, such as a flood gun, is moved in operational alignment with the workpiece.

Abstract: A compact infrared (IR) scene generator capable of generating multiple-color mid-IR scenes through the use of readily available commercial near-IR lasers and a fluorescent conversion material (FCM). Such a scene generator would be useful to test IR imaging sensors in a controlled laboratory environment. In operation, each laser emits energy at an initial wavelength outside the operating band of an IR imaging sensor. This energy of a first set of wavelengths is written onto the FCM in patterns, which collectively form an IR scene. The FCM absorbs the energy and radiates it at wavelengths longer than the initial wavelengths, i.e., a second set of wavelengths. As these longer wavelengths are within the operating waveband of the IR imaging sensor, the patterns written onto the FCM are detectable by it.

Abstract: Substantially pure uranium hexafluoride is shipped in a conventional overpack. A cylinder includes a vessel with a cylindrical sidewall A head permanently affixed to the sidewall closes one end of the vessel. A valve controls the flow of matter into and out of the vessel. A sealing surface connected to the vessel surrounds the valve. A cap covers the valve and a pair of seals is located between the sealing surface and the cap. The volume between the two seals, the cap and the sealing surface defines a test volume. A test port connects the test volume and an exterior surface of the vessel, and fasteners press the cap against the sealing surface. A maximum rate of leakage from within the cap to the atmosphere outside the cap is determined by measuring the leakage rate into the test volume with a leak testing apparatus connected to the test port. Thereafter the cylinder is placed in a conventional overpack.

Abstract: A motive force detection system prevents an overpowering of the movement of a transport box-carrying slidable tray of a FIMS system past a reference location upon detection of improper mating of the transport box to the FIMS system port plate or an obstruction to the movement of the slidable tray.

Abstract: An edge detector with sub-micron accuracy. The edge detector comprises two single mode optical fibers with an optical path between them. One fiber is coupled to a laser light source, and creates a light beam. The other fiber is coupled to an optical power detector. The optical power reaching the optical power detector is determined by how much of the light beam is obscured by an object. Thus the position of the edge of the object may be determined from the optical power measured by the detector. The edge of an object may be positioned automatically according to the optical power measured by the detector.

Abstract: A machine vision method and system for inspecting a material. The system comprises a light source arranged to illuminate the material and an imaging device configured to acquire image data corresponding to at least one characteristic of the material while the material is being illuminated by the light source. An image processor is configured to normalize the image data and to control adjustment of an exposure control level for the imaging device based upon the normalized image data. An exemplary method of implementing the machine vision system may include illuminating a material using a light source and obtaining image data corresponding to the material using an imaging device. The image data may be normalized and the adjustment of an exposure control level of the imaging device may be controlled based on the normalized image data.

Abstract: Initial image data having a pixel size smaller than a pixel size of a final image are obtained by using line sensors arranged in a main scan direction and a vertical scan direction, and the final image becomes of high quality by processing the initial image data to prevent the image from becoming uneven. Integration processing means carries out a first conversion process to convert the initial image data comprising signals detected by the line sensors into data for pixels divided in the main scan direction. The integration processing means carries out a second conversion process in which, whenever the data are obtained for three consecutive pixels in the main scan direction, the data are added to become data for one pixel of the final image. The data for the final image are then subjected to an equalization process such as dark current correction carried out by a correction means.

Abstract: A radiation image readout apparatus for reading out, by use of a line sensor formed of a plurality of photoelectric converting elements arranged in a straight line, a radiation image stored on a stimulable phosphor sheet etc., wherein the occurrence of a Moiré effect in the final image is controlled by preventing feedback distortion, is provided. A focusing optical system formed of a first lens array for causing a stimulated emission to become a parallel luminous flux and a second lens array for focusing the parallel luminous flux onto a dichroic mirror and line sensor for transmitting the parallel flux is provided. The refraction ratio of the second lens array and the positional relation of the second Selfoc lens array and the dichroic mirror are adjusted so that the MTF is 50% or less of the Nyquist frequency determined by the width of the direction X of the photoelectric converting elements.

Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

Abstract: A new and improved bonding pad having separate areas for probe needle contact and wire bonding in semiconductor packaging technology. The bonding pad typically has a generally elongated, rectangular configuration with a wire bonding area at one end and a probe needle contact area at the other end of the pad. At least one notch mark may be provided on or adjacent to the bonding pad between the wire bonding area and the probe needle contact area for demarcating these areas during chip production.

Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a crystallization-promoting catalyst is introduced.

Abstract: An active matrix driven electro-optical device, such as a liquid crystal device, enabled to add sufficient storage capacitance to pixel electrodes and decrease the diameter of contact holes connecting with pixel electrodes even when a fine pixel pitch is employed. The liquid crystal device has TFTs, data lines, scanning lines, storage capacitor lines, and pixel electrodes provided on a TFT array substrate. Each of the pixel electrodes is electrically connected to one of the TFTs by two contact holes through a barrier layer. A part of a semiconductor layer and each of the capacitor lines sandwich a first dielectric film and constitute a first storage capacitor, while a part of the barrier layer and each of the capacitor lines sandwich a second dielectric film and constitute a second storage capacitor.

Abstract: An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion, a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is realized without increasing the number of masks and the number of processes. In this display unit, a first wiring arranged between a semiconductor film and a substrate through a first insulating film is overlapped with this semiconductor film and is used as a light interrupting film. Further, a second insulating film used as a gate insulating film is formed on the semiconductor film. A gate electrode and a second wiring are formed on the second insulating film. The first and second wirings cross each other through the first and second insulating films. A third insulating film is formed as an interlayer insulating film on the second wiring, and a pixel electrode is formed on this third insulating film.

Abstract: A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.

Abstract: A method for producing a semiconductor substrate of the present invention, includes the steps: forming a first patterned mask containing a material having a growth suppressing effect on a lower substrate; growing a semiconductor crystal on the lower substrate via the first patterned mask to form a first semiconductor crystal layer; forming a second patterned mask containing a material having a growth suppressing effect on or above the lower substrate, the second patterned mask at least having a surface which is positioned at a level different from a level of a surface of the first patterned mask, with respect to a surface of the lower substrate; and growing a semiconductor crystal on or above the lower substrate via the second patterned mask to form a second semiconductor crystal layer.

Abstract: A semiconductor light emitting device includes: a silicon substrate; and a plurality of column-shaped multilayered structures formed on the silicon substrate in such a manner that the column-shaped multilayered structures are insulated from one another, the column-shaped multilayered structures being made of a nitride semiconductor material, and each column-shaped multilayered structure including a light emitting layer, wherein the column-shaped multilayered structures are connected to one another by an electrode.

Abstract: A semiconductor device has a substantially linear array of semiconductor blocks of one conductive type, each includes a diffusion region of the opposite conductive type and a electrode. The array is paralleled by an array of electrode pads, each connected to two semiconductor blocks, being connected to the diffusion region in one of the two semiconductor blocks and to the electrode in the other one of the two semiconductor blocks. The electrode pad can thus activate both semiconductor blocks, activating one semiconductor block when placed at one potential, and activating the other semiconductor block when placed at another potential. Efficient driving with a comparatively small number of electrode pads thus becomes possible.

Abstract: An optical device includes a substrate having a through hole formed therein, and an optical element mounted on the substrate with its optical section being placed to face the through hole, and a light transmissive member disposed at the through hole. Light transmissive under-fill material is provided between the substrate and the optical element and between the light transmissive member and the optical element.

Abstract: A light source including a specific LED and phosphor combination capable of emitting white light for direct illumination. In one embodiment, the light source includes an LED chip emitting in the 380-420 nm range radiationally coupled to a phosphor blend first phosphor selected from the group consisting of (Sr,Ba,Ca,Mg)5(PO4)3Cl:Eu2+ (SECA) and BaMg2Al16O27:Eu2+ with a second phosphor having the formula (Tb1-x-yAxREy)3DzO12 (TAG), where A is a member selected from the group consisting of Y, La, Gd, and Sm; RE is a member selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb, and Lu; D is a member selected from the group consisting of Al, Ga, and In; x is in the range from 0 to about 0.5, y is in the range from about 0 to about 0.2, and z is in the range from about 4 to about 5. The light source thus produced will provide a high quality white light.

Abstract: The tunnel junction structure comprises a p-type tunnel junction layer of a first semiconductor material, an n-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. At least one of the semiconductor materials includes gallium (Ga), arsenic (As) and either nitrogen (N) or antimony (Sb). The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer.

Abstract: A semiconductor device includes an active region with a main semiconductor device section, and a junction-termination region therearound. A first diffusion layer of a second conductivity type is formed in a surface of a first semiconductor layer of a first conductivity type, and extends from the active region into the junction-termination region. A second diffusion layer of the second conductivity type is formed in contact with the first diffusion layer, and extends in the junction-termination region. A first contact electrode is disposed in the active region and in contact with the first diffusion layer, and electrically connected to a first main electrode of the main semiconductor device section. A second contact electrode is disposed in the junction-termination region and in contact with the first diffusion layer, and surrounds the active region. A connection electrode electrically connects the first and second contact electrodes to each other.

Abstract: A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

Abstract: A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1).

Abstract: An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, Von, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.

Abstract: A III nitride multilayer including a given substrate, a III nitride underfilm including an Al content of 50 atomic percent or more for all of the III elements present in the III nitride underfilm, and a III nitride film including a lower Al content than the Al content of the III nitride underfilm by 10 atomic percent or more. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 800 seconds or below at the (100) plane. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 200 seconds or below at the (002) plane.

Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.

Abstract: The solid-state imaging device according to one embodiment of the present invention includes a semiconductor substrate, a plurality of photoelectric conversion regions arrayed in the vertical direction and the horizontal direction on the surface of the substrate, and an electric charge transfer region disposed between the photoelectric conversion regions adjacent in the horizontal direction of the substrate. The substrate comprises a n-type semiconductor substrate, a first p-type impurity region formed on the n-type semiconductor substrate, a semiconductor regions formed on the first p-type impurity region, and a second p-type impurity region disposed below the electric charge transfer region. The photoelectric conversion region and the electric charge transfer region are n-type impurity regions formed on the surface portion of the semiconductor region.

Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.

Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.

Abstract: This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: Disclosed are a DRAM cell having independent and asymmetric source/drain regions and a method of forming the same. The DRAM cell has an asymmetric structure in which source junctions are thick and drain junctions are thin. Therefore, the source/drain junctions have an asymmetric configuration via separate ion injection steps independent from each other, thereby preventing leakage current due to punch-through. Also, it is not necessary to form an ion injection layer for restraining punch-through, and a relatively low value of electric field is applied to the junctions to prolong refresh time. Further, the relatively thick spacer can be formed adjacent to the source regions thereby decreasing GIDL and further reducing electric field.

Abstract: A state of storage of a memory cell is determined based on the capacitance stored in capacitor, and the memory cell includes a transfer gate transistor, a capacitor and first and second inverters cross coupled with each other. The capacitor has one electrode electrically connected to an output node of the second inverter, and the other electrode is electrically connected to an output node of the first inverter. Thus, a semiconductor memory device that does not require refresh operation can be obtained.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.

Abstract: A semiconductor device having a capacitor of an MIM structure and a method of forming the same are described. The semiconductor device includes a semiconductor substrate; a first bottom interconnection formed over the semiconductor substrate; an intermetal dielectric layer formed over the semiconductor substrate; a plurality of openings exposing the first bottom interconnection through the intermetal dielectric layer; a bottom electrode conformally formed on the inside wall of the openings, on the exposed surface of the first bottom interconnection and on the intermetal dielectric layer between the openings; a dielectric layer and an upper electrode sequentially stacked on the bottom electrode; and a first upper interconnection disposed on the upper electrode. According to the present invention, an effective surface area per a unit planar area of a capacitor with an MIM structure is enlarged to increase capacitance thereof.

Abstract: A semiconductor device includes: lower storage node electrodes provided on a main surface of a silicon substrate; a dielectric film provided on the lower storage node electrodes; an upper cell plate electrode provided on the dielectric film; and an interlayer insulating film covering the upper cell plate electrode. The upper cell plate electrode contains ruthenium. The interlayer insulating film has a contact hole reaching the upper cell plate electrode. The contact hole is provided so that the distance between the main surface of the silicon substrate and the bottom face of the contact hole is not less than the distance between the main surface of the silicon substrate and the bottom face of the upper cell plate electrode. A semiconductor device is provided wherein contact defects in the upper electrode and the generation of an area penalty are prevented.

Abstract: In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.

Abstract: The stack-gate flash memory cell structure of the present invention comprises a floating-gate structure with a thinner floating-gate layer being formed in a central portion by using a spacer-formation technique; an implanted region being formed in the central portion of a channel for adjusting threshold-voltage and forming a punch-through stop; and a highly conductive control-gate structure spaced with an intergate-dielectric layer being formed over the floating-gate structure. The contactless NOR-type array of the present invention comprises a plurality of common-source conductive bus lines and a plurality of planarized common-drain conductive islands being integrated with a plurality of metal bit-lines. The contactless parallel common-source/drain bit-line array comprises a plurality of common-source/drain conductive bit-lines and a plurality of metal word-lines being integrated with a plurality of planarized control-gate conductive islands.

Abstract: A non-volatile memory (NVM) array including a plurality of 2-bit NVM transistors arranged in a plurality of rows extending along a first axis, and a plurality of columns extending along a second axis, perpendicular to the first axis. The non-volatile memory array includes a plurality of field isolation regions located in a semiconductor substrate and a plurality of word lines extending over the semiconductor substrate along the first axis, wherein the word lines form control gates of the 2-bit NVM transistors. Oxide-nitride-oxide (ONO) structures are formed between the substrate and the word lines, wherein the nitride layer provides floating gate storage for the NVM transistors. A plurality of H-shaped source/drain regions are defined by the field isolation regions and the word lines, wherein each source/drain region serves as a source/drain for four different NVM transistors in the array.

Abstract: A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer located on the p-type shallow well, a floating gate on one sidewall of the control gate and over the substrate, a tunnel oxide layer between the control gate and the floating gate and between the floating gate and the substrate, a drain and a common source disposed beneath each side of the control gate in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow p-type well, a pocket p-type well in the substrate around the drain and electrically connecting with the shallow p-type well.

Abstract: In a non-volatile memory, the word lines (6) are closely spaced without the usual field oxide or trench isolation between adjacent word lines. In a virtual ground embodiment, the surface area of one cell may be reduced thereby to practically 2F2, F being the minimum photolithographically-limited process dimension. In a NMOS embodiment, in which a nitride layer (8) is used for storing electric charge representing data, the packing density may be doubled evenly, by storing two bits per cell, thus reducing the area to F2 per bit. This can be achieved by reversing the read current with respect to the write current.

Abstract: The present invention relates to a high-voltage semiconductor component having a semiconductor substrate of a first conduction type on which a semiconductor layer is provided as a drift path that takes up the reverse voltage of the semiconductor component. The semiconductor layer is either of the first conduction type or of a second conduction type that is opposite the first conduction type. The semiconductor layer is more weakly doped than the semiconductor substrate. Laterally oriented semiconductor regions of the first and second conduction types are alternately provided in the semiconductor layer. Furthermore, the present invention relates to a high-voltage semiconductor component having a MOS field-effect transistor that is formed in a semiconductor substrate and has a drift path that is connected to its drain electrode.

Abstract: The present invention relates to a semiconductor device and a fabricating method thereof. The fabricating method comprises: forming an insulating film on a silicon substrate; forming a first conductive well of a first conductive type in the silicon substrate; first and second conductive layers of a second conductive type at a portion below the surface of the first conductive well and in the inner region of the first conductive well, respectively; patterning the insulating film and the first conductive layer of the second conductive type, so that contact holes are formed in such a manner that the second conductive layer formed in the inner region of the first conductive well is exposed through the contact holes; forming a gate insulating film on the sidewall of the first conductive well in the contact holes; and forming a gate electrode on the surface of the gate insulating film in the contact holes.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract: The present invention provides a thin film transistor (TET) and its production method which enable the stabilizing of saturation current and improving reliability by improving the film quality of the channel region. The TFT includes a channel region towering over a gate electrode through a gate insulation film, a source region connecting to the channel region and a drain region connecting to the channel region on an opposite side of the source region are formed on the polycrystal semiconductor film on which island-like patterning is performed. An indented section is formed on a surface of the channel region, and the section corresponding to the indented section becomes a recombination center which captures the small-number carrier (holes) because the degree of the crystallization is low in the section corresponding to the indented section due to shift from the optimum conditions at the time of laser annealing of the semiconductor.

Abstract: In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.

Abstract: A pixel structure comprising a thin film transistor, a pixel electrode, a scan line, a data line and an alignment mark. The alignment mark is formed beneath the data line. Misalignment is assessed through the degree of shifting between the alignment mark and the data line relative to each other. In addition, misalignment is also gauged through the degree of shifting between the alignment mark and the channel layer within the thin film transistor relative to each other.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode