Abstract: A system and a method are provided for bi-directional power conversion in a portable device. The system uses a single inductor to perform both buck and boost power conversion operations and a controller to supply signals to two switches, enabling electric current paths. The system includes a battery connected to ground and to an inductor terminal. The first switch has a terminal connected to a portable device power bus, a second terminal connected to a second inductor terminal, and an input to accept a control signal. The second switch has a terminal connected to the second inductor terminal, a second terminal connected to a portable device ground, and an input to accept a control signal. Controller inputs accept the bus voltage and the battery voltage and outputs supply power conversion control signals to the switches in response to evaluating the bus and battery voltages.

Abstract: In a non-insulated DC—DC converter for performing direct-current power conversion by operating a first MOS transistor and a second MOS transistor in mutually inverted phases, the second MOS transistor is held off during soft-start control. In soft-start control, the on-duty period of the first MOS transistor is short immediately after the switch-on of a power source, and is gradually extended afterwards.

Abstract: A current-sensing and correction circuit having programmable temperature compensation circuitry that is incorporated into a pulse width modulation controller of a buck mode DC—DC converter. The front end of the controller contains a sense amplifier, having an input coupled via a current feedback resistor to a common output node of the converter. The impedance of a MOSFET, the current through which is sampled by a sample and hold circuit is controlled by the sense amplifier unit. A sensed current correction circuit is coupled between the sample and hold circuit and the controller, and is operative to supply to the controller a correction current having a deterministic temperature-compensating relationship to the sensed current. The ratio of correction current to sensed current equals a value of one at a predetermined temperature, and has other values at temperatures other than at that temperature.

Abstract: Method and system for providing current transient control for N electrical devices, numbered (N≧2), where each device has an associated current transient I(n) upon power-up or power-down. Q subsets (preferably mutually exclusive) of devices are provided, where the sum of current transients (in-rush, etc.) for all devices in subset number q (q=1, . . . , Q; Q≧2) is no greater than a selected current value, such as (i) a maximum current that can be supplied by a current source or the maximum current that can be passed through a front end component associated with at least one device without injuring the device and (ii) a maximum current that can be supplied by a current source for power-up. A device may be redundantly assigned to more than one subset, to improve reliability. A time delay is implemented between power-up (or powerown) of any two distinct device subsets. Within an activated subset, a time delay is optionally implemented between any two distinct devices in the subset.

Abstract: A method an apparatus to dynamically modify the internal compensation of a low drop-out (LDO) linear voltage regulator is presented. The process involves creating an additional equivalent series resistance (ESR) from an internal circuit. The additional ESR of the internal circuit is sufficient to ensure DC output stability. This allows the ESR of the output capacitance to be reduced to zero if desired, for improved transient response. The zero induced by the ESR of the internal circuit is frequency compensated, so that it tracks the position of the output pole as the load varies.

Abstract: The invention relates to an energy storage circuitry system, comprising an energy storage element, a voltage boosting circuit for storing an input voltage in the energy storage element, the voltage boosting circuit being used to regulate the input voltage by a varying switching frequency based on a feedback voltage from the energy storage element, a comparison circuit for comparing the voltage in the energy element with a reference voltage to detect if the voltage in the energy storage element achieves a predetermined value for load supplying and generate a control signal, and a charging circuit for supplying power to a load in response to the control signal when the voltage in the energy storage element is detected to achieve the predetermined value.

Abstract: An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.

Abstract: A buffer employs an input stage with an active, LC load. The active load includes integrated inductors that combine with the parasitic gate capacitances of a pair of transistors in a negative-transconductance (−Gm) booster configuration. The resulting active load emphasizes a desired frequency, improving the quality, or “Q,” of the input stage, and consequently of the entire buffer.

Abstract: A test handler apparatus, having a treatment area; a testing station in the treatment area; and an output unit connected to an output of the treatment area. An input unit picks singulated or stripped packages and unloads them on carrier boats in a loading zone; a conveyor mechanism transfers the carrier boats from the loading zone through the treatment area to the testing station and from the testing station to the output unit. In practice, the carrier boat forms a universal carrier which is able to contain multiple singulated or strip packages for the purpose of testing. Placing packages onto carriers with standardized dimension allows handler equipment to accommodate the packages in singulated or strip condition.

Abstract: Methods and devices are provided that allow heads for use in disk drives to be tested in a helium environment in a cost-effective way with little or no impact on test time and with minimal consumption of helium.

Abstract: A method for determining downhole reservoir wettability includes acquiring a first set of NMR measurements of formation fluids in earth formations at a selected axial depth; inverting the first set of the NMR measurements to produce a first distribution of a spin relaxation parameter for a fluid component in the formation fluids; acquiring a second set of NMR measurements of a formation fluid sample removed by a formation fluid testing tool at the selected axial depth, the formation fluid sample being kept at a substantially same pressure and temperature as those of the formation fluids in the earth formations at the selected axial depth; inverting the second set of NMR measurements to produce a second distribution of the spin relaxation parameter for the fluid component in the formation fluid sample; determining the reservoir wettability from a comparison of the first and second distributions of the spin relaxation parameter.

Abstract: An extended Maxwell pair has a pair of cylindrical gradient coils disposed coaxially, carrying equal currents in mutually opposite directions. Each of these gradient coils may be surrounded by a coaxially disposed cylindrically extended shield coil so as to cancel the magnetic field outside. For given values of radii of the gradient and shield coils, the length and the center-to-center separation of the pair of gradient coils are determined by numerically solving an equation which is derived from the condition that the currents through the gradient and shield coils should together generate a magnetic field inside with a linear gradient. The equation to be solved is derived by calculating the magnetic field by a Fourier-Bessel expansion method incorporating the condition that the shield coils do shield the magnetic field inside and cancel the field outside the system.

Abstract: A facility for generating a uniform magnetic field, particularly for generating a basic magnetic field of a magnetic resonance examination apparatus, particularly a medical magnetic resonance tomography apparatus, has a shim device with a guide device to or in which a number of ferromagnetic articles, such as balls, are movably attached. At least two of the articles have ferromagnetic properties differing from one another, such as saturation magnetizations that differ in magnitude from one another. A method for improving the homogeneity of a magnetic field makes use of such a facility.

Abstract: A magnetotelluric geophysical survey system used with an airborne survey bird for natural resource exploration of oil and gas, mineral deposits and aquifers. The survey system uses natural electromagnetic EM fields as an energy source. The magnetotelluric airborne survey system includes an aerodynamic airborne survey bird adapted for being towed behind a helicopter or fixed wing aircraft. The survey system can also be incorporated into a fixed wind aircraft. The survey system includes a non-conductive nose boom on the survey bird with orthogonal electric dipoles for measuring electric fields from 0.01 Hz up to 480 Hz. An angular motion detector is mounted inside the bird and used for compensating for errors caused by angular motion of the bird when in the presence of strong electric field gradients. The survey bird can use a single magnetometer or pairs of magnetometers for measuring electromagnetic gradients.

Abstract: An apparatus and method for reducing crosstalk and other noise sources in downhole tools is disclosed. Due to confined space in the downhole tool environment and the fact that the transmit path utilizes significantly more electrical power than the receive path, electromagnetic noise easily couples between adjacent circuitry. The specification discloses a phase-reversal element that can selectively allow the received signal to pass unaffected, or which can cause a phase reversal of the received signal. A digital signal processor samples the received signal, which after receipt but before sampling has noise induced thereon. Thereafter, the digital signal processor samples the phase reversed received signal, which likewise has the noise induced thereon after receipt but before sampling. Subtracting the first sampled signal from the second produces a resultant signal in which the noise is substantially reduced.

Abstract: System and method for borehole compensation. The method includes simultaneously transmitting at least two modulated signals from one or more transmitters; receiving the at least two modulated signals by at least one receiver; and processing the received at least two modulated signals to determine a phase difference and an amplitude attenuation of the transmitted modulated signals, the processing providing borehole compensated data.

Abstract: A logging tool is disclosed for measuring the resistive anisotropy of formations around a borehole. The logging tool includes a set of electrodes that contact a wall of the borehole. The set of electrodes includes a first pair of current electrodes spaced apart vertically, and a second pair of current electrodes spaced apart horizontally. Between the first and second pair of current electrodes are two or more measurement electrodes that measure a vertical axis voltage difference and a horizontal axis voltage difference caused by currents flowing between the pairs of current electrodes. A resistive anisotropy can be calculated from the measured voltage differences. A third pair of current electrodes oriented perpendicularly with respect to the first and second pair of current electrodes may be provided with corresponding measurement electrodes if it is desired to measure the biaxial resistive anisotropy of the formation.

Abstract: The present invention is a system and method capable of providing continuous measurements of resistivity-through-casing (RTC) of a geological formation traversed by a boreholeby eliminating measurement of the casing resistance. To this end, a real-time feedback control substantially eliminates current flow along the casing in the vicinity of an injection point for injecting a measuring current into the formation. This allows direct estimation of the measuring current injected into the formation along with the casing voltage used to drive the current into the formation. As a result, there is no need for “nulling” or calibration cycle that requires two step measurements with the RTC tool held stationary. The preferred feedback is by the proportional integral derivative procedure (PID) with a digital signal processor that controls bi-directional steerable current sources supplying one or more current to the casing at various points.

Abstract: A method and apparatus for measuring the electrical efficacy of one or more battery cells for use in an uninterruptable power supply are disclosed. The efficacy is determined by making use of the ripple current which flows in the battery cells when in use in the uninterruptable power supply. Simultaneous measurement, for example, of the ripple current and a corresponding voltage component enables the internal impedance of a battery cell to be determined, the impedance acting as an indicator of electrical efficacy.

Abstract: An energy system is formed of a plurality of battery cells, and has an application associated therewith that draws power from the energy system. As the application is being used, voltage and current measurements are taken at a predetermined rate, and stored in a history table to create a series of time-based measurements. The measurements stored in the history table are then processed to compute an impedance parameter value corresponding to the AC impedance of the energy system This impedance parameter value is then stored in a memory buffer where it can be used to carry out various diagnotic and control functions.

Abstract: A tester for verifying the integrity of insulation in a branch circuit of a power distribution system. Two test circuits are included; the first providing an insulation test; and a second, a shared/grounded neutral test. In the insulation test, a 500-volt ac output limited to 5 milliamps is selectively applied to the pairs of wires of the branch circuit. If an output current of greater than 3 milliamps is recorded, an insulation failure is noted and the operator proceeds to the second test which applies a pulsed 3 volt, 1 ampere current-limited voltage across the suspected leads. One of the suspected leads is monitored with a portable ammeter to detect any pulse current.

Abstract: An ASIC (14, 14′, 14″) conditions two independent outputs (VINM, VINP) of a full Wheatstone piezoresistive bridge (12) in separate conditioning paths. Each path is provided with a bridge supply voltage (VHB1, VHB2) which can serve as a temperature related input signal to respective offset and gain compensation control circuits. The half bridge outputs are inputted to respective amplifiers (U1, U2) along with a selected percentage of the temperature dependent bridge supply voltage. The outputs of the amplifiers provide a signal proportional to respective half bridge output voltage. In one embodiment, the output of the amplifier (U2) in one conditioning path of one half bridge is connected to the input of an amplifier (U4) in the other conditioning path to provide a signal in the one path proportional to the Wheatstone bridge differential output voltage and in the other path a signal proportional to the Wheatstone half bridge output voltage.

Abstract: A method and a device for analyzing a sensor device, in which the sensor device forms an electric resonator in an oscillating circuit energized with an external energization voltage. The current in the oscillating circuit is detected in the range of the resonant frequency, and then the current thus detected is multiplied by the external excitation voltage. Finally, the signal obtained by this multiplication is averaged.

Abstract: Techniques for determining the distance between a measuring apparatus and an object are provided. The measuring apparatus includes a transmitter, a receiver and a filter module having a defined phase frequency characteristic, in which a modulated signal, in particular a light signal, is transmitted in the direction of the object by the transmitter, the signal reflected by the object is received by the receiver and the output signal of the receiver is delivered to the transmitter at least via the filter module, wherein at least the transmitter, the receiver and the filter module form a resonant circuit, the frequency of resonance of the resonant circuit is measured and the distance is determined from the frequency of resonance. The respective frequency of resonance of the resonant circuit is determined for at least two different phase frequency characteristics.

Abstract: The invention relates to a capacitive magnetic field sensor. This sensor has a first electrode (2) and a second electrode (3), which are spaced apart from one another and which form a measurement capacitance. The first electrode (2) is situated on a first substrate body (4), and the second electrode (3) on a second substrate body (5). The second substrate body (5) is designed as a deformable membrane in the vicinity of the second electrode (3). A magnetic body (6) is situated in the vicinity of the second electrode (3) and the membrane, and is rigidly connected to the membrane and to the second electrode (3). As a result of this rigid connection, the influence of an external magnetic field on the magnetic body causes not only the magnetic body (6) to change its position but also causes the membrane and the second electrode (3) to change their position, since they are rigidly connected to said magnetic body.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A method, device and software are disclosed which permit testing of both the optical portion and the electrical portion of an imaging device in a live bug configuration. Once an automated handler has positioned the device to be tested, the optical sensor on the image device is illuminated with electromagnetic radiation and electrical test signals are provided through the electrical pins on the integrated circuit package. These electrical and optical tests can be performed in sequence or simultaneously. The automated handler does not need to reposition or disengage from the device under test until both the electrical and optical tests are completed.

Abstract: An apparatus and method are provided for effectively and efficiently testing or burning-in land grid array (LGA) modules, through the use of a self-aligning clamping device for clamping the LGA against a circuit card. The self-aligning clamping device includes a clamping body having an LGA contact surface adapted for bearing against the LGA module, and a pivot element for receiving a clamping force from a ram element selectively movable along a ram axis oriented generally normal to the array of electrical test contacts on the circuit card and transferring the clamping force to the clamping body. The clamping body is also a heat exchanger for maintaining the LGA module at a desired operating temperature during test or burn-in.

Abstract: A conductive composition of titanium boronitride (TiBxNy) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the titanium boronitride is used to construct contact pads such as inline pads, backend pads, sensors or probes. Advantages of embodiments of the titanium boronitride include reduced scratching, increased hardness, finer granularity, thermal stability, good adhesion, and low bulk resistivity. Exemplary methods of creating the titanium boronitride include a sputtering process and a plasma anneal process.

Abstract: A test socket and system for testing packaged electronic circuits. The test system includes a control unit coupled by a communication channel to a socket which provides a location for mounting and testing a packaged electronic circuit. The socket includes one or more designated pairs of electrical connectors that provide power to the packaged electronic circuit. Each of the one or more designated pairs of electrical connectors includes a first electrical connector and a second electrical connector. In one embodiment, the first electrical connector and the second electrical connector in one or more pairs of designated connectors are connected together by a capacitor. In another embodiment, one or more capacitors that connect together the first electrical connector and the second electrical connector in one or more designated pairs of electrical connectors are packaged and embedded in the body of the socket.

Abstract: An object of the present invention is to provide an inspecting device equipped with a probe card capable of inspecting an object to be inspected appropriately even at heating or cooling time. The inspecting device of the present invention is an inspecting device equipped with a performance substrate provided with a terminal for inspection; a contactor substrate provided with a probe contacting an object to be inspected; and a probe card intervening between the probe of conductor substrate and a terminal of performance substrate, wherein the probe card is a multi-layered substrate in which a resin thin film is laminated on a ceramic board.

Abstract: A semiconductor testing apparatus for conducting a conduction test after stabilizing contact between probing pins and a wafer is provided. The semiconductor testing apparatus includes a heat transfer block which is contacted to the probing pins to adjust the temperature of the probing pins to a predetermined testing temperature before the probing pins are brought into contact with the wafer.

Abstract: A test fixture is disclosed for applying force to the surface of a printed circuit board to maintain proper electrical contact between the printed circuit board and an IC package or other electrical component on the opposite side of the board. The fixture employs a link structure to apply force to the board surface while still allowing access to contact points of interest on the side of the board opposite the IC package.

Abstract: Power supply connections to an integrated circuit are tested. The power supply connections are connected to a power supply conductor in the integrated circuit. For the test, combinations of current drawing circuits are switched on near the point where the power supply connection under test is connected to the power supply conductor. The current drawing circuits draw a considerable current, so as to cause a detectable voltage drop over the power supply connection, if this connection is operational. Different subsets of the current drawing circuits are activated successively. To prevent that all of the current drawing circuits are switched on at the same time by error, activation of each subset is controlled by a signal indicative of completion of activation of the preceding subset. A respective signal line is provided for each subset, to provide the signal for the subset.

Abstract: An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures.

Abstract: Disclosed are protection circuitry, and methods of operating the same, for use with clock circuits associated with integrated circuits (ICs). According to one exemplary embodiment, the protection circuitry is operable to generate at least two intermediate clock signals as a function of a received clock signal, and process the at least two intermediate clock signals to (i) cause an output of the protection circuitry to enter a high-impedance state when the at least two intermediate clock signals are different, and (ii) generate a resultant clock signal at the output of the protection circuitry equal to the received clock signal when the at least two intermediate clock signals are identical.

Abstract: A circuit board configured to provide multiple interfaces is disclosed. The circuit board comprises a termination slot inserted with a termination module configured to modulate circuits by applying a termination resistance and a termination voltage. If the termination module is inserted into the termination slot, the circuit board operates as a series stub terminated transceiver logic (SSTL) interface. Otherwise, the board operates as a low voltage transistor logic (LVTTL) interface. Additionally, the board comprises a switch configured to selectively connect a termination resistance to a bus. If the switch connects the termination resistance to the bus, the board operates as an SSTL interface. Otherwise, the board operates as an LVTTL interface.

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Abstract: A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.

Abstract: A low-voltage programmable connector includes two separate paths. Each path includes a buffer and a pair of transmission gates whose control terminals receive the voltages supplied by a memory element associated with that path. If the voltages supplied by the memory elements respectively close the transmission gates in the first path and open those in the second path, signal is transferred from the first terminal to the second terminal of the connector. If the voltages supplied by the memory elements respectively open the transmission gates in the first path and close those in the second path, signal is transferred from the second terminal to the first terminal of the connector. If the voltages supplied by the memory elements open the transmission gates in both the first and second paths, signal transfer between the first and second terminals of the connector is inhibited.

Abstract: An exclusive OR (XOR) circuit is provided to perform a logical XOR function on multiple bits that eliminates the XOR function hazard. The XOR circuit performs a logical XOR function on data values that have been encoded to prevent the XOR function hazard from occurring.

Abstract: Embodiments of the present invention relate to a voltage clamp circuit including a transistor and a switch. The switch is coupled between a gate of the transistor and a source or a drain of the transistor. Embodiments of the present invention can quickly raise and lower a voltage level supplied to a memory device.

Abstract: A current sampling half-bridge output driver capable of driving a wide range of loads using an accurate selection of current sensing resistors. Pluralities of stages are connected in series with the current sensing resistors from each stage connected in series. A range selector selects the stage appropriate for each current load. The reference resistors for a selected stage includes the current sensing resistor associated with that stage added in series to all current sensing resistors electrically connected between the selected stage and the load. The disclosed circuit avoids switching resistors in and out of the circuit and thereby increases the accuracy of the sensing resistor circuit.

Abstract: In a bus circuit which includes a plurality of signal lines, insertion pattern &agr;, which provides repeaters in only an odd numbered series of signal lines, and insertion pattern &bgr;, of which the segment length is equal to that of pattern &agr; and which provides repeaters to only an even numbered series of signal lines, are arranged in an alternating manner in accordance with the length of the signal lines. As a result, the segments during which data signals on the neighboring signal lines run together in opposite phases become half the entire length of the signal lines. Therefore, this bus circuit can prevent the operational speed from becoming slowed.

Abstract: A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.

Abstract: Clocked full-rail differential logic circuits with shut-off include a shut-off device. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: A device for recognizing power sources and associated method are provided. The device for recognizing power sources comprises two voltage-dividing devices. Each of the voltage-dividing devices is coupled to receive native power, and outputs the part of the voltage of the native power. According to the method, an output end of one voltage-dividing device is coupled to a signal end of the controller, and an output end of the other voltage-dividing device is coupled to the other signal end of the controller. When the native power exists, both of the above-mentioned signal ends are in a high voltage level. On the other hand, when native power does not exists, both of the above-mentioned signal ends are at a low voltage level. The power source of the hardware device and the value of the native power can be exactly recognized according to the voltage levels of both signal ends.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network.

Abstract: A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividing circuit, making gms of nMOS and pMOS transistors larger than that could be achieved using the conventional technique. Therefore, frequency dividing performance can be greatly improved in comparison with that achieved using conventional technology.

Abstract: A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.