Abstract: A semiconductor structure is provided that includes a gate, a dielectric spacer located adjacent to a sidewall of the gate, a source/drain region, and a continuous silicide strap located over the gate, the dielectric spacer and the source/drain region. The silicide strap provides an electrical connection between the gate and the source drain region. In one embodiment, the silicide strap is formed by a method that includes the steps of (1) implanting a semiconductor material, such as silicon, into upper surfaces of the gate, the dielectric spacer, and the source/drain region, (2) depositing a refractory metal over the implanted semiconductor material, and (3) reacting the refractory metal with the implanted semiconductor material, thereby forming the continuous silicide strap at the upper surfaces of the gate, the dielectric spacer and the source/drain region. Advantageously, the dielectric spacer does not need to be removed prior to forming the silicide strap.

Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.

Abstract: The present invention is a method for manufacturing a non-volatile semiconductor memory cell of a structure provided with a trap gate between a word line serving as a control gate, and a channel region of a substrate, the trap gate is constructed of an insulating layer and capable of trapping a carrier. The trap gate constructed of the insulating layer can change a threshold of a transistor locally because the carriers injected and trapped inside do not move in the gate. As associated with it, the trap gate does not need to be separated between adjacent memory cells. In addition, the insulating layers for electrical isolation need to be formed on and under the trap gate constructed of the insulating layer. However, the gate insulating layer of the three-layers structure can be formed very thin and highly reliably compared with the conventional floating gate structure.

Abstract: A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder.

Abstract: A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

Abstract: A semiconductor element provided in a semiconductor device includes a built-in contact-type sensor having a sensor area formed on a circuit formation surface. Connection terminals are provided in an area other than the sensor area. A wiring board is connected to the connection terminals of the semiconductor element so that an end surface of the wiring board is positioned on the circuit formation surface. A protective resin part covers a part extending from the end surface of the wiring board to the circuit formation surface so as to protect a connection portion between the semiconductor element and the wiring board.

Abstract: A high performance and small-scale circuitry substrate is described. The circuitry substrate includes a dielectric layer, a return plane attached to a bottom surface of the dielectric layer, and a plurality of return paths (ground) and signal lines that are attached to a top surface of the dielectric layer. The return paths on the top surface are connected to the return plane on the bottom surface by wrapping around at least one edge of the dielectric material. Return paths on the top layer can also separate each pair or adjacent signal lines. The circuitry substrate can be advantageously used to form an optoelectronic module.

Abstract: An image sensor system and methods of making such a system are described. The image sensor system includes a color filter array that is formed by a color filter process that incorporates a bottom antireflection coating. The bottom antireflection coating forms a protective layer that protects exposed areas of the active image sensing device structure during formation of the color filter array and, thereby, preserves the intrinsic transmission characteristics of the active image sensing device structure. The bottom antireflection coating also reduces degradation of metal structures (e.g., bonding pads) and pixel edges at the exposed surface of the active image sensing device structure. In addition, the bottom antireflection coating provides a reliable adhesive surface for the color filter array, substantially eliminating lifting of the color filter array resist structures.

Abstract: Within a method for fabricating a microelectronic, and a microelectronic fabrication fabricated in accord with the method, there is formed upon a bond pad formed over a substrate a conductor passivation layer. Within the method and the microelectronic fabrication, the bond pad is formed from a conductor material selected from the group consisting of aluminum and aluminum alloy conductor materials, and the conductor passivation layer is formed from a noble metal conductor material. The invention provides particular value for fabricating color filter sensor image array optoelectronic microelectronic fabrications with attenuated bond pad corrosion.

Abstract: A high temperature hybrid-circuit structure includes a temperature sensitive device which comprises SiC, AlN and/or AlxGa1-xN(x>0.69) connected via electrodes to an electrically conductive mounting layer that is physically bonded to an AlN die. The die, temperature sensitive device and mounting layer (which can be W, WC or W2C) have temperature coefficients of expansion within 1.06 of each other. The mounting layer can consist entirely of a W, WC or W2C adhesive layer, or an adhesive layer with an overlay metallization having a thermal coefficient of expansion not greater than about 3.5 times that of the adhesive layer. The device can be encapsulated with a reacted borosilicate mixture, with or without an upper die which helps to hold on lead wires and increases structural integrity. Applications include temperature senensors, pressure sensors, chemical sensors and high temperature and high power electronic circuits.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as a support and electrical interconnect for conventional die bonded thereto. Multiple die can be connected to the membrane, which is then packaged as a multi-chip module. Other applications are based on membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A semiconductor isolation structure. The semiconductor isolation structure includes a substrate. A first device and a second device are formed within the substrate. An isolation region is formed within the substrate between the first device and the second device. The isolation region includes a deep region which extends into the substrate. The deep region includes a deep region cross-sectional area. A shallow region extends to the surface of the substrate. The shallow region includes a shallow region cross-sectional area. The deep region cross-sectional area is greater than the shallow region cross-sectional area. For an alternate embodiment, the deep region includes an oxide and the shallow region includes a protective wall. The protective wall can be formed from an oxide and a nitride.

Abstract: A semiconductor apparatus includes a MOS transistor and a resistive element having insulative first polysilicon and conductive second polysilicon films, an insulating film for a resistive element, and a third polysilicon film. The second polysilicon film is formed in a region adjacent each side edge of the first polysilicon film, and has a contact hole formed therein. The third polysilicon film determines a resistance value of the resistive element, and is continuously formed on the second polysilicon film and the insulating film formed on the first polysilicon film. The MOS transistor is formed in an active region surrounded by the field insulating film, and includes a gate oxide film and a gate electrode including a polysilicon film formed as a lower layer with the second polysilicon film and a polysilicon film formed as an upper layer with the third polysilicon film. A method of making this semiconductor apparatus is also described.

Abstract: A semiconductor structure and a method of determining an overlay error produced during formation of the semiconductor structure are disclosed. The semiconductor structure comprises a first two-dimensional periodic pattern and a second two-dimensional periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second two-dimensional periodic patterns indicates the magnitude and direction of an overlay error caused during the formation of the first and second two-dimensional periodic patterns. The semiconductor allows one to independently determine the overlay errors in linearly independent directions by directing a light beam of known optical properties onto the first and second two-dimensional periodic patterns and by analyzing the diffracted beam by comparison with reference data.

Abstract: A semiconductor device comprising: an underlayer interconnect layer; an interlayer dielectric film formed with a connection hole reaching the underlayer interconnect layer; and an upper interconnect layer buried in the connection hole, wherein the interlayer dielectric film includes an insulating film containing an impurity for detecting a first etching end point, a first insulating film, an insulating film containing an impurity for detecting a second etching end point and a second insulating film, these four films being laminated in this order.

Abstract: The present invention integrates an inductor into a semiconductor package by integrally forming inductive segments in the leadframe. The inductive segments may be connected directly to a lead of the leadframe, or indirectly to a lead or a bond pad on a semiconductor die via wirebonds to form an inductor. The inductance value for the resultant inductor is typically controlled by the point of contact for the wirebonds or the leads about the inductive segment. The inductance values may also be controlled by the shape and size of the inductive segments. The leadframe may be formed to support multiple inductive segments, and one or more configurations, including those using one or more die flags to support a like number of semiconductor die.

Abstract: A discrete semiconductor device is vertically sandwiched between an upper wall of a case body and a case bottom plate to be fixed inside a case. The discrete semiconductor device is fitted in the case to be positioned on a predetermined portion inside the case with high accuracy. A space defined by a side surface of the discrete semiconductor device and an inner wall of the case forms a duct for a coolant used for cooling the discrete semiconductor device. The discrete semiconductor device, except main electrodes and signal terminals, is immersed in the coolant. With this structure provided is a power semiconductor device which allows an increase in radiating efficiency of a power semiconductor element and reduction in manufacturing cost.

Abstract: A semiconductor integrated circuit card is disclosed in which such a semiconductor integrated circuit chip device comprising a substrate having a circuit pattern formed thereon, a semiconductor circuit chip bonded onto the substrate and having an electrode connected to the circuit pattern, a reinforcement metal plate, and a seal resin portion for covering a peripheral face of the semiconductor integrated circuit chip and sticking the reinforcement metal plate onto the semiconductor integrated circuit chip is mounted within a card substrate.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.

Abstract: A first microelectronic element such as a semiconductor chip is mounted to a circuit board using an adaptor which has a region extending beneath the first microelectronic element and an additional region which may be folded over the first microelectronic element or which may project laterally from the first microelectronic element. The adaptor includes a functional element in the additional region, such as a further microelectronic element or an array of terminals for mounting another element. The assembly provides the benefits of a stacked chip assembly or other mustachio module, but can be made without the need for a special prepackaged stacked chip assembly. The adaptor can be configured so that it does not materially increase the height of the first microelectronic element above the circuit board.

Abstract: Reinforcing material having Rockwell hardness of 60 or above and comprising base material and adhesive is formed, and then the reinforcing material is attached to one side of silicon wafer on which circuits are not formed prior to dicing.

Abstract: A diode coupling-based arrangement back-biases each of the semiconductor substrates of a plurality of integrated circuits at the maximum (e.g., most negative) DC voltage applied to any individual circuit, irrespective of a potential variation in applied DC voltages. Each semiconductor chip/substrate includes an auxiliary terminal to which each DC voltage terminal for that chip is diode-coupled. The auxiliary voltage terminal is connected to the underside biasing and thermal dissipation pad of the substrate. When multiple packages are mounted and conductively joined to a shared metallic dissipation region of a support substrate, all auxiliary voltage terminals will be connected in common, so as to back-bias each semiconductor substrate to the most maximum (e.g., most negative) of all applied DC voltages.

Abstract: A method of making an integrated circuit device using an encapsulated semiconductor die having leads extending therefrom and attaching a heat spreader to each of the major outer encapsulant surfaces thereof. One or both of the heat spreaders has a pair of end posts configured for allowing further encapsulation of portions thereof and insertion into through-holes in a substrate to position and support the device during and following the outer lead solder reflow step at board assembly. The heat spreaders provide high heat dissipation and EMR shielding, and may be connected to the substrate ground to become ground planes.

Abstract: A power semiconductor package, comprising: a power MOSFET die having a bottom surface with a bottom electrode disposed for contacting a conductor on a support board, and having a top surface with a top electrode; a bump strap which bridges over the power MOSFET die, having mounting portions disposed respectively on opposite sides of the power MOSFET die and disposed for mounting on the support board, and a central portion which engages and is conductively connected to the top electrode of the power MOSFET die. The bottom electrode comprises at least one of a drain electrode and a gate electrode, and the top electrode comprises a source electrode. The bump strap extends upward from the mounting portions to define a respective pair of upper portions of the bump strap which are disposed above the power MOSFET die, the central portion of the bump strap being disposed lower than the upper portions so as to be adjacent to the top electrode of the power MOSFET die.

Abstract: It is an object to provide an electrode structure of a carrier substrate of a semiconductor device in which the strength and the reliability of the joint portion between an electrode of a semiconductor package and an electrode of a main substrate are improved. A soldering land (103) that is an electrode of a carrier substrate (102) is hemispheric having a concentric hemispheric face hollow portion thereinside, a flange portion is provided in the circumferential portion thereof, and the outer diameter of the flange portion corresponds to the outer diameter of the conventional cylinder. Two slits (104) are provided in the flange portion and parts of a wall surface adjacent to the flange portion for venting air. A hemispheric face recess is provided in the carrier substrate (102) toward an outer surface, and the soldering land (103) is fixedly attached to the carrier substrate (102) so that the soldering land (103) is fitted into the recess and the flange portion abuts the outer surface of the carrier substrate.

Abstract: A semiconductor device includes a lower wiring layer, a first insulating layer formed on the lower wiring layer and having a via hole with a width, a via mask layer formed on the first insulating layer and having an opening with a width larger than the width of the via hole, a second insulating layer formed on the via mask layer and having an upper wiring, groove whose width coincides with the width of the via hole, a via contact structure buried in the via hole, and an upper wiring layer buried in the upper wiring groove.

Abstract: Systems and methods are described for sharing signals across a common metal trace on a single metal layer of an integrated circuit. The signals are time division multiplexed across the common metal trace such that a single metal layer of an integrated circuit is used to multiplex signals to and from a poly-silicon layer, reducing utilization of upper metal layers of the integrated circuit.

Abstract: An integrated circuit interconnect is provided having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top and wide bottom metal lines by means of a first via having a width, a second via having a width and spaced more than two widths away and less than four widths away from the first via.

Abstract: A semiconductor device in which a problem such as a thermal diffusion defect in a hollow wiring technique can be solved. In the semiconductor device, a gap is formed between wirings formed on a substrate, and the gap is filled with a gas having a thermal conductivity equal to or higher than three times that of air at 0° C.

Abstract: To significantly reduce parasitic capacitance of component's landing pad, the present invention forms patterned holes in reference potential layers below the pad, thus effectively increasing the dielectric distance between the pad and the reference potential planes below the pad, raising the characteristic impedance of the pad above that of the trace connected to the pad. A controlled amount of parasitic capacitance is re-introduced to the pad by forming at least one grounded metal plate adjacent to the pad, bringing the characteristic impedance of the pad to substantially match that of the trace. The distance of the metal plates from the pad, and the configuration of the patterned holes are predetermined to substantially match the pad's impedance with that of the trace.

Abstract: A semiconductor device includes a first semiconductor chip having a plurality of pads, a second semiconductor chip having a plurality of pads, the second semiconductor chip being fixed over a main surface of the first semiconductor chip, an insulating layer formed between the first semiconductor chip and the second semiconductor chip a plurality of conductive posts formed over the main surface of the first semiconductor chip and a main surface of the second semiconductor chip, the plurality of conductive posts being electrically connected to the plurality of pads on the first semiconductor chip and the plurality of pads on the second semiconductor chip and a resin covering the main surfaces of the first and second semiconductor chips, the resin partially covering the plurality of conductive posts.

Abstract: A microstructure relay is provided, having a body that includes upper and lower portions. The lower portion is formed from a substrate, and the upper portion is formed on the substrate to avoid bonding of the lower portion to the upper portion. A support member is fixed to the body at a first end of the support member to form a cantilever, wherein an upper surface of the support member and a lower surface of the upper portion of the body form a cavity. A first contact region is located on the upper surface at a second end of the support member. The first contact region comprises a first contact, wherein pivoting the support member toward the lower surface causes the first contact to be electrically coupled to a counter contact.

Abstract: An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal wire bonding is coupled to the signal connection point and the signal pad. Two shielding wire bondings are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal wire bonding. The signal trace line is set on the substrate and coupled to the signal connection point. The power ring circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.

Abstract: A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.

Abstract: A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounded by a dielectric. The SRAM cell is small and provides fast read/write access times.

Abstract: A mobile power generation system is provided. The system includes a main trailer having an engine and an electric generator turned by the engine, an air filtration trailer having air filtration equipment for filtering air used as inlet air to the engine, an exhaust trailer having a part of an exhaust silencing system for reducing engine output noise, and an auxiliary trailer having auxiliary equipment for use during operation of the engine.

Abstract: A device is described for generating an electric voltage by which a body of a capacitive and/or inductive sensor capable of vibration, such as a capacitive micromechanical rotational rate sensor in particular, is induced to vibrate. In order to reduce the manufacturing cost of the sensor, a voltage generating device is provided which induces a constant mechanical deflection of the body capable of vibration, this deflection being independent of the manufacturing tolerances of the sensor.

Abstract: Method and system are provided that allow determining in a vehicle having two or more sources of electrical energy what corrective action needs to be undertaken in the event one of the energy sources, due to malfunctions and/or environmental conditions, is not able to carry through a cranking event. The system, by way of a bidirectional DC/DC converter, has the capability to transfer electrical energy in either direction between the energy sources. The system includes a controller configurable with computer-readable logic or intelligence that enables the controller to make a decision based on appropriate source parameters, e.g., temperature, to automatically determine when, where, and how much energy needs to be transferred. This decision will enhance the opportunity to successfully perform the next starting or cranking event.

Abstract: A wave energy converter (WEC), for use in a body of water of depth Dw, includes a tubular structure and a piston within the tubular structure where the relative motion between the piston and the tubular structure is used to generate electric power. The length (L) of the tubular structure may be selected to have a predetermined value based on the fact that: (a) the efficiency of the power generated by WEC increases as the length “L” of the tubular structure increases from a minimal value until L reaches an optimal value; and (b) the efficiency decreases as L is increased beyond the optimal value due to the increased mass of the water that the tubular structure and the piston have to move.

Abstract: A hydro-energy conversion system that comprises a hydraulic turbine rotor, a turbine housing that is rotatably connected to the hydraulic turbine rotor and a turbine cover that is detachably connected to the turbine housing. A mounting flange is connected to the turbine housing. An input plumbing fitting is connected to the turbine housing. An output plumbing fitting is connected to the turbine housing. A generator is coupled to the hydraulic turbine rotor.

Abstract: The present invention provides a system and building for generating electricity using wind power. The invention includes an enclosure, a wind turbine/generator and two or more air ducts. The enclosure, which is to be mounted within or in close proximity to a building, has an air intake and an air exhaust has an air intake and an air exhaust. The wind turbine/generator generates electricity from the wind received form the air intake and is disposed within the enclosure between the air intake and the air exhaust. Each air duct has a first end connected to an air duct intake device and second end connected to the enclosure air intake.

Abstract: The electrical system of an engine-powered outdoor machine is made more flexible in design with a virtual multi-pole switch comprising a microprocessor coupled to power-controlled devices of the electrical system, a single-pole switch coupled to an input of the microprocessor, and a program of the microprocessor simulating one or more interconnected multi-pole switches embodied in hardware and the wiring harness.

Abstract: The invention relates to a motor-vehicle key, comprising a key housing (2, 3), in which an emergency key (5) is stored. The key housing (2, 3) has a cover shell (2) and a divided base shell (3) which is configured as two base-shell sections (3a, 3b). The emergency key (5) is fixed to one of the base-shell sections (3a) by its key head (7), whilst the other base-shell section (3b) has a shaft recess (8) for the key shaft (9).

Abstract: A dual battery system includes a starter battery and a battery of the vehicle electric system, a starter and electric consumers that are divided up into start-relevant consumers and consumers of the vehicle electric system. At least one starter switch is interposed between the starter and the starter battery. A first, electronically fully locking switch element is interposed between the starter battery and the start-relevant consumers and a second electrically fully locking switch element is interposed between the battery of the vehicle electric system and the start-relevant consumers. An element is interposed between the starter battery and the battery of the vehicle electric system that prevents the flow of current from the starter battery to the battery of the vehicle electric system and the consumers of the vehicle electric system.

Abstract: A string set of series-connected incandescent bulbs in which substantially all of the bulb filaments in the set are individually provided with a shunt circuit which includes a voltage responsive switch which is inoperative during normal operation of the string set when connected to a source of operating potential and which becomes operative only in response to an increase in the voltage thereacross which exceeds its rating, and in which the remaining bulbs of the circuit continue to receive substantially rated current therethrough and substantially rated voltage thereacross and further continue to be illuminated at substantially constant illumination even though other or substantially all of the other bulbs in the string are either inoperative or are missing from their respective sockets.

Abstract: A power management system for semiconductor manufacturing prevents malfunctions of loading devices when transient power interruption occurs by maintaining power to the facilities for a period of time after the transient power interruption occurs. The system includes an emergency cutoff circuit, a first power controller, and a second power controller. The emergency cutoff circuit prevents trips in a power relay for one second at the time of transient power interruption. The first power controller discharges a DC voltage for a predetermined time period when AC power is not supplied through a power supply line thereto due to transient power interruption. The second power controller receives the DC voltage provided from the first power controller and discharges the DC voltage during a transient power interruption.

Abstract: An interface between software and hardware, as well as a fuzzy logic control algorithm, for controlling a DC-DC converter or an AC-DC or DC-AC inverter are provided. A control circuit receives commands from a control logic to operate a converter or inverter in various operation modes. Control software inputs can be translated into signals to operate the converter or inverter. Control variables in the control software can be configured to operate under various control modes. If the converter or inverter cannot simultaneously meet the demands placed on two or more variables, the control logic can use prioritization to choose a more important constraint.

Abstract: An electromagnetic switching device includes a contact arrangement with three contacts which couple a three-phase load to three phases of a three-phase power supply system, and disconnect the three-phase load from the three phases. Switching erosion takes place on the contacts. An overall erosion is determined for each contact, and is supplied to a drive circuit. The contact arrangement is operated by the drive circuit as a function of the overall erosion such that the overall erosion of the contacts are approximated to one another.

Abstract: A power supply module for use between an AC/DC power supply unit and an electrical power tool driven by an electric motor and powered by a rechargeable battery pack which has a normal operating voltage and a higher fully-charged terminal voltage. The module includes an input connectable to the supply unit and an output connectable in parallel to the battery pack, and an operating circuit for delivering DC power from the supply unit to the tool in parallel with the battery pack. The operating circuit provides a DC operating voltage at the output of a value between the normal operating voltage and the fully-charged terminal voltage of the battery pack, and provides an output current limited to a predetermined value. The circuit has a comparator for determining whether the output current is less than or is increasing toward exceeding the predetermined value provides a corresponding control signal.

Abstract: A linear driving device of compact size capable of fundamentally canceling a reactive force produced in acceleration and deceleration of a slider within the linear driving device. A slider and a stator constitute a linear motor. The stator is supported to move linearly on the base by an air bearing and the slider is supported to move linearly on the stator. When the slider is driven by the stator to move in one axial direction, a reactive force is exerted on the stator in an opposite axial direction to move the stator in the opposite direction, so that substantially no force is transmitted from the stator to the base. A ratio of weights of the stator and the slider is lopsided so that motion strokes of these members are different. Since the reactive force produced in acceleration and deceleration is canceled within the linear driving device and is not transmitted to the base, any undesirable effect is caused outside of the linear driving device.