Abstract: A pulse width detection circuit for accurately detecting a pulse width from an input signal. The detection circuit includes a first filter circuit for receiving the input signal and generating a first processed signal. The first processed signal includes a first component having an AC component of the input signal and a second component having a low frequency component or a DC component of the input signal. A second filter circuit is electrically connected to the first filter circuit. The second filter circuit includes a high pass filter for receiving the first processed signal and generating a second processed signal. A binary conversion circuit is electrically connected to the second filter circuit to receive the second processed signal and generate the binary signal.

Abstract: An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.

Abstract: The present invention enables an IC to have a fast PWM while maintaining the low frequency clock requirement of the temperature measurement. Methods are presented to increase the resolution of the control using a relatively low input clock. According to one method, the numerator and denominator of the PWM duty cycle equation are adjusted to achieve a desired resolution. According to another method, a determined number of PWM cycles are used to set the PWM duty cycle. For example, an averaging of 1024 duty cycles may be used to achieve an increased resolution of the duty cycle as compared to using only one duty cycle. According to yet another method, an error integrating loop is used to determine the level of the next cycle. The number of cycles used to reach the target PWM duty cycle depends on the desired resolution.

Abstract: A variable delay circuit delays a first input signal in accordance with a delay adjustment signal and outputs the delayed signal as a first delay signal. A decision circuit outputs, in accordance with a phase difference between the first delay signal and a clock signal, an increase or decrease signal. A delay adjustment circuit generates, in accordance with the increase or decrease signal, the delay adjustment signal to adjust the variable delay circuit. Accordingly, even when a discrepancy in timing between the first input signal and clock signal occurs due to a change in temperature, a fluctuation in voltage or the like, a first receiver circuit can receive the first input signal in synchronization with the clock signal without fail. Since the valid period of the first input signal relative to the clock signal can be minimized, the transmission rate of the first input signal can be increased.

Abstract: Methods include receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract: A rectifying circuit and method to produce a DC output by rectifying a sinusoidal source having a plurality of output phase voltages and a plurality of phase-to-phase voltages, the rectifying circuit including a bridge circuit coupled to the output phase voltages, the bridge circuit having a plurality of switches; and a control circuit coupled to the output phase voltages and to the bridge circuit, the control circuit being configured to control the switches in accordance with respective absolute values of the phase-to-phase voltages; wherein the output phase voltages are rectified to produce the DC output. When the sinusoidal source is inductive, switch turn-off may be timed to provide synchronous rectification related to estimates of source periodicity.

Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.

Abstract: A steering circuit for a programmable circuit employing programming voltages that exceed normal operating voltages comprises a plurality of steering transistors. At least one steering transistor has its gate driven by a bootstrapping transistor.

Abstract: A charge pump device for supplying a boosted voltage to a memory device includes a charge pump part constructed with first to nth unit charge pumps, and a multi-level detector for detecting a level of a boosted voltage to selectively drive the unit charge pumps in accordance with an amount of power consumption of the host and thereby outputting at least one level detection signal.

Abstract: In the disclosed semiconductor integrated circuit, a plurality of power supply terminals of the logic circuit block are connected to the actual power supply line via the leak current cut-off circuit. When the logic circuit block is to be activated, the delay control circuit controls the leak current cut-off circuit to electrically connect the power supply terminal to the actual power supply line with a delay of the predetermined time. Therefore, when the logic circuit block is activated, voltage drop of the actual power supply line can be lowered to a small value and erroneous operation of the other logic circuit block in the activated condition due to the power supply noise can be prevented.

Abstract: A complementary source follower circuit has an N-channel type transistor and a P-channel transistor. The threshold voltage of each transistor is independently controlled by a back bias voltage control circuit so that the input voltage and the output voltage relationship can be made linear without the use of an additional circuit such as a level shifting circuit. Also, power consumption can be reduced when the circuit is in standby mode by using the back bias voltage control circuit to achieve non-linearity. A back bias voltage control circuit can also be used to control the threshold voltage of a transistor in series with a resistance load to reduce power usage.

Abstract: Low noise bandgap references of the type providing a temperature independent output by balancing the proportional to absolute temperature dependence of the difference in base-emitter voltages of two transistors operating at different current densities with the negative temperature coefficient of the base-emitter voltage of a transistor. The bandgap references disclosed reduce the noise characteristic of such references by balancing the difference in base-emitter voltages of a first number of pairs of transistors, each pair having two transistors operating at different current densities, with the negative temperature coefficient of the base-emitter voltage of a second number of transistors, the second number being less than the first number. Various embodiments are disclosed, including embodiments having an output corresponding to the bandgap of the transistor material, and multiples of the bandgap of the transistor material.

Abstract: In a semiconductor device, a time-counting circuit counting a prescribed time in transition to a low-power operation mode includes a CR-type time constant circuit and a complementary NOR gate. The time-counting circuit causes electric charges to be released from a capacitive element through a resistance element when a prescribed signal attains L level. As release of the electric charges continues, the NOR gate operates, a power control signal is output at L level, and the semiconductor device makes a transition to the low-power operation mode. Thus, since the time-counting circuit does not include a multi-stage delay circuit and a latch circuit for time-count, power consumption is low, and circuit area is small. Consequently, the semiconductor device capable of transition to the low-power operation mode can simultaneously implement lower power consumption and smaller circuit area.

Abstract: Integrated circuit device that uses tristate switching means to disconnect input/output pins from input buffers during a power down mode, thereby preventing current leakage through partially turned on MOS transistors inside input buffers. A transition detection means connected between the input/output pins and the controlling inputs of the tristate switching means monitors electronic signal at the input/output pins while the chip is in a power-down mode and turns on the tristate switching means when a signal transition is detected.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: In embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalized is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. A similar arrangement including a suitably calibrated equalizer may be utilized to address phase tracking error in a PLL frequency demodulator.

Abstract: A gain control at the input monitors an input signal and a supply voltage, which drives an output. The gain control adjusts the gain to compress the input signal when the supply voltage decreases in magnitude and/or the input signal is of such magnitude to cause the supply voltage to decrease.

Abstract: An amplifying circuit receiving an input voltage and a reference voltage equal to a fraction of the circuit supply voltage, the reference voltage provided by a time constant circuit, including a circuit for, upon power-on, inhibiting the amplifying circuit for as long as the difference between the value of the provided reference voltage and the voltage at the output of the time constant circuit is greater than a determined threshold.

Abstract: A transconductance power amplifier for amplifying a signal to a capacitive load, including a first N-channel enhancement MOSFET transistor operatively arranged to source current to the capacitive load, wherein the first N-channel MOSFET transistor has a threshold gate to source voltage, a second N-channel enhancement MOSFET transistor operatively arranged to sink current to the capacitive load, an operational amplifier operatively arranged to transmit and amplify an input signal to both of the first and second MOSFET transistors, and, means for biasing the first N-channel enhancement MOSFET transistor such that its gate to source voltage is always at or above its threshold when the load draws near zero current so that very little additional gate charge is required to turn it on more fully.

Abstract: One embodiment is a method for adjusting impedance of a power amplifier system comprising combining an output of a first power amplifier with an output of a second power amplifier via a coupler that couples an output connection of the first power amplifier with an output connection of the second power amplifier, wherein a prematching impedance network coupled to the second power amplifier adjusts a system impedance to a first value when the second power amplifier is not actuated, and wherein the prematching impedance network adjusts the system impedance to a second value when the second power amplifier is actuated.

Abstract: The signal generated by a high-power amplifier (HPA) operating in its non-linear region is linearized by an amplifier circuit using feed-forward compensation in which an auxiliary channel relies on a model of the HPA to generate an auxiliary signal that is combined with the HPA output to generate an amplified linearized output signal. The amplifier circuit may be implemented with a pre-distorter in the main amplifier channel to linearize the HPA using both pre-compensation and feed-forward compensation. Using the HPA model in the auxiliary channel enables the auxiliary signal to be generated without directly relying on the HPA output. This enables the amplifier circuit to be implemented without having to delay the high-power HPA output signal prior to being synchronously combined with the auxiliary signal. In preferred embodiments, the auxiliary channel signal is generated using a relatively low-power amplifier operating in its linear region.

Abstract: A differential amplifier and a method for amplifying an input signal are disclosed. The differential amplifier comprises an amplification stage configured to amplify an input signal to produce an amplified output, a current source configured to provide a bias current for the amplification stage, and an impedance network connected to the amplification stage and the current source. The impedance network is configured to provide a high common mode impedance within the range of operating frequencies.

Abstract: A radio frequency (RF) pulse power amplifier biased with a relatively low supply voltage generates one or more RF pulses having a relatively large output power. The RF pulse power amplifier may be configured as a push-pull power amplifier operating in class D mode including first and second sections, balanced-to-unbalanced (balun) transformer, and a load resistor coupled across the output winding of the balun transformer. Each section has a current source providing bias current, a MOS transistor, and a pair of bipolar transistors. Each section receives its input digital signal at the MOS transistor, which acts as a current switch for a bias current from a current source. With a relatively small voltage change in response to the input digital signal, the MOS transistor switches the bias current between itself and a transistor pair used to drive the corresponding half (input winding) of the balun transformer.

Abstract: A bias controller sets the quiescent current of a power amplifier to a desired value by dynamically adjusting the power amplifier bias voltage. Using closed-loop control, the bias controller sets the bias voltage to whatever value is needed despite circuit component variations and temperature effects. Operation of the bias controller complements dynamic bias voltage adjustment in advance of transmit operations, such as in advance of a transmit burst. In a first state, where the power amplifier is in a quiescent condition, the bias controller adjusts bias voltage to set the desired quiescent current by detecting the supply current into the power amplifier. The bias controller then transitions to a second state, where it maintains the adjusted bias voltage irrespective of amplifier supply current. Despite its ability to sense supply current into the power amplifier, the bias controller's configurations avoid dissipative current sensing during normal operation of the power amplifier.

Abstract: A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A frequency lock loop has a reloadable N counter that counts cycles of an output frequency during one cycle of a reference frequency. A VCO generates the output frequency. A VCO control drives the VCO based on the count from the counter. The VCO control may include a latch for latching the count at each reference frequency cycle. The VCO control may include a VCO driver, such as a D/A converter or proportional charge pump, connected to a voltage control as input to the VCO. The counter may be reloaded with the integer N value at each cycle of the reference frequency. The counter may decrement from the integer value at each cycle of the output frequency. A lock may occur at N times the reference frequency without regard to phase between output and reference frequencies.

Abstract: A microwave oscillator includes a transistor for oscillation, an insulating substrate on which the transistor is mounted, a first strip conductor which is attached to the insulating substrate and which has one end connected to the output terminal of the transistor, and a second strip conductor which is attached to the insulating substrate and which has one end connected to input terminal of the transistor. The microwave oscillator further includes a TE01-mode dielectric resonator which couples with the first strip conductor and the second strip conductor, and a varactor diode. The varactor diode has one end connected to the other end of the first strip conductor or the other end of the second strip conductor, and the other end is RF-grounded, such that the capacitance of the varactor diode can be changed.

Abstract: A self-biased voltage controlled oscillator (VCO) that includes a VCO core including a plurality of switching transistors, a resonant tank circuit operatively coupled to the VCO core, a current source operatively coupled to the VCO core for supplying a bias current to the VCO core, and a biasing circuit operatively coupled to both the resonant tank circuit and to the current source. The biasing circuit and the switching transistors of the VCO core cooperatively function to bias the current source, whereby the VCO is self-biased.

Abstract: A pulse width modulation circuit of the present invention includes: pulse generation means being provided with a first power supply and charged with a first current and a second current between which a constant current is distributed to turn ON/OFF a switching element, thereby generating a pulse from a first output section; pulse modulation means for controlling the charging while controlling a distribution ratio between the first current and the second current based on an input signal, thereby changing a pulse width of the output pulse; and first short circuit means for shorting the first output section with the first power supply when the pulse being output from the first output section transitions to a voltage of the first power supply.

Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.

Abstract: An electronic component assembly includes an electromagnetic interference (EMI)-producing component capable of generating EMI and an EMI-sensitive component. The electronic component assembly further includes a radiation shunt disposed proximate to the EMI-sensitive component capable of attracting at least a portion of the EMI and, by attracting the at least a portion of the EMI, shielding the EMI-sensitive component from the at least a portion of the EMI. By providing a radiation shunt to shield the EMI-sensitive component, a need is reduced for a mechanical shield that surrounds the EMI-sensitive component.

Abstract: A method for damping an LC filter coupled to a converter and generating a filter signal. The method comprises sensing the filter signal and processing the filter signal to generate a corresponding feedback signal. The feedback signal is subtracted from a controller signal to generate a difference signal. The difference signal is used for damping the LC filter.

Abstract: A compact non-reciprocal circuit device capable of handling a high power without impairment of the characteristics. The non-reciprocal circuit device contains a magnetic substrate that exhibits anisotropic behavior by application of a direct-current magnetic field. On the surface of the substrate, strip-lines are disposed at an angle, being insulated with each other. One end of each strip-line is grounded, and the other end of each is connected through a capacitor to a ground. Of the ends connecting the capacitors, one end connects to a termination resistor; the remaining ends connect each to an input terminal and an output terminal. The non-reciprocal circuit device exhibits non-reciprocal characteristics between the input and output terminals. The case of the device contains an insulating thermal conductor that serves as a heat-radiator for the termination resistor and the strip-lines.

Abstract: A semiconductor device includes a switching element, for example, a Schottky barrier diode, which controls transmission/cutoff of a signal transmitted between two portions of a transmission line. An anode electrode of the switching element is interposed between the two portions of the transmission line and the longitudinal direction of the anode electrode is aligned with the longitudinal direction of the transmission line. A cathode electrode of the switching element is disposed on at least one of the widthwise sides of the anode electrode, and is connected to ground.

Abstract: A microwave circuit utilizes a spiral-like coupler configuration to achieve the functionality of a traditional coupler with higher density and lower volume. A plurality of substrate layers having metal layers disposed on them are bonded to form the package. A plurality of groundplanes may be used to isolate the spiral-like shape from lines extending out to contact pads or other circuitry.

Abstract: A surface acoustic wave duplexer includes a piezoelectric substrate; a transmitting filter formed on the piezoelectric substrate; a receiving filter formed on the piezoelectric substrate; a transmitting (Tx) branching line formed on the piezoelectric substrate; and a receiving (Rx) branching line formed on the piezoelectric substrate.

Abstract: A dielectric filter comprising a dielectric block having first and second opposed surfaces with a width direction and a length direction greater than the width direction. At least three conductive through holes are arrayed in the dielectric block in the length direction. In one embodiment, a sectional shape of at least one conductive through hole located between two other conductive through holes of the at least three conductive through holes is elongated in the width direction. In another embodiment, a sectional shape of two conductive through holes on either side of a third conductive through hole of the at least three conductive through holes is elongated in the width direction. With these arrangements, the jumping coupling capacitance is controlled.

Abstract: An LC high-pass filter circuit device includes an inductor defined by via holes formed in adjacent insulating sheets which are connected in the direction of stacking of the sheets so as to define a single trap inductor. Inductor via holes formed in another insulating sheet define separate high-pass filter inductors. The trap inductor and the high-pass filter inductors have axes which extend substantially perpendicularly to the planes of the insulating sheets. Each of the high-pass circuit inductors defines, in combination with a high-pass filter capacitor, a high-pass filter circuit, while the trap inductor defines, in combination with a capacitor, a trap circuit. The high-pass filter circuits and the trap circuit in combination define a small-sized LC high-pass filter circuit device which exhibits high Q value and which excels in frequency characteristics, as well as a laminated LC high-pass filter device, a multiplexer and a radio communication apparatus incorporating the LC high-pass filter circuit device.

Abstract: A space is defined in a portion of an overlapping region where an open end portion of a resonant electrode and an inner-layer ground electrode, of a dielectric layer which is interposed between the resonant electrode and the inner-layer ground electrode. A space is defined in a portion of an overlapping region where the open end portion of the resonant electrode and another inner-layer ground electrode, of a dielectric layer which is interposed between the resonant electrode and the other inner-layer ground electrode. These spaces are filled with respective members having a dielectric constant higher than the dielectric layers.

Abstract: By using a method for manufacturing a dielectric laminated device, an opening is formed on a first dielectric sheet, a strip line and an input and output line including an input and output electrode are formed by burying electrode materials in said opening, the first dielectric sheet is laminated with the second and third dielectric sheets disposed above and below respectively to form a laminate, a first and second shield electrodes and a ground electrode are formed, an end of the strip line is connected to the ground electrode, the first shield electrode and the second shield electrode are mutually connected through the ground electrode, and the input and output electrode is exposed along the line direction of the strip line. By this constitution of the above dielectric laminated device, the mounting reliability of the dielectric laminated device can be further increased.

Abstract: Asymmetric support for high frequency transmission lines. An asymmetrical support structure coaxially supports a center conductor over a ground plane using a dielectric material. Absorbing material between the dielectric and the outer conductor reduces the effects of high order modes.

Abstract: An object of the present invention is to provide a relay in which an external lead-out terminal portion can be arranged in an optional position so as to constitute an in-line terminal while forming a base and performing a sealing operation easily. Horizontal portions are formed by bending terminal portions of coil terminals of an electromagnet block, and the horizontal portions are laid along the under face of a base to arrange the terminal portions and other terminal portions in a line.

Abstract: The invention relates to a relay designed with integral parts to simplify assembly, reduce manufacturing costs, and increase strength. The relay has a coil base member. The coil base member has a base member and a coil member integrally connected. The base member has an upper side, side faces and a bottom surface. The coil member has inner sides. The coil base member has a side opening that extends from the inner sides of the coil member to the upper side of the base member and to the side faces and bottom surface of the base member.

Abstract: An electromagnetic switching relay having a base member and a magnetized coil. The base member having first guide elements. The magnetized coil having a terminal and second guide elements positioned substantially between the first guide elements that engage the first guide elements. A partition layer that allows displacement of the magnetizing coil relative to the base member before the second guide elements engage the first guide elements and fixes the second guide elements to the first guide elements when the base member and the magnetized coil are pushed toward each other.

Abstract: A magnetic clamping arrangement (10) for holding the arrangement, and in particular a body (5), operably clamped with respect to a ferromagnetic surface (6) by way of a body datum face (8), comprises housing (12) mounted on the body, and electromagnet (16) carried by the housing. The electromagnet comprises a core (18), having three limbs 20.1, 20.2 and 20.3, each terminating in a pole face 22.1, 22.2 and 22.3, being formed by a plurality of ferromagnetic transformer laminations (26). stacked together and slideable with respect to each other in a direction to and from the pole faces. Lamination bias (36), in the form of masses 38, 40.1 and 40.2 of resilient compressible material, defined quiescent pole faces from which individual laminations may depart by sliding when forced against a surface having ridges and/or grooves extending in the lamination planes, but exerts a restoring force on such laminations so displaced.

Abstract: A magnetic field generator for confining plasma within a vacuum chamber is disclosed. The magnetic field generator produces a multi-pole magnetic field around a workpiece positioned within the vacuum chamber. The magnetic field generator is provided outside the vacuum chamber and comprises a plurality of segment type permanent magnets circularly arranged. The magnetic field generator further comprises a plurality of magnetic members to which the segment type permanent magnets are selectively attached.

Abstract: Transformer cores, especially those of wound or laminated annealed amorphous metals which include support assemblies are disclosed. Methods for their manufacture, and their use in assembled transformers are also disclosed.

Abstract: An inductor module includes a common inductor core and an inductor winding. The inductor winding includes a plurality of inductor winding sections, each of which has a first end and a second end, and each of which is wound on the common inductor core. The inductor winding further includes a common contact interconnecting the second ends of the inductor winding sections.

Abstract: One configuration of the present invention is a radio frequency transformer board that has a planar dielectric substrate having a first surface, an opposite second surface, and a transformer. The transformer includes a first elongate conductor disposed on the first surface and having a first end and a second end, a second elongate conductor disposed on the second surface and having a first end and a second end. The first end of the first conductor and the second end of the second conductor are disposed proximate an edge of the substrate and spaced apart from one another along the edge. The second end of the first conductor and the first end of the second conductor are electrically shorted to one another proximate the edge of the substrate.