Abstract: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A diode region on the second face is configured to emit light in the predetermined wavelength range, into the substrate upon application of voltage across the diode region. A mounting support on the diode region, opposite the substrate is configured to support the diode region, such that the light that is emitted from the diode region into the substrate, is emitted from the first face upon application of voltage across the diode region. The first face of the substrate may include therein a plurality of grooves that define the plurality of triangular pedestals in the substrate. The grooves may include tapered sidewalls and/or a beveled floor.

Abstract: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer consisting of either an n-type nitride-based semiconductor layer or a nitride-based semiconductor substrate having a wurtzite structure and thereafter forming an n-side electrode on the etched back surface of the first semiconductor layer.

Abstract: A semiconductor device, such as a pin diode, includes a first drift layer, a second drift layer, an anode layer on the first drift layer, and a buffer layer formed between the first and second drift layers. The shortest distance from the pn-junction between the anode layer and the buffer layer, and the thickness of the buffer layer are set at the respective values at which a high breakdown voltage is obtained, while reducing the tradeoff relation between the soft recovery and the fast and low-loss reverse recovery.

Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

Abstract: An n− type layer 12 is epitaxially grown on one main surface (front surface) of an n+ type silicon substrate 11 and an anode electrode 13 is electrically in contact with the other main surface (rear surface) thereof. A p type region 14 is selectively formed in a surface layer of the n− type layer 12 and a n+ type region 15 is selectively formed in a surface layer of the p type region 14. A cathode electrode 17 is electrically in contact with a surface of the n+ type region 15.

Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: A semiconductor device includes a continuous doped substrate with a surface, a sulfur-based dielectric material layer positioned on the surface of the continuous doped substrate, a dielectric material layer positioned on the sulfur-based dielectric material layer, and a gate contact region positioned on the sulfur-based dielectric material layer. The continuous doped substrate includes silicon (Si) and the sulfur-based dielectric material includes a transition metal sulfide such as strontium zirconium sulfur (SrZrS), barium zirconium sulfur (BaZrS), strontium hafnium sulfur (SrHfS), barium hafnium sulfur (BaHfS), or the like. Further, the gate contact region includes a layer of one of strontium titanium sulfur (SrTiS), barium titanium sulfur (BaTiS), or the like positioned adjacent to the dielectric material layer.

Abstract: A bipolar heterojunction transistor (HBT) includes a collector layer, a base layer formed on the collector layer, a first transition layer formed on the base layer, an emitter layer formed on the first transition layer, a second transition layer formed on the emitter layer, and an emitter cap layer formed on the second transition layer. Each of the first and second transition layers is formed of a composition that contains an element, the mole fraction of which is graded in such a manner that the conduction band of the HBT is continuous through the base layer, the first and second transition layers, the emitter layer and the emitter cap layer.

Abstract: A semiconductor chip has a circuit block, a power supply line and a ground line. A condenser chip in which a noise reduction condenser connected to the circuit block is stacked on the semiconductor chip. Because the condenser chip is stacked on the semiconductor chip, it is not necessary to provide a noise reduction condenser on the semiconductor chip and also not to provide a noise reduction condenser on a substrate on which the semiconductor chip is mounted.

Abstract: A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

Abstract: An active matrix light emitting device which is capable of clear color display of multiple gray scales is provided. The light emitting device has a pixel portion, and the pixel portion has a plurality of pixels. Each of the plurality of pixels has an EL element, a first EL driver TFT, a second EL driver TFT, a switching TFT, and an erasure TFT. The first EL driver TFT and the second EL driver TFT are connected in parallel.

Abstract: An active pixel sensor for producing images from electron-hole producing radiation includes a crystalline semiconductor substrate having an array of electrically conductive diffusion regions, an interlayer dielectric (ILD) layer formed over the crystalline semiconductor substrate and comprising an array of contact electrodes, and an interconnect structure formed over the ILD layer, wherein the interconnect structure includes at least one layer comprising an array of conductive vias. An array of patterned metal pads is formed over the interconnect structure and are electrically connected to an array of charge collecting pixel electrodes. A radiation absorbing structure includes a photoconductive N-I-B-P photodiode layer formed over the interconnect structure, and a surface electrode layer establishes an electrical field across the radiation absorbing structure and between the surface electrode layer and each of the array of charge collecting pixel electrodes.

Abstract: The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewall of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is formed in the recess and the top surface of the barrier layer is recessed below the top surface of the oxide or oxide/nitride layer. The process continued with a formation of an oxidation resistant conductive layer and the deposition of a further oxide layer to fill remaining portions of the recess.

Abstract: In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL2a) are formed on a first layer, and lines M2 (e.g., M2a) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL1c) are formed on the first layer, and lines M2 (e.g., M2c) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M2 on the second layer can have a smaller line interval.

Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.

Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

Abstract: A semiconductor device includes: a digital circuit including a first capacitive element of metal-insulator-metal structure, and an analogue circuit including a second capacitive element of metal-insulator-metal structure. Bottom electrodes, capacitive insulation layers, and top electrodes of the first and second capacitive elements are formed in the same or common processes to each other. The bottom electrodes are electrically connected with contacts in an underlying inter-layer insulator. The top electrodes are electrically connected with other contacts in an overlying inter-layer insulator.

Abstract: A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.

Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.

Abstract: A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.

Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.

Abstract: A method for manufacturing a flash memory comprises forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric and forming a first conductive layer on the first dielectric layer. Next step is to pattern the first dielectric layer, the first conductive layer and the substrate to form a trench in the substrate. An isolation is refilled into the trench, a portion of isolation is removed to a surface of the first conductive layer. A portion of the first conductive layer is removed, thereby forming a cavity between adjacent isolation. A second conductive layer is formed along a surface of the cavity and the isolation, next, a portion of the second conductive layer is removed to a surface of the isolation. Subsequently, a second dielectric layer is formed on a surface of the floating gate, a third conductive layer is formed on the second dielectric layer as a control gate.

Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and a transition region that extends between the drift region and a first surface of the semiconductor substrate. The transition region has a vertically retrograded doping profile therein that peaks at a first depth relative to the first surface. An insulated gate electrode is provided that extends on the first surface and has first and second opposing ends. First and second base regions of second conductivity type are provided in the substrate. The first and second base regions are self-aligned to the first and second ends of the insulated gate electrode, respectively, and form respective P-N junctions with opposing sides of an upper portion of the transition region extending adjacent the first surface. First and second source regions are provided in the first and second base regions, respectively.

Abstract: The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si-film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: A semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device includes a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. The second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is equal in depth to the second well. The second and third wells are formed down to a level lower than the device isolation structure.

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract: Diffusion barrier film layers and methods of manufacture and use are provided. The films comprise boron-doped TiCl4-based titanium nitride, and provide an improved diffusion barrier having good adhesive, electrical conductivity, and anti-diffusion properties. The films can be formed on a silicon substrate without an underlying contact layer such as TiSix, an improvement in the fabrication of contacts to shallow junctions and other miniature components of integrated circuits.

Abstract: A thermoelectric semiconductor has a P-type semiconductor and an N-type semiconductor disposed in parallel. A heat absorbing side of the thermoelectric semiconductor and a substrate that has an optical element mounted on its upper surface are disposed on the same plane. A heat radiation side of the thermoelectric semiconductor is disposed such that a direction from the heat absorbing side to the heat radiation side of the thermoelectric semiconductor is parallel with the upper surface of the substrate. Based on this arrangement, it is possible to set the environmental temperature of an optical module to the same level as the operation temperature of a laser diode.

Abstract: A base of an optoelectronic device is disclosed. The present invention comprises an opening and a reflective surface. The base of the optoelectronic device incorporates with a transparent conductive substrate and an optoelectronic element to construct the optoelectronic device, wherein the optoelectronic element is disposed on the transparent conductive substrate, and the opening is used to hold the optoelectronic element. Moreover, the transparent conductive substrate is placed on the top of the opening, and the reflective surface is located at the bottom in the opening.

Abstract: A photodetector device includes a doped semiconductor substrate. A first intrinsic semiconductor material layer, a main reflector, a second intrinsic semiconductor material layer, an upper semiconductor material layer, which is doped the opposite as the substrate, are formed in succession on the semiconductor substrate. An upper electrode is formed on and electrically connected with the upper semiconductor layer, and a lower electrode is electrically connected to the semiconductor substrate. One of the intrinsic semiconductor layers is relatively thin to absorb incident light, while the other is relatively thick. The photodetector device, a p-i-n photodetector, has an I region including the intrinsic semiconductor layers with different thicknesses, and a main reflector therebetween. The thickness of the entire I region can be increased with a reduced transit distance for holes.

Abstract: An optical semiconductor device includes: a photo detector section which includes: a first semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, and an antireflection film formed on a surface of the second semiconductor layer and preventing reflection of incident light; and a circuit element section which includes: a circuit element formed on the second semiconductor layer on the semiconductor substrate, and a passivation film covering an uppermost electrode layer among electrode layers constituting the circuit element and formed out of a same material as a material of the antireflection film.

Abstract: An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

Abstract: In a manufacturing process of an SOI structure semiconductor device in which an MOS capacitor is located on an SOI substrate, the capacitor insulating film of the MOS capacitor is prevented from degrading due to a bimetal effect, which is caused by a thermal treatment and characteristic to the SOI substrate. A trench is formed to surround the MOS capacitor in the SOI substrate, thick oxide films are formed on sidewalls defining the trench, and the trench is filled with polysilicon to complete a trench isolation layer. Because the thick oxide films have a coefficient of thermal expansion that is different from that of a silicon semiconductor layer of the SOI substrate, the thick oxide films are able to prevent the capacitor insulating film from degrading in film quality due to the thermal treatment in the manufacturing process. As a result, an SOI semiconductor device in which an MOS capacitor on an SOI substrate offers performance comparable to an MOS capacitor on a silicon substrate can be formed.

Abstract: An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first and a second end separated by a programmable link. The first end of the one-time programmable element is coupled to a power supply voltage node in the package. The second end of the programmable element may be coupled to an external package connection (e.g., a package pin) and/or to an internal package node that connects to an input terminal of the integrated circuit die when the integrated circuit die is mounted in the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Abstract: The invention concerns an intgrated inductor (20), consisting of a flat winding of one or several turns (21, 22, 23) made of a conductive material above a substrate provided with at least a subjacent conductive level wherein is produced, through a contact pick-up strip (12′), at least an intersection of the winding, the width of at least one turn and/or one interval between two turns being reduced in line with said contact pick-up strip.

Abstract: The present invention reduces the capacitance components of pads to improve high frequency characteristics. An optical module includes a light emitting element having an electrode to which a bias current is supplied, an interconnect substrate on which an interconnect pattern is formed to supply the bias current, and a ferrite bead inductor having one terminal connected to a pad connected to the electrode using a bonding wire and the other terminal connected to a pad as the interconnect pattern.

Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p−-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.

Abstract: The present invention is directed to a novel semiconductor device, which can be efficiently fabricated for use in Zener diode applications. Precision Zener diodes and the method for manufacturing the same are provided. The Zener diodes of the present invention are made from a semiconductor substrate layer having a range or resistivity, on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device.

Abstract: A unit cell is disclosed that facilitates the creation of a layout of at least a portion of a microelectromechanical system. The unit cell includes a plurality of electrical traces. Some of these electrical traces pass through the unit cell. Other electrical traces extend only part way through the unit cell. At least certain boundary conditions exist for the unit cell that allow the same to be tiled in a row and in a manner that results in adjacently disposed unit cells in the row being electrically interconnected in the desired manner.

Abstract: A chip electronic component including a ceramic element and terminal electrodes with metal coating thereon formed on the surface of the ceramic element. A glass layer is formed on a part of the surface of the ceramic element where the terminal electrodes are not formed. A glass material for the glass layer contains at least two species of alkali metal elements selected from Li, Na and K, and the total amount of the alkali metal elements is greater than or equal to 20 atomic percent of the total amount of elements except oxygen contained in the glass material.

Abstract: A stereolithographically fabricated package that surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. The package may be fabricated from thermoplastic glass, other types of glass, ceramics, or metals. Stereolithographic processes are used to fabricate at least a portion of the substantially hermetic package around the semiconductor dice of assemblies including carrier substrates or leads or around bare or minimally packaged semiconductor dice, including on dice that have yet to be singulated from a wafer. As at least a portion of the substantially hermetic package is stereolithographically fabricated, that portion may include a series of superimposed, contiguous, mutually adhered layers of a suitable hermetic material. The layers can be fabricated by consolidated selected regions of a layer of unconsolidated particulate or powdered material, or by defining an object layer from a sheet of material.

Abstract: The invention relates to an integrated circuit provided with a set of contacts for connecting the integrated circuit to a differential transmission line. The set of contacts comprises at least one first pair of contacts intended to receive a first power supply voltage, a second pair of contacts intended to receive a second power supply voltage and a third pair of contacts, referred to as signal contacts, intended to be connected to the transmission lines. Each power supply contact may indifferently receive ground or one of the high or low power supply voltages, realizing two possible power supply configurations, positive or negative. The signal contacts are surrounded by the power supply contacts so as to realize a specific shielding which is independent of the positive or negative power supply configuration.

Abstract: A die package is formed, which allows additional electrical connections to the die by using internal leads or traces from a lead frame. The internal leads are exposed through an upper or lower surface of the package, thereby allowing an additional die package to be stacked and electrically connected to the underlying die or additional inputs/outputs to underlying external circuitry, such as a printed circuit board.

Abstract: A resin-molded device of an aspect of the present invention includes a plurality of electronic elements spaced from each other. It also has a plurality of lead members, each one of the lead members electrically connecting to the corresponding one of the electronic elements. Further, it has a plurality of metal blocks spaced from each other so that a plurality of channel portions are defined between the metal blocks. Each of the metal blocks is arranged so as to correspond to at least one of the electronic elements and the lead members connected to the electronic element. The resin-molded device includes a resin package of electrically insulating material molded so as to hold together the plurality of the electronic elements, the lead members, and the metal blocks. The resin package includes a plurality of resin inlets through which fluid resin is injected, and wherein each of the resin inlets opposes to the corresponding one of the channel portions.

Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.