Patents Issued in January 16, 2007
  • Patent number: 7164298
    Abstract: A slew rate enhancement circuit of an operational amplifier including a main output stage, a monitoring stage and an assistant output stage is provided. An input voltage of the operational amplifier is detected by the main output stage to decide whether to output a main current to the load or not. The main output stage also generators a first push signal and a first pull signal according to the input voltage, and thereafter the second push signal and second pull signal are level shifted by the monitoring stage. A second push signal and second pull signal will turn on or turn off the assistant output stage to decided whether to output an assistant current to the load or not. Specially, the improved compact circuit does not increase state operating current for the original operational amplifier and occupy a small chip area.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: January 16, 2007
    Assignee: Novatek Microelectronics Corp.
    Inventor: Kuang-Feng Sung
  • Patent number: 7164299
    Abstract: An output buffer circuit having a so-called pre-emphasis function of emphasizing a signal waveform in data transmission in an information processing device or the like according to an attenuation of a transmission line, includes a first buffer which receives input of an input signal which gives a logical value of a signal to drive the transmission line and a second buffer which drives the transmission line in cooperation with the first buffer, thereby cutting off, at the time of de-pre-emphasis when the pre-emphasis function is disabled, current flowing through the second buffer.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: January 16, 2007
    Assignee: NEC Corporation
    Inventor: Takaaki Nedachi
  • Patent number: 7164300
    Abstract: A power-low reset circuit is provided. The power-low reset circuit receives a reset signal outputted from a power on reset circuit and a stored voltage of a capacitive device in the power-on reset circuit provides an electrical path when a power voltage drops under a predetermined voltage level. The power-on reset circuit is used for generating the reset signal at an initial moment of turning on a power source. The capacitive device can be discharged or charged through the electrical path to restore to its initial status.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: January 16, 2007
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Po-Chin Hsu
  • Patent number: 7164301
    Abstract: A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: January 16, 2007
    Assignee: Freescale Semiconductor, Inc
    Inventor: Christopher K. Y. Chun
  • Patent number: 7164302
    Abstract: A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input node, the output node, and the data clock line. A mirror primary latch element is connected to the input node in parallel with the primary latch element, to the storage node, and to the data clock line. A weak keeper is connected to the storage node and to the not storage node. A strong enabled tri-state keeper is connected to the not storage node, to the data clock line, and to the output node. The input node is either a dynamic data input node or a static data input node. Optionally, the weak keeper is also clock enabled.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: January 16, 2007
    Assignee: Sun Microsystems, Inc.
    Inventor: Ilyas Elkin
  • Patent number: 7164303
    Abstract: A delay circuit generates an output signal by delaying an input signal, and includes a ferroelectric capacitor having a first end and a second end, a means for inverting a polarization of the ferroelectric capacitor by producing an electric potential difference between the first end and the second end based on an electric potential of the input signal and a generation means for generating the output signal by delaying the input signal based on a change in an electric potential of the second end caused by the polarization inversion.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: January 16, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Kenya Watanabe
  • Patent number: 7164304
    Abstract: A duty ratio correction circuit includes: a first switching amplifier circuit into which an input pulse signal is input; a current control device connected with the switching device for controlling a current in accordance with a bias voltage signal; a waveform shaping circuit that correct an output of the first switching amplifier circuit; a first integration circuit that integrates a corrected output; a reference voltage setting unit that sets a reference voltage signal defining a duty ratio; a comparator circuit that compares an output of the first integration circuit with the reference voltage signal; a second switching amplifier circuit that includes a switching device connected in series with a constant current circuit, the switching device using a comparison judgment signal as a gate signal; and a second integration circuit that integrates an output of the second switching amplifier circuit and outputs the bias voltage signal.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 16, 2007
    Assignee: Yamaha Corporation
    Inventor: Yasuhiko Sekimoto
  • Patent number: 7164305
    Abstract: The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: January 16, 2007
    Assignee: STMicroelectronics PVT. Ltd.
    Inventors: Sushil Kumar Gupta, Paras Garg
  • Patent number: 7164306
    Abstract: In a composite multiplexer circuit designed to multiplex plural frequency bands by interconnecting plural multiplexer circuits in parallel, a multiplexer circuit for extracting a frequency band of a GPS reception system includes a matching network including an inductor and a capacitor, and a surface acoustic wave filter connected in series with the matching network. The multiplexer circuit for the GPS reception system can be so set as to have infinite impedances at the other frequency bands than the frequency band thereof. This prevents signals in the other frequency bands from leaking into the multiplexer circuit for the GPS reception system.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: January 16, 2007
    Assignee: Kyocera Corporation
    Inventor: Yutaka Makino
  • Patent number: 7164307
    Abstract: A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Stephen H. Tang, Victor Zia, Badarinath Kommandur, Siva G. Narendra, Vivek K. De
  • Patent number: 7164308
    Abstract: A bandgap voltage reference circuit comprising a first circuit providing a first voltage representative of to Vbe of a first bipolar transistor, a second circuit providing a second voltage ?Vbe representative of the difference of two Vbe voltages of two bipolar transistors, and a comparator having respective inputs receiving voltages representative of Vbe and ?Vbe and an output coupled to the base of the first bipolar transistor whereby a voltage representative of the sum of respective constants multiplying Vbe and ?Vbe is provided at the output of the comparator.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: January 16, 2007
    Assignee: International Rectifier Corporation
    Inventor: Chik Yam Lee
  • Patent number: 7164309
    Abstract: A voltage multiplier circuit includes a control circuit and a first voltage multiplier stage. The control circuit receives a power supply voltage and a reference voltage and provides a first output voltage being the difference between a first selected voltage and the power supply voltage where the first selected voltage is a function of the reference voltage and is independent of variations in the power supply voltage. The first voltage multiplier stage receives the first output voltage and a clock voltage signal having a clock voltage value and provides a second output voltage being the sum of the first output voltage and the clock voltage value. When the clock voltage value is equal to the power supply voltage, the second output voltage of the first voltage multiplier stage is the first selected voltage independent of any power supply voltage variations.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: January 16, 2007
    Assignee: Micrel, Inc.
    Inventors: Paul Smith, John Shaw
  • Patent number: 7164310
    Abstract: The present invention is directed toward a system and apparatus for digitally controlling a bias control signal for at least one transistor. The present invention provides for software writable registers that control the bias control signal. The present invention further provides for the bias control signal to be temperature compensated based upon a temperature signal and a temperature profile stored in software writable registers. The present invention further provides for software control of the initialization and configuration of the bias control signal through stored program control of the values in the software writable registers.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: January 16, 2007
    Assignee: Integration Associates Inc.
    Inventors: Jean-Luc Nauleau, Janos Erdelyi, William H. McCalpin
  • Patent number: 7164311
    Abstract: A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 16, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Golam R. Chowdhury, Douglas R. Holberg
  • Patent number: 7164312
    Abstract: A circuit for audio amplification includes an amplifier and a first input resistor. The amplifier is arranged to provide an amplifier output signal that is based, in part, on a capacitively-coupled audio input signal. The capacitively-coupled audio input signal is based, in part, on an input RC value. The input RC value is given by the input capacitance times the input resistance. The input resistance is reduced during the turn-on in order to achieve a fast turn-on time with minimal pop-and-click noise. Also, the input resistance is increased to its normal value after the turn-on so that full audio fidelity is substantially maintained during normal operation.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: January 16, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Raminder Jit Singh, Ansuya P. Bhatt
  • Patent number: 7164313
    Abstract: Circuits, methods, and systems are provided for opening a primary feedback loop in a transmitter. An auxiliary feedback loop can be closed when the primary feedback loop is opened, and a controller can match a gain of the primary feedback loop to another gain in the transmitter.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 16, 2007
    Assignee: Aspendos Communications
    Inventors: Peter Capofreddi, Derek K. Shaeffer, Sriraman Dakshinamurthy, Korhan Titizer
  • Patent number: 7164314
    Abstract: A power amplifier module for amplifying radio frequency signals includes a radio frequency power amplifier including one or more semiconductor transistors, adapted to receive an input radio frequency signal and power control signals, and to output an amplified radio frequency signal. The power amplifier module is integrated with input and output impedance matching networks and a power sensor that is adapted to receive the amplified radio frequency signal and to output a signal indicating the power output level of the power amplifier module. The power amplifier module also includes control logic in accordance to at least one of the qualities and the power level of the amplified radio frequency signal.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: January 16, 2007
    Assignee: Micro Morio Corporation
    Inventors: Ikuroh Ichitsubo, Guan-Wu Wang, Weiping Wang
  • Patent number: 7164315
    Abstract: A method for measuring the forward power output of an amplifier with improved accuracy with a mismatched load based on probing the amplitude of the AC voltage and current in the final amplifier stage. Amplitudes are combined resulting in a composite reading that is affected less by load mismatch. Variations include measuring signal amplitude at two points 90 degrees apart in the transmission medium and measuring the power supply voltage and current of a saturated amplifier.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: January 16, 2007
    Assignee: Avago Technologies Wirleless IP (Singapore) Pte. Ltd.
    Inventors: Lovell H. Camnitz, Bartholomeus Hendrik Jansen, Ray Myron Parkhurst, Jr.
  • Patent number: 7164316
    Abstract: Provided is a series type Doherty amplifier which includes a first power amplifier and a second power amplifier using a plurality of transformers. The first power amplifier and the second power amplifier are connected in series. The second power amplifier and a first transformer are connected in series. A first path is branched from a junction between the first power amplifier and the second power amplifier and a phase delay device and a second transformer are connected in series. An output port of the second transformer is connected to a junction of a second path of an output port of the second power amplifier. An efficiency of each power amplifier is determined by a ratio of 1:M in size of a final stage of each of the first and second power amplifiers.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: January 16, 2007
    Inventors: Junghyun Kim, Joo-Min Jung
  • Patent number: 7164317
    Abstract: An op amp is arranged for low-voltage, rail-to-rail operation with a class AB output. The op amp includes a transconductance input stage, a folded cascode middle stage that includes a split cascode, a high-side driver, a low-side driver, a sampling circuit, and a split-cascode bias circuit. The split cascode includes two cascode transistors with their sources coupled to each other. Also, the sampling circuit that is arranged to sample the high-side driver current and the low-side sample current. The split cascode bias current is arranged to compare the sample current with a reference current, and to provide bias voltages to the gates of the two cascode transistors in the split cascode.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: January 16, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Perry Scott Lorenz
  • Patent number: 7164318
    Abstract: Continuous variable-gain low-noise amplifier. The amplifier continuously adjusts its gain between well-defined high and low values by using a cascode current-steering circuit to partition signal current between two different nodes of an output loading network. A shunt feedback network connected from an intermediate node of the loading network to the input provides negative feedback that linearizes the amplifier as its gain is decreased. The circuit degrades the noise figure at lower gains by varying the gain without directly dumping the signal current to the power supply. The circuit produces only small changes in input and output impedances and preserves an improved reverse-isolation cascode characteristic as the gain is controlled.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: January 16, 2007
    Assignee: Sequoia Communications
    Inventors: Damian Costa, Joseph Austin, John Groe, Michael Farias
  • Patent number: 7164319
    Abstract: A power amplifier comprises an input terminal, an output terminal and a first amplification stage coupled with the input and output terminals. The first amplification stage having a node and a resistive structure coupled with the node. The resistive structure includes a first resistive circuit coupled with the node; and an adaptation circuit coupled with the first resistive circuit such that when the first amplification stage is in a first mode, the resistive structure provides a first effective resistance and when the first amplification stage is in a second mode, the resistive structure provides a second effective resistance.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: January 16, 2007
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Darren W. Ferwalt
  • Patent number: 7164320
    Abstract: A current threshold circuit includes a series impedance, a reference voltage source, and a comparison module. The series impedance couples an output of a current source to a load, wherein impedance of the series impedance is substantially less than impedance of the load. The reference voltage source is operably coupled to produce a reference voltage differential. The comparison module is operably coupled to compare the reference voltage differential with a differential voltage of the series impedance, wherein the comparison module generates an excessive current indication when the differential voltage of the series impedance compares unfavorably to the reference voltage differential.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: January 16, 2007
    Assignee: Sigmatel, Inc.
    Inventors: Matthew D. Felder, Marcus W. May
  • Patent number: 7164321
    Abstract: A power amplifier includes a transconductance stage and a modulation detection and bias determination module, and may include a cascode stage. The modulation detection and bias determination module operably couples to the transconductance stage and to the cascode stage when present and is operable to detect modulation characteristics of an signal operated upon by the transconductance stage. The modulation detection and bias determination module is also operable to controllably bias the transconductance stage and/or the cascode stage when present based upon detected modulation characteristics. The detected modulation characteristics are typically determined based upon a measured signal level, e.g., voltage level, current level, or power level, of the signal operated upon by the transconductance device. For non-constant envelope modulations, the signal level varies over time with the modulation envelope. The operational characteristics of the power amplifier, e.g.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: January 16, 2007
    Assignee: Broadcom Corporation
    Inventor: Arya Reza Behzad
  • Patent number: 7164322
    Abstract: A technique for establishing a tuning signal window for a multi-band VCO involves setting the tuning signal window to an initial size, preferably a relatively small size, and determining whether the VCO is churning. When the VCO is determined to be churning, the tuning signal window is expanded until the VCO stops churning. In an embodiment, the tuning signal window is expanded incrementally until the tuning signal window is large enough to include a solution, where a solution is defined as an operating point along a frequency band that satisfies both the setpoint frequency and tuning window signal requirements. The tuning signal window can be set at an offset relative to the tuning signal zero to compensate for shifts in the frequency bands that may result from changes in operating conditions.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: January 16, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Thomas Allen Knotts, Gunter Willy Steinbach
  • Patent number: 7164323
    Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: January 16, 2007
    Assignee: Qualcomm Incorporated
    Inventor: Beomsup Kim
  • Patent number: 7164324
    Abstract: A CMOS single-ended frequency doubler with improved subharmonic rejection and low phase noise which allows a single ended reference signal to be utilized in a Balanced Colpitts oscillator. The input is reproduced with a 180-degree phase shift for the opposite Colpitts transistor. This is achieved by adding two PMOS transistors. One transistor is placed as a follower, which reproduces any voltage shift applied to its gate to its source. Another transistor is a matching transistor for balance. By applying the single-ended signal to the gate of the follower transistor, it is reproduced at the source. The rest of the circuit takes advantage of the summing of two period currents with a 180-degree phase shift. The present invention achieves superior performance for frequency doubling due to the squaring of the gate voltage in the corresponding drain current. As a result, the double frequency component is further enhanced.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: January 16, 2007
    Assignee: Phaselink Semiconductor Corporation
    Inventor: Pierre Paul Guebels
  • Patent number: 7164325
    Abstract: A Voltage Controlled Oscillator (VCO) in a battery-powered device, such as a cellular phone, can be configured to tune across a fairly wide frequency range using a relatively narrow control voltage range. The frequency response of the VCO can be temperature compensated by applying a temperature variable voltage source to varactors that form part of a VCO resonant circuit. The reference end of the varactor can be supplied with a temperature dependent voltage source that has a temperature dependence that substantially compensates for varactor temperature dependence. The temperature dependent voltage source can be a Proportional To Absolute Temperature (PTAT) device.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: January 16, 2007
    Assignee: Qualcomm Incorporated
    Inventors: Vladimir Aparin, Yue Wu
  • Patent number: 7164326
    Abstract: The oscillator circuit comprises an oscillator including an oscillating transistor through which an oscillating current flows; a first mirror transistor where the source/drain of which is grounded and the drain/source of which is connected to the oscillating transistor in series; a first reference transistor where the source/drain of which is grounded and the drain/source and the gate of which are connected in common to the gate of the first mirror transistor; a second mirror transistor where the source of which is connected to a power line and the drain/source of which is connected to the drain/source of the first reference transistor; and a second reference transistor where the source/drain of which is connected to the power line, the drain/source and the gate of which are connected in common to the gate of the second mirror transistor and the drain/source of which is connected to an external terminal to which an external resistor is connected.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: January 16, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Makoto Sakaguchi
  • Patent number: 7164327
    Abstract: A simplified compensation matrix is set up for the compensation of phase errors between the I and the Q component in data transmission systems with quadrature modulation or demodulation. This simplified compensation matrix permits a previously determined phase error ?? to be used as the basis for replacing two of the multipliers required in the conventional circuit configurations by relatively simple shift registers (4, 5) for a multiplication by 1 or by a constant.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 16, 2007
    Assignee: Infineon Technologies AG
    Inventor: Stefano Marsili
  • Patent number: 7164328
    Abstract: Various embodiments of a direct digital amplitude modulator (DDAM) for modulating radio frequency (RF) or intermediate frequency (IF) or baseband signal with the invented interpolation technique are disclosed. The interpolation technique greatly reduces the amplitudes of alias signals without using an analog filter. The embodiments therefore are significant for various communication transmitters to achieve simple structure, good linearity and high power efficiency.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: January 16, 2007
    Assignee: Infineon Technologies Wireless Solutions Sweden AB
    Inventors: Jiren Yuan, Yijun Zhou
  • Patent number: 7164329
    Abstract: The present invention provides a phase shifting filter and a phase compensating direct downconversion receiver. A DC offset detector detects a DC offset in a received baseband signal and provides a feedback signal. A tunable filter phase shifts a local oscillator signal responsive to the feedback signal. The phase-shifted local oscillator signal is used to directly downconvert a received RF signal, whereby DC offset in the resulting baseband signal is reduced.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: January 16, 2007
    Assignee: Kyocera Wireless Corp.
    Inventors: Stanley S. Toncich, Raymond Curtis Wallace
  • Patent number: 7164330
    Abstract: Provided is a broadband phase shifter using a coupled line and parallel open and short stubs. The broadband phase shifter of the present research has a new switching network structure by forming a coupled line, main transmission lines and parallel ?/8 (45°) open and short stubs on both ends of the main transmission lines in order to obtain broadband phase characteristic that the phase difference between two networks is uniform.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: January 16, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Soon-Young Eom
  • Patent number: 7164331
    Abstract: An RF choke for minimizing hum modulation in a coaxial cable system that carries broadband signals along with high amperage 60 Hz AC power signals. The choke contains two conductors wound about a rod core. The first conductor includes two groups of clockwise windings each containing three turns. The second conductor wound counterclockwise also contains two groups of winding one of which contains four turns and the other of which contains three turns. The two connectors are separated by a space of about 0.20? and a 750 ohm resistor is placed in parallel over the second group of winding in the first conductor and a second 510 ohm resistor is placed in parallel over the first group of windings in the second conductor.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 16, 2007
    Assignee: National Electronics Devices Inc
    Inventor: Prabhakara V. Reddy
  • Patent number: 7164332
    Abstract: Inside a multilayer dielectric substrate, there are a spiral-shaped first slot set in a part of a first ground conductor layer and a spiral-shaped second slot in a part of a second ground conductor layer put on the front surface of the multilayer dielectric substrate, the first slot and the second slot are opposite in a spiral winding direction and the first slot and the second slot overlap with each other as viewed from the top face, so that a resonance phenomenon can be produced at a frequency lower than a resonance frequency of a resonator with a conventional structure.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: January 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Kanno, Kazuyuki Sakiyama, Ushio Sangawa, Tomoyasu Fujishima
  • Patent number: 7164333
    Abstract: A standing wave barrier for at least one radio frequency cable having a cable axis has at least one metallic base web that proceeds parallel to the cable axis from a first web end to a second web end. The web ends are coupled to one another in terms of radio frequency terms via a capacitance, so that the base web and the capacitance together form a radio frequency resonant oscillator circuit. The base web and the capacitance are situated in one of two half-shells that can be connected to one another such that the radio frequency cable is clamped between them. The capacitance has an adjustable capacitor element that has a first capacitor surface and a second capacitor surface. The first capacitor surface is connected in electrically conductive fashion to the first web end, and the second capacitor surface is connected in electrically conductive fashion to the second web end.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: January 16, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helmut Greim, Jürgen Hagen
  • Patent number: 7164334
    Abstract: The present switch including the present actuator has a supporting column on a substrate, and a cap plate provided on the supporting column. The supporting column pivotally supports the cap plate. At ends of the cap plate, a plurality of beams are provided, respectively. The plurality of beams are subjected to electrostatic force of absorbing electrodes. According to the present switch, tilting directions of the cap plate (beams) can be set freely. Therefore, by providing the beams in a plurality of directions desired by a user and positioning the absorbing electrodes on the substrate so that the absorbing electrodes respectively correspond to the beams, the cap plate can be tilted in a plurality of desired directions. With this arrangement, the present switch has high degree of freedom as to the positions and number of substrate contact points.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 16, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuhiko Shirakawa
  • Patent number: 7164335
    Abstract: A three-position push-pull switch assembly is disclosed that includes two magnetic reed switches mounted to a circuit board located within the switch housing. A magnet is mounted to an actuator that extends into the switch housing and is axially translatable from a center position to a pushed in position and a pulled out position. When in the center position, the two magnetic reed switches are in a first closed-open operational state. When force is applied to the actuator shaft to move it into the pushed-in position, the reed switches are in a second closed-open operational state. Similarly, when force is applied to move the actuator shaft to the pulled out position, the magnetic reed switches are in a third closed-open operational state.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: January 16, 2007
    Assignee: G.T. Development Corporation
    Inventor: Alan K. Forsythe
  • Patent number: 7164336
    Abstract: The invention relates to an actuator for actuating a valve installed in a hydraulic or compressed air system comprising a coil support which can be displaced by means of air space induction in a magnetically conducting housing on a magnetic cylinder composed of a permanent magnet and a cylinder pole disk. The invention is characterized in that the dimensions of the permanent magnet and the pole disk correspond to each other in such a way that the diameter of the front surface of the permanent magnet is at least the same size as the circumferential surface of a neighboring pole disk and that the width of the coil associated with the pole disk exceeds the width of the pole disk by the lift amplitude of the coil support.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: January 16, 2007
    Assignee: Parker Hannifin GmbH & Co. KG
    Inventors: Hartmuth Rausch, Peter-Klaus Budig, Ralf Werner
  • Patent number: 7164337
    Abstract: A splash proof electromagnetic door holder is sealed to prevent failures caused by exposure to moisture. The electromagnetic door holder comprises a ground box, a main housing attached to the ground box, and a coil assembly attached to the main housing. The coil assembly includes a bobbin containing a wire coil. A sealant, preferably epoxy, covers the face of the bobbin to prevent moisture from entering the coil assembly. A seal is incorporated between a coil passage in the main housing and the coil assembly. Seals are included between the main housing and the ground box. The resulting the electromagnetic door holder resists the entry of moisture into the electromagnetic door holder and thereby improves the reliability of the electromagnetic door holder.
    Type: Grant
    Filed: December 11, 2004
    Date of Patent: January 16, 2007
    Assignee: RSG/Aames Security, Inc.
    Inventor: Andrea Furia
  • Patent number: 7164338
    Abstract: An energy transfer element having an energy transfer element input winding and an energy transfer element output winding. In one aspect, the energy transfer element input winding is capacitively coupled to the energy transfer element output winding. The energy transfer element is capacitively coupled to electrical earth. One or more additional windings are introduced as part of the energy transfer element. The one or more additional windings substantially reduce capacitive displacement current between the energy transfer element input winding and energy transfer element output winding by balancing the relative electrostatic fields generated between these windings and/or between the energy transfer element and electrical earth by canceling the electrostatic fields generated by all windings within the energy transfer element relative to electrical earth through the selection of the physical position and number of turns in the additional windings.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: January 16, 2007
    Assignee: Power Integrations, Inc.
    Inventors: Arthur B. Odell, Chan Woong Park
  • Patent number: 7164339
    Abstract: An integrated transformer with a stack structure comprises a middle dielectric layer, a bottom dielectric layer, a first winding and a second winding. A portion of the first winding is disposed over a surface of the middle dielectric layer and the remaining portion of the first winding is disposed over a surface of the bottom dielectric layer. A portion of the second winding is disposed over the surface of the middle dielectric layer and the remaining portion of the second winding is disposed over the surface of the bottom dielectric layer. The second winding doesn't intersect with the first winding. The portions of the first and second windings over the surface of the middle dielectric layer connect with the remaining portions of the first and second windings over the surface of the bottom dielectric through via plugs.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: January 16, 2007
    Assignee: Winbond Electronics Corp.
    Inventor: Kai-Yi Huang
  • Patent number: 7164340
    Abstract: A transformer is constituted of an inner core, a plurality of outer cores connected in a ring to the inner core, a primary winding which is fed with a high frequency wave and wound around the inner core, and a secondary winding wound outside the primary winding. The secondary winding has, for the two outer cores, windings which are caused to pass at least once between the inner core and each of the respective outer cores, and the windings passed in the same direction are connected in parallel. With this configuration, it is possible to achieve a transformer for a switching power supply with a low voltage regulation.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: January 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Nakagawa, Kenji Kawataka, Akeyuki Komatsu
  • Patent number: 7164341
    Abstract: A surface-mountable PTC thermistor element includes electrodes disposed on a top surface and a bottom surface of a thermistor element body, in which each of the electrodes is connected with a terminal respectively and each of the terminals is extended downward. An upper terminal is protected from being detached by a reaction force acting against pressing at the time of press-mounting the PTC thermistor element onto a surface of a substrate. A vertical-leg portion of the lower terminal is placed inside the thermistor element body in the radial direction from the outer edge of the thermistor element body. Preferably, the vertical-leg portion of the lower terminal is placed in the vicinity of the center of the thermistor element body.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: January 16, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takayo Katsuki, Takeo Haga
  • Patent number: 7164342
    Abstract: The present invention relates to a load sensor and provides a highly accurate load sensor with multi-layered wiring at low costs. It provides crystallized glass and non-crystalline glass which are best for a load sensor, and combines these to form multi-layered wiring, and further, makes a glass layer of composite type as needed, and reduces uneven printing in printing multiple layers with use of hardening type paste.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: January 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiichi Nakao, Yukio Mizukami, Hiroaki Ishida, Masaaki Katsumata
  • Patent number: 7164343
    Abstract: A variable potentiometer with a wiper terminal and first and second terminals has relay switches for shorting or for unshorting resistors. When resistance is reduced between the wiper and one of said terminals, resistance is increased between the wiper and another terminal. In one embodiment two strings of resistors with the same nominal values are used between the wiper and the terminals. In another embodiment, a single string of resistors are used and are switched into either the electrical connection between the wiper and the first terminal or between the wiper and the second terminal. When resistance is lowered between the wiper and one of said first or second terminals a first resistor is replaced with a first short circuit and when resistance is increased between said wiper and another of said first and second terminals a second short circuit is replaced with the first resistor.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: January 16, 2007
    Assignee: Avistar, Inc.
    Inventors: Gary Kessler, Michael Garcia, Albert Migliori
  • Patent number: 7164344
    Abstract: A non-contact IC card reading/writing apparatus having a superior reception characteristic includes a loop antenna, a resonant circuit unit, a wireless transmitting unit, and a wireless receiving unit. The resonant circuit unit, the wireless transmitting unit, and the wireless receiving unit are coupled to each other via any one of a directional coupler, a circulator, and an isolator.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: January 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Futoshi Deguchi, Hiroshi Yoshinaga, Akihiko Hirata, Masahiko Tanaka
  • Patent number: 7164345
    Abstract: Disclosed is an apparatus for realizing an alarm function using a mobile terminal and a charging device for charging the mobile terminal. The mobile terminal includes a controller for generating an alarm control signal a predetermined time period ahead of a predetermined alarm time, and a first interface for transmitting the alarm control signal to the charging device. The charging device includes a second interface for receiving the alarm control signal from the mobile terminal, and a lamp driver for generating a lamp driving signal for controlling a lamp in response to the received alarm control signal.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: January 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eung-Jin Park
  • Patent number: 7164346
    Abstract: An internal powerline network is provided with a routing device for routing a signal on only a part of the network. In this way the data capacity of the network is increased. The routing device is advantageously attached to the fuse box of the powerline network.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: January 16, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Bernard Hunt, Richard M. Miller-Smith
  • Patent number: 7164347
    Abstract: A mannequin suitable for use as a hairdressing training tool including a head component, a hair portion, sensors for sensing undesirable characteristics such as high temperature or rapid movement, and signalling means for indicating the same to a user.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 16, 2007
    Inventor: Beverely Nita