Abstract: A CAN package light emitting device comprises a semiconductor laser 1 bonded on a sub mount 6 and a CAN package 2 for housing the semiconductor laser 1 bonded on the sub mount 6. The CAN package 2 comprises a fixing structure 3 for fixing the semiconductor laser at a predetermined position, and a cap 4 covering the semiconductor laser 1 fixed to the fixing structure 3. Vapor pressure of Si organic compound gas in the CAN package 2 is limited to or below 5.4×102 N/m2 to prevent any deposit as thick as inviting characteristics deterioration from being formed on the light emitting portion of the semiconductor laser 1 within the guaranteed time of its proper operation.

Abstract: A semiconductor device includes a first layer, a plurality of first test elements which are arranged in the first layer, a second layer which is different from the first layer and has a first surface and a second surface opposed to the first surface, the first surface of the second layer being adhered to the first layer, an opening portion which is arranged on the second surface of the second layer, and a plurality of pads which are arranged in the second layer and are electrically connected to the first test elements, a part of the pads being exposed from the opening portion.

Abstract: In a photovoltaic device of the present invention, junction characteristics are improved by enhancing interface characteristics between a crystalline silicon semiconductor and an amorphous silicon semiconductor. In the photovoltaic device, an n-type crystalline substrate (11) and a p-type amorphous silicon thin film (13) are laminated with an i-type amorphous silicon thin film (12) interposed as well as an n-type amorphous silicon thin film (15) is provided on a rear surface of the crystalline silicon substrate (11) by interposing an i-type amorphous silicon thin film (14) between them. Oxygen atoms exist at interfaces between the crystalline silicon substrate (11) and the i-type amorphous silicon thin films (12), (14) in a higher concentration than that in the i-type amorphous silicon thin films (12), (14).

Abstract: The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique.

Abstract: A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component.

Abstract: A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer; a third insulating layer formed on the data wire; a pixel electrode formed on the third insulating layer and connected to the data wire, wherein width and length of at least one of the first and the second semiconductor portions vary between at least two pixel areas.

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract: A light emitting device having a plastic substrate is capable of preventing the substrate from deterioration with the transmission of oxygen or moisture content can be obtained. The light emitting device has light emitting elements formed between a lamination layer and an inorganic compound layer that transmits visual light, where the lamination layer is constructed of one unit or two or more units, and each unit is a laminated structure of a metal layer and an organic compound layer. Alternatively, the light emitting device has light emitting elements formed between a lamination layer and an inorganic compound layer that transmits visual light, where the lamination layer is constructed of one unit or two or more units, and each unit is a laminated structure of a metal layer and an organic compound layer, wherein the inorganic compound layer is formed so as to cover the end face of the lamination layer.

Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

Abstract: A light emitting device including a substrate transparent at the emission wavelength and an active layer structure formed on such substrate, in which the thickness of the substrate is 75 ?m or less, and/or a layer for suppressing spectral-intensity-modulation due to the substrate-mode is provided between the substrate and the active layer structure. Such device can suppress the spectral-intensity-modulation due to the substrate-mode, which is observed for the case the substrate is transparent at the emission wavelength, to thereby provide a light emission device excellent in linearity of the current-light output characteristics, and to thereby improve the coupling characteristics with an external cavity.

Abstract: An electrical contact for an optoelectronic device which includes a mirror layer (2) of a metal or a metal alloy, a protective layer (3), which serves for reducing the corrosion of the mirror layer (2), a barrier layer (4), a coupling layer (5), and a solder layer (8). A contact of this type is distinguished by high reflectivity, good ohmic contact with respect to the semiconductor, good adhesion on the semiconductor and good adhesion of the layers forming the contact with one another, good thermal stability, high stability with respect to environmental influences, and also solderability and patternability.

Abstract: An LED package includes a substrate, internal electrodes provided in an even (2n) number and formed on an upper surface of the substrate, external electrodes provided in the even (2n) number, formed on at least a part of surfaces of the substrate other than the upper surface of the substrate, and electrically connected to the corresponding internal electrodes, and LEDs provided in the even (2n) number, located on the upper surface of the substrate, and provided with an anode and a cathode. The anodes and cathodes of the LEDs are electrically connected to the internal electrodes such that the anode of each of the LEDs is connected to the anode of a neighboring one of the LEDs and the cathode of each of the LEDs is connected to the cathode of another neighboring one of the LEDs.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an imager in which pixels in an array includes a capacitor and readout circuitry with NMOS transistors. Periphery circuitry around the array can include PMOS transistors. Because the silicide layer is formed after the conductive layers, it is not exposed to high temperatures and, therefore, migration and cross-contamination of dopants is reduced.

Abstract: A potassium/sodium ion sensing device applying an extended-gate field effect transistor, which using an extended-gate ion sensitive field effect transistor (EGFET) as base to fabricate a potassium/sodium ion sensing device, using the extended gate of the extended-gate ion sensitive field effect transistor as a signal intercept electrode, and immobilizing the hydro-aliphatic urethane diacrylate (EB2001) intermixed with electronegative additive, potassium ionophore, sodium ionophore, and the like, to fabricate a potassium/sodium ion sensing electrode. The present invention utilizes the photocurability and good hydrophilicity of the hydro-aliphatic urethane diacrylate (EB2001), and fixes potassium/sodium ionophore, can obtain a non-wave filter, single-layer, stable signal potassium and sodium ion sensor.

Abstract: A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.

Abstract: A display device has display elements provided inside of pixels, each being formed in vicinity of intersections of signal lines and scanning lines aligned in matrix form; and photoelectric conversion elements, wherein each of the photoelectric conversion elements includes first, second and third semiconductor regions disposed adjacently in sequence in parallel to a surface of a substrate; a first electrode connected to the first semiconductor region; and a second electrode connected to the third semiconductor region, the first semiconductor region being formed by injecting a first conductive impurity in first dose amount; the third semiconductor region being formed by injecting a second conductive impurity in second dose amount; and the second semiconductor region being formed by injecting the first conductive impurity in third dose amount less than the first dose amount.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.

Abstract: The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

Abstract: A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. A second set of trenches, perpendicular to the first set, is formed to separate columns of the array. Wordlines are formed along rows of the array. The wordlines are formed into the second set of trenches in order to shield adjacent floating gates. Metal shields are formed in the first set of trenches along the rows and between floating gates on the pillars.

Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.

Abstract: An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract: There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a <110> crystal direction of a support substrate (1) with a <100> crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the <100> crystal direction of the SOI layer (3). Since hole mobility is higher in the <100> crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

Abstract: A method for manufacturing a metal-oxide-semiconductor transistor prevents the occurrence of a contact spiking phenomenon. The method includes forming a metal thin film and an isolation oxidation film on a semiconductor substrate, and selectively etching the isolation oxidation film such that the isolation oxidation film is left remaining only over a field oxidation film; heat treating the semiconductor substrate to form silicide by the metal thin film in gate, source, and drain regions; removing portions of the metal thin film that is not formed into silicide, that is, removing unreacted metal thin film; removing the isolation oxidation film left remaining on the field oxidation film; and heat treating the semiconductor substrate in an oxygen environment to form the unreacted metal thin film remaining on the field oxidation film into a metal oxidation film. The present invention is related also to a semiconductor device that employs a metal-oxide-semiconductor transistor made using the method.

Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.

Abstract: An integrated circuit comprises a first source, a first drain and a first gate that is arranged between the first source and the first drain. A first body is arranged in the first source. A second gate is arranged between the first source and a second drain. The first body includes a body contact tap. The first and second gates are arranged farther apart adjacent to said body contact tap than in areas that are not adjacent to said body contact tap An edge of the first body is substantially aligned with the first gate.

Abstract: A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near the center of the gate insulating film in the thickness direction. The peak value of nitrogen concentration in the gate insulating film is equal to or greater than 10 atm % and less than or equal to 40 atm %.

Abstract: An angular velocity sensor includes a tuning-fork-shaped substrate (1), drivers (110) that are provided on the arms forming a tuning fork and vibrate the arms; monitors (150) for detecting vibrations generated by the drivers (110); and detectors (120) for detecting displacement of vibrations made in application of an angular velocity. The drivers (110), the monitors (150), and the detectors (120) are made of a lower electrode layer, a piezoelectric thin film, and an upper electrode layer formed on the arms. The outer peripheral edge of the piezoelectric thin film is shaped like a step having at least one flat portion. The flat portion along the outer peripheral edge has no upper electrode layer formed thereon. This structure prevents short circuits between the lower electrode layer and the upper electrode layer.

Abstract: Disclosed is a new type of magnetoresistive random-access memory (MRAM) device using a magnetic semiconductor, which is capable of achieving high-integration and energy saving in a simplified structure without any MOS transistor, based on a rectification effect derived from a p-i-n type low-resistance tunneling-magnetoresistance-effect (low-resistance TMR) diode with a structure having a p-type half-metallic ferromagnetic semiconductor, an n-type half-metallic ferromagnetic semiconductor and at least one atomic layer of nonmagnetic insulator interposed therebetween, or a rectification effect derived from a p-n type low-resistance tunneling-magnetoresistance-effect (low-resistance TMR) diode with a structure devoid of the interposed atomic layer of nonmagnetic insulator.

Abstract: Devices such as transistors, amplifiers, frequency multipliers, and square-law detectors use injection of spin-polarized electrons from one magnetic region, into another through a control region and spin precession of injected electrons in a magnetic field induced by current in a nanowire. In one configuration, the nanowire is also one of the magnetic regions and the control region is a semiconductor region between the magnetic nanowire and the other magnetic region. Alternatively, the nanowire is insulated from the control region and the two separate magnetic regions. The relative magnetizations of the magnetic regions can be selected to achieve desired device properties. A first voltage applied between one magnetic region and the other magnetic nanowire or region causes injection of spin-polarized electrons through the control region, and a second voltage applied between the ends of the nanowire causes a current and a magnetic field that rotates electron spins to control device conductivity.

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Abstract: A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress to it.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first to fourth inner electrodes are alternately arranged, and first to fourth terminal electrodes formed on side faces of the multilayer body. The multilayer capacitor has a first capacitor portion including first and second inner electrodes, and a second capacitor portion including third and fourth inner electrodes and exhibiting a capacitance different from that of the first capacitor portion. The first inner electrodes are electrically connected to respective ones of the plurality of first terminal electrodes through lead conductors, whereas the second inner electrodes are electrically connected to respective ones of the plurality of second terminal electrodes through lead conductors. The third and fourth inner electrodes are electrically connected to the third and fourth terminal electrodes through lead conductors, respectively.

Abstract: A semiconductor component having a tuned variable resistance resistor and a method for manufacturing the tuned variable resistance resistor. A semiconductor process for manufacturing a semiconductor component is selected. For the selected process, the tuned variable resistance resistor is characterized to determine the maximum stress current as a function of the width of the tuned variable resistance resistor. Then, for a given width and maximum stress current, the voltages across the resistors are characterized as a function of length. A tuned variable resistance resistor having a length and width capable of sustaining a predetermined maximum stress current is integrated into a semiconductor component. The semiconductor component may include protection circuitry designed in accordance with the Human Body Model, the Charge Device Model, or both.

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure.

Abstract: Provided are a semiconductor and semiconductor substrate exhibiting low resistance on the substrate side while exhibiting high resistivity in an epitaxially grown layer formed thereover; a method of manufacturing the same; and a semiconductor device employing this semiconductor. The semiconductor consists of a compound single crystal and comprises a region having a planar defect density of 1×107/cm2 or more and a region having a planar defect density of 1/cm2 or less. The semiconductor substrate comprises the aforementioned semiconductor on a substrate. The methods of manufacturing the aforementioned semiconductor and semiconductor substrate are also provided.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including at least one overlying hardmask layer; forming spacers selected from the group consisting of oxide/nitride and oxide/nitride oxide layers adjacent the polysilicon gate structure; removing the at least one overlying hardmask layer to expose the polysilicon gate structure; carrying out an ion implant process; carrying out at least one of a wet and dry etching process to reduce the width of the spacers; and, forming at least one dielectric layer over the polysilicon gate structure and spacers in one of tensile and compressive stress.

Abstract: A field effect transistor comprising, as provided on a support substrate, an insulation layer, a gate electrode and an organic semiconductor layer separated by the insulation layer, a source electrode and a drain electrode provided so as to contact the organic semiconductor layer, wherein elongation ?1 (%) at the yield point of the insulation layer is larger than elongation ?2 (%) at the yield point of the support substrate.

Abstract: A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivity SiOx film and further to increase the insulating property, a highly reliable semiconductor device free from crack or peeling of the film by employing the low relative permittivity SiOx film as an interlayer insulating film for metal wirings, are provided. The low relative permittivity film is characterized in that it is made of a porous material, the major constituent of which is SiOx (where 1.8?X?1.0), and the relative permittivity at 1 MHz is at most 2.3.

Abstract: In one exemplary embodiment, a structure comprises a substrate having a top surface, and a die attach pad situated on the top surface of the substrate. The die attach pad includes a die attach region and at least one substrate ground pad region electrically connected to the die attach region. The die attach pad further includes a die attach stop between the die attach region and the at least one substrate ground pad region. The die attach stop acts to control and limit die attach adhesive flow out to the at least one substrate ground pad region during packaging so that the at least one substrate ground pad region can be moved closer to die attach region so that shorter bond wires for connecting the at least one substrate ground pad region to a die wire bond pad may be used during packaging.

Abstract: An optical semiconductor apparatus has an eyelet having a through hole, an insulating member provided in the through hole, a semiconductor optical element, and a submount on which the semiconductor optical element is mounted. The insulating member supports a plurality of lead terminals. The submount has a first portion supported by the eyelet, a second portion supported by the eyelet, and a third portion disposed between the first portion and the second portion and located above the insulating member. The semiconductor optical element is provided on the third portion of the submount.

Abstract: A BGA type semiconductor device which realizes its high speed operation and high integration density by shortening power supply or grounding wires to reduce its inductance. In the BGA type semiconductor device, the power supply or grounding wires are provided in the vicinity of the center of a BGA board to realize the high-speed operation and high integration density, whereby an electronic circuit or equipment using the BGA type semiconductor device can be made high in operational speed and made sophisticated in function.

Abstract: In a semiconductor device including a semiconductor wafer having a first main surface where a circuit element is formed, electrode pads are formed at an upper portion of the first main surface of the semiconductor wafer electrically connected with the circuit element. Index marks are formed on a second main surface of the semiconductor wafer that is opposite the first main surface. The index marks consist of line segments and indicate a direction along which the semiconductor device is to be mounted.

Abstract: A semiconductor device includes a base, a semiconductor element having a plurality of electrodes, a plurality of conductive lines connected to the electrodes of the semiconductor element, plating stubs attached to the conductive lines, and a plurality of wiring layers formed in a plurality of layers on the base. The plating stub attached to a first conductive line, and the plating stubs attached to one or a plurality of second conductive lines adjacent to the first conductive line, exist in different conductive wiring layers.

Abstract: A dielectric composite material containing a toughened benzocyclobutene resin and at least about 50% by weight of an inorganic filler. Also electronic packages having at least one conductive layer and at least one layer of the dielectric composite material. The dielectric composite material can have a dielectric constant less than about 3.5, and a dielectric loss of less than about 0.004.