Abstract: A vacuum gate valve capable of airtightly isolating or interconnecting two vacuum chambers adopts a link lever mechanism to convert a vertical linear dynamic force into a vertical force and a transversal force required for opening or shutting the valve, so as to provide a transversal force large enough to resist the pressure difference between the two vacuum chambers. In the meantime, the invention can prevent an O-ring of the valve from being worn out or damaged when the valve is opened or shut. If the shut valve has no dynamic force, an airtight status will be maintained to isolate the two vacuum chambers. The vacuum gate valve of the invention adopts a low-price flexible sealed tube to lower the cost of the vacuum device.

Abstract: This invention concerns highly concentrated self-emulsifying preparations containing organopolysiloxanes and alkylammonium compounds and use thereof in aqueous systems on textile substrates. More particularly, this invention concerns preparations consisting of fully or partially quaternized amino-functional organopolysiloxanes, quaternary alkylammonium compounds, if appropriate an organic hydrotrope and if appropriate water.

Abstract: Deicing compositions comprised of hydroxyl-containing organic compounds and/or organic acid salts are disclosed.

Abstract: A temperature sensor for a display device is provided, which includes a substrate for the display devices, and a temperature sensing line formed on the substrate. The temperature sensing line is a conductor.

Abstract: A liquid crystal composition having a negative dielectric anisotropy and containing at least one compound selected from a group of compounds represented by formula (1) as a first component, at least one compound selected from a group of compounds represented by formula (2) as a second component, at least one compound selected from a group of compounds represented by formula (3) as a third component, and at least one compound selected from a group of compounds represented by formula (4) as a fourth component: wherein the liquid crystal composition consists essentially of the first component, the second component, the third component and the fourth component and wherein R1 is alkyl or alkenyl; R2 is alkyl or alkoxy; R3 is alkyl or alkoxymethyl; R4 is alkyl; A1 is 1,4-cyclohexylene or 1,4-phenylene; A2 is 1,4-cyclohexylene, 1,4-phenylene or 2-fluoro-1,4-phenhlene; and Z1 is a single bond or —COO—.

Abstract: A phosphate dispersant which can improve the efficiency of dispersing nickel metal powder by effectively adsorbing on the surface of the metal powder and preventing aggregation thereof, and a paste composition and a dispersion method using the same are provided. A multilayer ceramic capacitor (MLCC) is also provided. The phosphate dispersant can achieve the optimal dispersion efficiency by strongly adsorbing on the surface of the nickel metal powder. An improvement in the dispersion efficiency as such can consequently suppress aggregation of the nickel metal powder during the preparation of a conductive paste composition containing a nickel metal powder, and therefore a larger amount of the nickel metal powder can be used in the paste composition. The increased amount of nickel metal powder allows producing an internal nickel electrode having improved electric properties and mechanical properties during the production of MLCCs.

Abstract: There is provided a particulate conductive filler which comprises a conductive metal coating formed over a coarse carbon-based core such as graphite between 350 and 1000 microns in size. The conductive filler is used in conjunction with a polymer matrix such as an elastomer typified by silicone elastomer to form composite materials for conductive and electromagnetic interference shielding applications.

Abstract: A virtual electronic perimeter fence includes at least a first, second and third fence post each including an emitter for emitting a beam of infrared light at a predetermined frequency. The first, second and third fence posts include a receiver for receiving the predetermined frequency of infrared light emitted from a designated fence post. A beam of infrared light of a first frequency is emitted from the first fence post to the second fence post and a beam of infrared light of a second frequency is emitted from the second fence post to the third fence post and infrared light of a third frequency is emitted from the third fence post to the first fence post for providing a virtual electronic perimeter fence that provides an alarm if an interruption occurs in the beam of infrared light while eliminating cross-signals therebetween. A light, sound and video system may be provided.

Abstract: A kind of safety fence and protection pole connection apparatus for trampoline, belonging to the manufacture technique field for trampoline subassembly. It comprises a fence protection stem; an outside frame with a short pole attached its bottom; a foot supporter located under the short pole; wherein the fence protection stem, short pole and foot supporter are clamped down together by hinge style embrace clamps separately. The hinge style embrace clamp comprises a clamp body with a hole for protection hole and a hole for tube, a hinge located the end of the clamp body, a clamping device located the open part of the embrace clamp. The present invention provides a safety fence and protection pole connection apparatus for trampoline; it has reasonable design, enough structure strength for the frames, nice orientation for the fence protecting stems, and conveniences in the assembly and manufacture.

Abstract: A guard rail system available in kits ready for assembly is formed of a capped wood composite with the look and feel of wood. The system includes balusters fastened to an upper rail and a bottom rail, each of which are attached to a post or wall. The upper rail is formed of a plurality of pieces that fit together to form a circumferential finished surface and include a longitudinal cavity. Fasteners that couple the balusters to the upper rail and the upper rail to the posts, are not externally visible. The brackets that couple the upper rail to the posts are disposed within the longitudinal cavity.

Abstract: One embodiment of the present invention provides for a fence system having a post and a bracket. The post preferably has at least one longitudinal channel extending a length of the post, the channel being narrower at an opening of the channel than at an interior of the channel. The bracket preferably has an engagement member slidingly engaged with the channel of the post, and a rail receptacle housing adapted to support a rail. A further embodiment of the present invention provides for a method of assembling a fence comprising the steps of providing a post, inserting an end of a rail into a rail receptacle housing of a bracket, sliding an engagement member of the bracket into engagement with a dovetail-shaped channel extending the length of the post, and attaching the bracket to the post at a desired position.

Abstract: A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective coating (ARC) film on the bottom electrode film, patterning and etching the ARC film and the bottom electrode film to form a bottom electrode comprising a side edge, and forming a phase change material portion on the ARC film and the bottom insulating layer, wherein the phase change material portion physically contacts the side edge of the bottom electrode. The method further includes forming a top electrode on the phase change material portion, and forming a top electrode contact on the top electrode.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: The present invention relates to a doped semiconductor nanocrystal layer comprising (a) a group IV oxide layer which is free of ion implantation damage, (b) from 30 to 50 atomic percent of a semiconductor nanocrystal distributed in the group IV oxide layer, and (c) from 0.5 to 15 atomic percent of one or more rare earth element, the one or more rare earth element being (i) dispersed on the surface of the semiconductor nanocrystal and (ii) distributed substantially equally through the thickness of the group IV oxide layer. The present invention also relates to a semiconductor structure comprising the above semiconductor nanocrystal layer and to processes for preparing the semiconductor nanocrystal layer.

Abstract: The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer on the basis of doped Si or doped GaP and a III/V semiconductor disposed thereupon and having the composition GaxInyNaAsbPcSbd, wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand and of a to d on the other hand is substantially 1:1, to methods for the production thereof, new semiconductors, the use thereof for the production of luminescence diodes and laser diodes or also modulator and detector structures, which are monolithically integrated in integrated circuits on the basis of the Si or GaP technology.

Abstract: A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include a semiconductor substrate, and at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. The gate may include a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel may include a plurality of stacked base semiconductor monolayers, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers. The at least one non-semiconductor monolayer may be positioned at depth of about 4-100 monolayers relative to the interface between the channel and the gate dielectric.

Abstract: A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: There is provided a field effect transistor having an organic semiconductor layer, including: an organic semiconductor layer containing at least porphyrin; and a layer composed of at least a polysiloxane compound, the layer being laminated on the organic semiconductor layer so as to be in intimate contact with the organic semiconductor layer. As a result, there can be provided a field effect transistor which enables an organic semiconductor layer having high crystallinity and high orientation to be formed and which exhibits a high mobility.

Abstract: An organic light emitting display device is disclosed. The device includes a substrate; a first electrode formed on the substrate; an organic layer including at least an emission layer and formed on the first electrode; and a second electrode formed on the organic layer. The emission layer includes a host and a dopantmaterial. The dopant is one of materials having the structure of Formula 1, where R may be one selected from the group consisting of ethylene, an ethylene derivative, stilbene, a stilbene derivative. Also, R1 to R6 may be different from or equal to each other, and each is selected from the group consisting of a hydrogen atom, a halogen atom, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C5 to C20 aryl group, a C3 to C30 heterocyclic group, and an aliphatic C3 to C30 hydrocarbon group.

Abstract: A method for fabricating a flat panel display, comprising preparing an insulating substrate; forming separated source and drain electrodes on the insulating substrate to define a channel region; forming a first passivation layer on the source and drain electrodes; forming a metal layer having an opening corresponding to the channel region on the first passivation layer; forming a deposition opening in the passivation layer by using the metal layer as a mask to expose the channel region; forming an organic semiconductor layer and a second passivation layer, in turn, in the deposition opening and on the metal layer; and removing the metal layer, the organic semiconductor layer and the second passivation layer while allowing the layers formed in the deposition opening to remain.

Abstract: A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region.

Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a liquid crystal display panel and an optical film assembly. The liquid crystal display panel includes two substrates and a liquid crystal layer disposed between the substrates, and has a plurality of multi-domains defined in a unit pixel. The optical film assembly includes a biaxial film and a polarizing film formed integrally with the biaxial film. Moreover, the biaxial film is disposed near to the liquid crystal cell.

Abstract: Provided are a thin film transistor (TFT) substrate and a method for manufacturing the same. The method comprises forming on a substrate a conductive layer, an impurity-doped silicon layer, and an intermediate layer, wherein the intermediate layer comprises intrinsic silicon; patterning the intermediate layer, the impurity-doped silicon layer, and the conductive layer to form a data line, a source electrode, a drain electrode, ohmic contact portions, and intermediate portions, wherein an ohmic contact portion and an intermediate portion are on the source electrode, and an ohmic contact portion and an intermediate portion are on the drain electrode; forming an intrinsic silicon layer on the substrate; and patterning the intrinsic silicon layer to form a semiconductor layer forming channel portion between the source electrode and the drain electrode, and a contact portion on the intermediate portion.

Abstract: The invention provides a flat panel display having an insulating substrate; a data line formed on the insulating substrate; an interlayer insulating film formed on the data line having a first contact opening exposing the data line; a connecting member formed in a part of the first contact opening; an interlayer insulating film around the first contact opening; a gate insulating film formed on the connecting member having a second contact opening exposing the connecting member; and an organic semiconductor layer formed on the gate insulating film.

Abstract: In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized. After the crystallization, a patterning step is carried out to form an active layer with a desired shape. The present invention is also characterized by forming a semiconductor film through a sputtering method, subsequently forming an insulating film. Next, the semiconductor film is crystallized through the insulating film, so that a crystalline semiconductor film is formed. According this structure, it is possible to obtain a thin film transistor with a good electronic property and a high reliability in a safe processing environment.

Abstract: The present invention provides a field effect transistor that includes a semiconductor layer (15) containing an organic substance, and a first electrode (16), a second electrode (12), and a third electrode (14) that are not in contact with each other at least electrically. The first electrode (16) is arranged above the semiconductor layer (15), the second electrode (12) is arranged below the semiconductor layer (15), and the third electrode (14) is arranged beside the semiconductor layer (15). The semiconductor layer (15) is connected electrically to two electrodes selected from the first electrode (16), the second electrode (12), and the third electrode (14), and the electrically insulating layers (13,17) are interposed between the electrodes (12, 14, 16). The first electrode (16) lies over the semiconductor layer (15) so as to extend beyond the periphery of the semiconductor layer (15).

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 ?, e.g., between 100 and 750 ?. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.

Abstract: An LCD panel with mixed substrate materials and a method of making the LCD panel are presented. The LCD panel is made of a first substrate, a second substrate disposed substantially parallel to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate includes a glass substrate, a TFT formed on the glass substrate, and a color filter formed on the TFT. The second substrate includes a plastic substrate and a common electrode formed on the plastic substrate. Forming the color filter on the TFT eliminates the need to form black matrices on the second substrate, preventing misalignment of the two substrates due to different heat sensitivities. Since there is no concern of substrate misalignment caused by heat, laser beam can be used to cut the substrates during the manufacture of the LCD panel.

Abstract: A display device with a decreased number of electrical lines and a method of making such display device are presented. The display device includes: a plurality of thin film transistors electrically connected to data wiring, wherein the data wiring includes a data line and a data electrode; a partition wall formed on the thin film transistor and having a contact hole exposing the data wiring; and a cathode electrically connected to the data wiring through the contact hole.

Abstract: In a radiation-emitting optoelectronic semiconductor chip comprising an active layer (3) at least one p-doped layer (9) and a layer sequence (8) comprising a plurality of undoped layers (4, 5, 6, 7), which is arranged between the active layer (3) and the p-doped layer (9) and contains at least a first undoped layer (5) and a second undoped layer (6), the second undoped layer adjoining the first undoped layer (5) and succeeding the first undoped layer (5) as seen from the active layer (3), the first undoped layer (5) and the second undoped layer (6) in each case contain aluminum, the aluminum proportion being greater in the first undoped layer (5) than in the second undoped layer (6). The layer sequence (8) advantageously acts as a diffusion barrier for the dopant of the p-doped layer.

Abstract: A white light light emitting diode (LED) formed by depositing an LED chip that emits light at a first wavelength and forming a semiconductor nanocrystal complex. The semiconductor nanocrystal complex absorbs at least a portion of the light emitted by the LED chip and emits light at a second wavelength. The semiconductor nanocrystal complex and a powdered phosphor are deposited over the LED chip. The powdered phosphor also absorbs a portion of the light emitted by the LED chip and emits light at a third wavelength. The semiconductor nanocrystal complex is selected to provide a color of the spectrum that is lacking from the combined output of phosphor/LED chip combination, to improve a Color Rating Index (CRI) value and to provide a “warmer” light. The semiconductor nanocrystal complex and the powdered phosphor can be mixed into the same matrix material or into separate matrix materials and/or deposited as separate layers.

Abstract: A nitride-based semiconductor light-emitting device capable of stabilizing transverse light confinement is obtained. This nitride-based semiconductor light-emitting device comprises an emission layer, a cladding layer, formed on the emission layer, including a first nitride-based semiconductor layer and having a current path portion and a current blocking layer, formed to cover the side surfaces of the current path portion, including a second nitride-based semiconductor layer, while the current blocking layer is formed in the vicinity of the current path portion and a region having no current blocking layer is included in a region not in the vicinity of the current path portion. Thus, the width of the current blocking layer is reduced, whereby strain applied to the current blocking layer is relaxed. Consequently, the thickness of the current blocking layer can be increased, thereby stabilizing transverse light confinement.

Abstract: A light-emitting device comprises a multi-layer structure including one or more active layer configured to irradiate light in response to the application of an electric signal, a transparent passivation layer laid over an outmost surface of the multi-layer stack, a reflector layer laid over the passivation layer, and a plurality of electrode pads coupled with the multi-layer structure. In a manufacture process of the light-emitting device, the reflector layer and the passivation layer are patterned to form at least one opening exposing an area of the multi-layer structure.

Abstract: A white light semiconductor light emitting device includes a semiconductor LED and first and second phosphors provided on a light emitting region of the LED to emit light within a first wavelength range, which is different from that of light emitted from the LED, by absorbing a portion of the light emitted from the LED. The first and second phosphors are respectively a barium-silicate-base green phosphor and a zinc-selenium-base red phosphor.

Abstract: An object of the present invention is to provide a nitride semiconductor product which causes no time-dependent deterioration in reverse withstand voltage and maintains a satisfactory initial reverse withstand voltage. The inventive nitride semiconductor product comprises an n-type layer, a light-emitting layer, and a p-type layer which are formed of a nitride semiconductor and sequentially stacked on a substrate in the above order, the light-emitting layer having a quantum well structure in which a well layer is sandwiched by barrier layers having band gaps wider than the band gap of the well layer, wherein each barrier layer comprises a barrier sublayer C which has been grown at a temperature higher than a growth temperature of the well layer, and a barrier sublayer E which has been grown at a temperature lower than a growth temperature of the barrier sublayer C, and the barrier sublayer C is disposed closer to the substrate with respect to the barrier sublayer E.

Abstract: A light emitting diode (LED) and a method are provided for fabricating the a LED with an improved structure for better light emitting efficiency and better light output performance.

Abstract: A light extraction plate can be used with a light emitting diode (LED) to efficiently extract and provide control over the spatial distribution of extracted light in terms of intensity and angle. The extraction plate can have millions of optical micro-elements and can be manufactured independently of the LED using conventional integrated circuit (IC) fabrication techniques. The extraction plate is preferably attached or bonded to an LED surface.

Abstract: This invention provides an organic electroluminescent element (organic EL element) utilizing phosphorescence which emits light efficiently with high luminance at low current density, shows good driving stability and is applicable to display devices such as flat panel displays and illuminating devices. The element comprises an anode, organic layers and a cathode piled one upon another on a substrate, at least one of the organic layers is a light-emitting layer containing a host material and a dopant material and a pyrazole-derived compound having 2-4 pyrazole structures represented by the following formula I in the same molecule is used as said host material; wherein, Ar1-Ar3 are independently hydrogen or substituted or unsubstituted aromatic hydrocarbon groups and at least one of Ar1-Ar3 is a group other than hydrogen.

Abstract: Provided is a silicophosphate-based phosphor of Formula 1 and a light-emitting device including the same: [(Sr(1-x-y-a-b-c) BaaCabMgcEuxMny)4Si(PO4)4 ??(1) where 0<x?0.2, 0?y?0.2, 0<a?0.2, 0<b?0.5, and 0<c?0.5. The silicophosphate-based phosphor of Formula 1 is chemically and thermally stable and can be easily prepared. The phosphor exhibits a high luminous property when excited by a UV LED excitation light source having a wavelength of 360-420 nm, and emits light having a wavelength of 570 to 630 nm. Accordingly, the silicophosphate-based phosphor can be used in a LED, a lamp, a self-emission type liquid crystal display device, or the like. In particular, when a white LED includes the silicophosphate-based phosphor, the color rendering index of the white LED is high and thus an excellent color rendering property can be obtained.

Abstract: An LED structure is disclosed herein, which comprises, sequentially arranged in the following order, a light generating structure, a non-alloy ohmic contact layer, a metallic layer, and a substrate. As a reflecting mirror, the metallic layer is made of a pure metal or a metal nitride for achieving superior reflectivity. The non-alloy ohmic contact layer is interposed between the metallic layer and the light generating structure so as to achieve the required ohmic contact. To prevent the metallic layer from intermixing with the non-alloy ohmic contact layer and to maintain the flatness of the reflective surface of the first metallic layer, an optional dielectric layer is interposed between the metallic layer and the non-alloy ohmic contact layer.

Abstract: A light-emitting-diode packaging structure having thermoelectric device, which is applied to the LED unit packaged using the flip chip technology. This is realized by directly building the thermoelectric elements into the solder bump layer of the light-emitting-diode packaging structure to replace a part of the solder bumps, as such raising the heat dissipation efficiency of the light emitting diode unit, enhancing the stability and reliability of light emission of the LED unit, and reducing the difficulties and complexity of the integration of the LED package.

Abstract: The present invention relates to a flip chip light emitting diode, in which the flow of current concentrated on a portion adjacent to an n-type electrode can be induced into the center of a light emitting section and a current-spreading effect is accordingly enhanced, thereby increasing light emission efficiency of a light emitting diode chip, and a method of manufacturing the same.

Abstract: The invention relates to a wavelength-convertible LED package including a package substrate having a lead frame, and an LED mounted on the package substrate and electrically connected to the lead frame. The wavelength-convertible LED package also includes a low refractive index region surrounding the LED, having a first refractive index, and a high refractive index layer formed on the low refractive index region, having a rough pattern on an upper surface thereof and a second refractive index higher than the first refractive index. The wavelength-convertible LED package further includes a resin part containing phosphor for converting the wavelength of light emitted from the LED, having a third refractive index lower than the second refractive index.

Abstract: A light emitting diode (LED) formed by depositing an LED chip and coupling a stability layer to the LED chip. Semiconductor nanocrystals are placed in a first matrix material to form a nanocrystal complex layer. The nanocrystal complex layer is deposited on top of the stability layer. A thickness of the stability layer is chosen to maximizes a power of a light output by the nanocrystal complex layer. The matrix material and the stability layer can be of the same type of material. Additional layers of matrix material can be deposited on top of the nanocrystal complex layer. These additional layers can comprise matrix material only or can comprise matrix material and semiconductor nanocrystals to form another nanocrystal complex layer.

Abstract: The leads of a light emitting diode are made coaxial. The inner lead protrudes lower than the outer lead. The package is inserted into a spongy display panel for power supply. The display panel has three layers: a lower conducting layer for contacting said inner lead and a top conducting layer for contacting said outer layer, and an insulating layer between the top and the bottom layer. For LED with a bottom electrode and a top electrode, the LED can be mounted on the planar tops of the inner lead and the top electrode wire bonded to the outer lead, or the LED can be mounted on the side surface of the inner lead and the top electrode wire bonded to the outer lead. For LED with two bottom electrode, the LED electrodes can straddle over the planar tops of the inner lead and the outer lead, or the LED electrodes can straddle over the telescopic side surfaces of the two leads.

Abstract: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm?3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.