Abstract: A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

Abstract: A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from each other while restraining parasitic capacitance, latch-up phenomena, and formation of field transistors. The three-dimensional high voltage transistor includes an active area of the three-dimensional high voltage transistor formed in the form of a column on predetermined areas of a Silicon-On-Insulator substrate, source and drain formed in the active areas of the three-dimensional high voltage transistor in the depth direction, a channel area formed between the source and the drain in the depth direction, and a column-shaped gate formed at the side of the channel area on the Silicon-On-Insulator substrate.

Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Abstract: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to increase a channel area so as to simplify process steps, thereby improving the yield and productivity for manufacturing a semiconductor device.

Abstract: A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.

Abstract: A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one nonsemiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: In a low withstand voltage vertical trench MOSFET having an SJ structure, an N type epitaxial layer which is a current path and a trench structure which extends from a semiconductor surface into the N type epitaxial layer are provided, and a floating P type region is formed in a portion of the N type epitaxial layer positioned below the trench structure. The P type region is formed below the trench structure by ion-implanting P type impurity ions. By forming the P type region below a fine trench gate through ion-implantation, energy for ion-implantation can be reduced, and a fine SJ structure can be fabricated. Accordingly, a device structure which allow formation of a fine SJ structure in a low withstand voltage power MOSFET and a manufacturing method of the same can be provided.

Abstract: The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

Abstract: The present invention discloses an N-ary mask-programmable memory (N-MPM). N-MPM cells can have N cell-states, with N>2. N-MPM cells could be geometry-defined, junction-defined, or both. Based on an nF-opening process (n?1), partial-contacts with feature size<1F can be implemented with an nF-opening mask with feature size?1F. N can be a non-integral power of 2. In this case, each memory cell represents fractional bits.

Abstract: A building structure for covering a large object with a cover comprising: multiple frames, each frame being part of a building structure); at least one motor suspended from at least one of said plurality of frames and connected to one or more spools; and an arm lifting structure suspended from the frame and comprising: at least two arms; a plurality of lifting connectors, each attached on one end to an arm on a first end and attached to one of the spools on a second end; and at least one fastening roller member mounted to each arm for temporarily securing the cover to the arms. Alternate embodiments of the building structure include laterally and/or longitudinally translating motors and/or guides for ensuring the that arms are raised and lowered straight up and down.

Abstract: A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching the gate electrode; a hollow portion existing between the source layer and the semiconductor substrate, and between the drain layer and the semiconductor substrate, respectively; and the hollow portion in absence between the semiconductor layer under the gate electrode and the semiconductor substrate.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity.

Abstract: An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.

Abstract: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

Abstract: A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.

Abstract: An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact compensation, and high-temperature annealing is carried out in order to activate implanted impurities. Subsequently, an interlayer insulation film, a storage capacitor, and another interlayer insulation film are formed in sequence. Then, contact holes reaching a part of wiring layers are formed in the peripheral circuit part while, in the guard ring part, a trench reaching a diffusion layer is formed. Next, a barrier metal film is formed in each of the contact holes and the trench, and further, a contact plug comprising, for example, a W film is buried therein.

Abstract: A semiconductor structure that includes a first gate structure, second gate structure and a nitrogen-containing etch-stop layer. The first gate structure whose sidewalls are bounded by at least one first spacer is formed on a semiconductor substrate. The second gate structure whose sidewalls are bounded by at least one second spacer is formed on the semiconductor substrate, wherein the second gate structure is adjacent to the first gate structure. The nitrogen-containing etch-stop layer is formed over the first and second gate structures, having a thickness substantially the same over the semiconductor substrate, thereby improving a step coverage of a subsequent layer formed on the nitrogen-containing etch-stop layer between the first and second gate structures.

Abstract: A chemical sensor is provided that includes a semiconductor layer, an organic chemical layer disposed on a surface of the semiconductor layer, and a heating element configured to heat the semiconductor layer.

Abstract: A harsh environment transducer including a substrate having a first surface and a second surface, wherein the second surface is in communication with the environment. The transducer includes a device layer sensor means located on the substrate for measuring a parameter associated with the environment. The sensor means including a single crystal semiconductor material having a thickness of less than about 0.5 microns. The transducer further includes an output contact located on the substrate and in electrical communication with the sensor means. The transducer includes a package having an internal package space and a port for communication with the environment. The package receives the substrate in the internal package space such that the first surface of the substrate is substantially isolated from the environment and the second surface of the substrate is substantially exposed to the environment through the port.

Abstract: A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first surface and has a fixed magnetization direction. A magnetization variable layer is provided on the second surface, has variable magnetization direction, and has a planer shape including a rectangular part, a first projected part, and a second projected part. The rectangular part has mutually facing first and second longer sides and mutually facing first and second shorter sides. The first projected part projects from the first longer side at a position shifted from the center toward the first shorter side. The second projected part projects from the second longer side at a position shifted from the center toward the second shorter side.

Abstract: A method for generating an offset field for a magnetic random access memory (MRAM) device includes forming a first pinned layer integrally with a wordline, and forming a second pinned layer integrally with a bitline. An MRAM cell is disposed between the wordline and the bitline, the MRAM cell including a reference layer, an antiparallel free layer and a tunnel barrier therebetween. The first pinned layer is formed with an internal magnetization in a manner so as to create a first external field generally perpendicular to a long axis of the wordline, and the second pinned layer is formed with an internal magnetization in a manner so as to create a second external field generally perpendicular to a long axis of the bitline.

Abstract: A packaged electro-optic integrated circuit and a multi-fiber connector including an integrated circuit substrate, at least one optical signal providing element, at least one optical signal sensor, sensing at least one optical signal from the at least one optical signal providing element and at least one discrete reflecting optical element, mounted onto the integrated circuit substrate, cooperating with the at least one optical signal providing element and being operative to direct light from the at least one optical signal providing element.

Abstract: An imaging chip is packaged in transparent injection molded material. The chip may have photosensitive elements arranged in a two-dimensional array on semiconductor material. Each element corresponds to a pixel of an image. The package may be formed of epoxy resin. In one aspect of the invention, the transparent plastic material provides a color filter. Second and third packages with complementary color filters may be used to provide signals for a color imaging system. In another aspect of the invention, a lens is integrated into the plastic package. In another aspect of the invention, a semiconductor chip is applied to a pre-formed plastic package by bump bonding.

Abstract: A thin film semiconductor device such as a photovoltaic device is fabricated on a lightweight substrate material which is affixed to a layer of material which is in turn supported by a carrier. Following the fabrication of the device, the carrier is removed such as by an etching process, leaving the layer of material adhered to the substrate. The adhered layer provides a balancing force to the back side of the substrate which minimizes or eliminates the tendency of the semiconductor device supported on the opposite side of the substrate to cause the substrate to curl. Also disclosed are devices and structures made by this method.

Abstract: An apparatus comprises: a substrate; a photodetector formed on an area of a surface of the substrate; an electrical contact formed on a portion of the photodetector; and a reflector formed over a portion of the photodetector distinct from the portion of the photodetector having the electrical contact formed thereon. The substrate, the photodetector, and the reflector are arranged so that an optical signal to be detected is incident on the photodetector from within the substrate, and at least a portion of the optical signal incident on the photodetector and transmitted thereby on a first pass is reflected by the reflector to propagate through the photodetector for a second pass.

Abstract: A semiconductor device includes a drift layer of a first conductivity type having a doping concentration and a conduction layer also of the first conductivity type on the drift layer that has a doping concentration greater than the doping concentration of the drift layer. The device also includes a pair of trench structures, each including a trench contact at one end and a region of a second conductivity type opposite the first conductivity type, at another end. Each trench structure extends into and terminates within the conduction layer such that the second-conductivity-type region is within the conduction layer. A first contact structure is on the drift layer opposite the conduction layer while a second contact structure is on the conduction layer.

Abstract: A semiconductor device is configured that a high-withstand voltage semiconductor device (101) and logic circuits (201 and 301) are integrated on a single chip and that a high-withstand voltage high-potential island (402) including the high-potential-side logic circuit (301) is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region (405) having a level shift wire region (404) that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.

Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

Abstract: A semiconductor memory device includes an insulation layer disposed in a fuse region of a substrate, a fuse including a conductive pattern disposed on the insulation layer and a metal pattern disposed in physical contact with the conductive pattern, the conductive pattern composed of a material that thermally explodes when it absorbs a laser beam.

Abstract: A varactor structure with high quality factor and good linearity, and a method for fabricating the same are disclosed. According to the method, an additional ion implantation is performed between a first electrode ion implantation and a second electrode ion implantation to form a high doped region. In other words, a high doped region of the same conductive type as the second electrode is disposed between the second electrode and the substrate. The varactor with additional high doped region not only has a high quality factor and good linearity, but also a high tuning ratio.

Abstract: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.

Abstract: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.

Abstract: The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.

Abstract: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.

Abstract: A semiconductor apparatus comprises a plurality of transistor devices including a control terminal being inputted with a control signal and a first and a second terminals that a current flows therein according to the control signal, and a plurality of substrate conductive portions each formed in a region different from a region where the plurality of transistor devices are formed therein, wherein the transistor devices are connected to the substrate conductive portions, and each of the substrate conductive portion includes a semiconductor layer separated from other substrate conductive portions.

Abstract: A semiconductor device consistent with the present invention includes a semiconductor substrate having a semiconductor chip region and a scribe region; a first insulating layer formed in the semiconductor chip region of the semiconductor substrate; a metal contact plug formed in the first insulating layer; a metal sidewall formed on a side of the first insulating layer in the scribe region; a metallization wiring electrically connected with the substrate via the metal contact plug; and a second insulating layer and a protective layer formed over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region.

Abstract: A deposition oxide interface with improved oxygen bonding and a method for bonding oxygen in an oxide layer are provided. The method includes depositing an M oxide layer where M is a first element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5, plasma oxidizing the M oxide layer at a temperature of less than 400° C. using a high density plasma source, and in response to plasma oxidizing the M oxide layer, improving M-oxygen bonding in the M oxide layer. The plasma oxidation process diffuses excited oxygen radicals into the oxide layer. The plasma oxidation is performed at specified parameters including temperature, power density, pressure, process gas composition, and process gas flow. In some aspects of the method, M is silicon, and the oxide interface is incorporated into a thin film transistor.

Abstract: A MEMS package and a method for its forming are described. The MEMS package has at least one MEMS device located on a flexible substrate. A metal structure surrounds the at least one MEMS device wherein a bottom surface of the metal structure is attached to the flexible substrate and wherein a portion of the flexible substrate is folded over a top surface of the metal structure and attached to the top surface of the metal structure thereby forming the MEMS package.

Abstract: The invention discloses a monolithic integrated circuit with at least one signal connection carrying a signal and with an interference suppression device integrated in the circuit to reduce radiated interference. The interference suppression device has at least one stripline having a section whose beginning is coupled to the signal connection and whose end is short-circuited, wherein a length of the section is chosen as a function of a predefinable frequency, in particular as a function of a frequency of the radiated interference that is to be suppressed.

Abstract: A quad flat non-lead (QFN) package at least comprises a die, a lead frame and a molding compound. The lead frame comprises a plurality of L-shaped leads for electrically connecting the die. Two pre-plated conductive layers, formed on a bottom portion and a top portion of each L-shaped lead, are exposed to a bottom surface and a top surface of the package, respectively. The molding compound is formed for encapsulating the die and the L-shaped leads.

Abstract: A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. The semiconductor package may have an indented or non-planar surface structure.

Abstract: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the outer side into the interposer. The aperture may be divided into at least two openings, and at least a first of the openings may extend from the outer side through the interposer in order to allow connection to the microchip device.

Abstract: The invention provides a flexible wiring board for repeated folding sections which exhibits excellent folding endurance, and a flex-rigid wiring board comprising the flexible wiring board as a section thereof. The flexible wiring board for repeated folding sections of the invention comprises a wiring patterned base film layer (11), a flexible insulating material layer (12) covering the layer (11), and a cover film layer (13) covering the layer (12).

Abstract: An electronic module assembly including a first substrate; a first semiconductor die mounted to a top surface of the first substrate; a second substrate located above the first semiconductor die and electrically and mechanically connected to the top surface of the first substrate; a second semiconductor die mounted to a top surface of the second substrate; a heat spreader located above the second semiconductor die and thermally coupled to the second semiconductor die; and encapsulant material at least partially surrounding the second semiconductor die and the heat spreader.

Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.