Abstract: An LED chip comprising an electrically conductive and radioparent substrate, in which the epitaxial layer sequence is provided on substantially the full area of its p-side with a reflective, bondable p-contact layer. The substrate is provided on its main surface facing away from the epitaxial layer sequence with a contact metallization that covers only a portion of said main surface, and the decoupling of light from the chip takes place via a bare region of the main surface of the substrate and via the chip sides. A further LED chip has epitaxial layers only. The p-type epitaxial layer is provided on substantially the full area of the main surface facing away from the n-conductive epitaxial layer with a reflective, bondable p-contact layer, and the n-conductive epitaxial layer is provided on its main surface facing away from the p-conductive epitaxial layer with an n-contact layer that covers only a portion of said main surface.

Abstract: The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to each other in that order; first and second electrodes that are connected to the first-conductivity-type region and the second-conductivity-type region, respectively, at both ends of the semiconductor layer; and a gate electrode that is coupled to the second-conductivity-type region or the first-conductivity-type region in an intermediate area of the semiconductor layer, the gate electrode being provided over a plurality of faces of a semiconductor layer portion serving as the second-conductivity-type region or the first-conductivity-type region in the intermediate area.

Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

Abstract: A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first major electrode of the die. The thin metal clip has a relatively large surface area, and package resistance which is caused by skin effect phenomenon is reduced thereby in high frequency applications.

Abstract: An InGaAs photodetector is provided having an avalanche photodiode (APD), a p-intrinsic-n (PIN) photodiode, and a microlens structure that provides high optical fill factors for both the APD and the PIN photodiodes. The photodetector can be used for both ranging and imaging applications, can be formed as a single pixel, and multiple pixels can be fabricated to form a focal plane array. A method of fabricating the photodiode is also provided.

Abstract: A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.

Abstract: A method of producing a metal element of an electronic device on a substrate, including the steps of: forming a mixture of a material comprising metal atoms with a liquid, depositing the material from the liquid mixture onto a substrate, and then irradiating at least part of the deposited material with light to increase the electrical conductivity of the deposited material.

Abstract: An improved electrostatic discharge (ESD) protection structure that is suitable for use in a large-scale CMOS circuit fabrication technology is disclosed. When surge energy enters the first conductor during an ESD event, the surge current is conducted through the first contacts of the first MOS transistors, the second contacts of the first MOS transistors, the fourth conductor, and the third contacts of the second transistors. As each third contact is paired with each second contact, the surge current is conducted from a second contact to the paired third contact. Then, the surge current is conducted through the third contacts, fourth contacts, and the second conductor. In this operation, electric fields are generated in the direction of the first contacts, the second contacts, the fourth conductor, the third contacts, and the fourth contacts.

Abstract: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields.

Abstract: A method of driving a solid-state image sensing device comprises plural photoelectric conversion devices arranged in rows and columns perpendicular to the rows, VCCDs through which charges generated by the photoelectric conversion devices are transferred in the column direction, and an HCCD through which the charges transferred from the VCCDs are transferred in the row direction. The photoelectric conversion devices include plural photoelectric conversion device rows including the photoelectric conversion devices arranged in the rows include first photoelectric conversion device rows each of which different kinds of photoelectric conversion devices are mixed and second photoelectric conversion device rows each of which has one kind of photoelectric conversion devices.

Abstract: A solid state image pickup device includes: a semiconductor substrate; a well formed in a surface layer of the semiconductor substrate; a light reception region formed in the well and including a plurality of charge accumulation regions formed in a matrix shape and a plurality of vertical CCDs formed along each column of the charge accumulation regions; a horizontal CCD formed in the well and coupled to ends of the vertical CCDs; a peripheral circuit formed in the well in partial regions of the light reception region and the horizontal CCD; a shield layer formed on the semiconductor substrate including a partial area above the peripheral circuit, made of conductive material and surrounding the light reception region, the shield layer being electrically connected to the semiconductor substrate; a support disposed above the shield layer and made of conductive material; and a translucent member placed on the support.

Abstract: A photoelectric conversion device comprising: an inorganic photoelectric conversion film; and an organic photoelectric conversion film, wherein an insulating film between the inorganic photoelectric conversion film and the organic photoelectric conversion film has a thickness of from 1 to 6 ?m, wherein the organic photoelectric conversion film has a multilayer structure comprising four or more layers, or wherein a protective film having a multilayer structure comprising three or more layers is provided on the organic photoelectric conversion film.

Abstract: A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.

Abstract: Disclosed is a gas permeable electrode comprising an electrocatalyst which is permeable to a reactant or reaction product, the electrocatalyst comprising particulate boron-doped diamond. There is also disclosed a method of making an electrocatalyst which is permeable to a reactant or reaction product, the method comprising the step of forming an electrocatalyst comprising particulate boron-doped diamond.

Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

Abstract: The present invention is to provide a memory device including: a plurality of memory cells that each include a memory element having a memory layer and first and second electrodes that sandwich the memory layer, the plurality of memory cells being divided into memory blocks of m columns by n rows (m and n are each an integer of not less than 1, m+n?3), the memory elements in the same memory block having the first electrode that is formed of a single layer in common to the memory elements; and a voltage application unit that applies any voltage to the first electrode of the memory block.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.

Abstract: Provided are an n-type carbon nanotube field effect transistor (CNT FET) and a method of fabricating the n-type CNT FET. The n-type CNT FET may include a substrate; electrodes formed on the substrate and separated from each other; a CNT forrmed on the substrate and electrically connected to the electrodes; a gate oxide layer formed on the CNT; and a gate electrode formed on the gate oxide layer, wherein the gate oxide layer contains electron donor atoms which donate electrons to the CNT such that the CNT may be n-doped by the electron donor atoms.

Abstract: A method of forming a pixel of an image sensor with reduced etching damage is disclosed. The method first includes forming a light sensitive element in a substrate. Then, a transfer gate is formed atop the substrate and adjacent to the light sensitive element. A protective layer, such as an anti-reflective coating, is then formed over the light sensitive element. A blanket oxide layer is formed over the protective layer and the transfer gate. Finally, the oxide layer is etched back to form a sidewall spacer the sidewall of a gate stack. The protective layer protects the surface of the light sensitive element from etching damage.

Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof.

Abstract: An imaging device having a pixel array in which one plate of a storage capacitor is coupled to a storage node while another plate is formed by an electrode of a photo-conversion region.

Abstract: One photodetection system includes a wide bandgap photodetector array which is physically and electrically integrated on a flexible interconnect layer including electrical connections, which is packaged in a manner for being electrically integrated with processing electronics such that the packaging and the processing electronics are configured for obtaining and processing signals detected by the photodetector array, or which includes both the flexible interconnect layer and processing electronics packaging features. Another photodetection system includes a wide bandgap focal plane array module including a photodetector pixel array, scan registers, a substrate supporting the array and the scan registers, and electrical interconnections coupling each pixel to at least two of the scan registers.

Abstract: Image sensor devices are provided having reduced dark current generation characteristics. These image sensor devices include a semiconductor substrate and a photo-detector therein (e.g., P-N photodiode). The photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers. A first transistor, which has a terminal configured to receive the charge carriers generated by the photo-detector, is also provided. The first transistor includes a first gate electrode and a first pair of lightly doped source and drain regions of unequal width on opposite sides of the first gate electrode. This first transistor may be a three-terminal device and the terminal that is configured to receive the charge carriers may be selected from a group consisting of a gate, source and drain terminals. In particular, the first transistor may be configured as a reset transistor or as a source-follower transistor.

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract: A solid-state imaging device is formed on a silicon substrate for providing a MOS type solid-state imaging device which has a device isolation structure and causes a small amount of leak current. The solid-state imaging device includes, for each pixel, an imaging region which includes a photodiode having a charge accumulation region of a first conductivity type, a transistor and a device isolation region whose depth is less than a depth of the charge accumulation region of the first conductivity type, at which an impurity density is at maximum.

Abstract: An isolation region formed in a substrate and lined with a transparent metal layer. The isolation region provides isolation between adjacent active areas of an integrated circuit structure, for example the inventive region may provide isolation between pixels of a pixel array. Utilizing a transparent material maintains high quantum efficiency of the pixels as photons are not blocked from penetrating into the substrate. In one exemplary embodiment, a shallow trench isolation region is formed in a substrate, lined with an oxide or other dielectric, and an indium-tin-oxide shielding layer is formed over the oxide. The lined trench may then be filled with either the transparent metal material or a transparent insulating material.

Abstract: An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size relative to the pixel.

Abstract: Provided is a CMOS image sensor and a manufacturing method thereof. The CMOS image sensor includes a gate electrode, a photodiode, a transistor region, and a light blocking material. The gate electrode is formed on a semiconductor substrate with an intervening gate insulating layer. The photodiode region is formed on one side of the gate electrode. The transistor region is formed on another side of the gate electrode. The light blocking material is formed on the transistor region to block light from reaching the transistor region.

Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.

Abstract: Articles are provided including a base substrate having a layer of an IBAD oriented material thereon, and, a layer of barium-containing material selected from the group consisting of barium zirconate, barium hafnate, barium titanate, barium strontium titanate, barium dysprosium zirconate, barium neodymium zirconate and barium samarium zirconate, or a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the layer of an IBAD oriented material. Such articles can further include thin films of high temperature superconductive oxides such as YBCO upon the layer of barium-containing material selected from the group consisting of barium zirconate, barium hafnate, barium titanate, barium strontium titanate, barium dysprosium zirconate, barium neodymium zirconate and barium samarium zirconate, or a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates.

Abstract: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors (101) and along a dicing line (110) inside the dicing line (110).

Abstract: A semiconductor device includes a MOS transistor having a capacitor-forming surface; and a ferroelectric capacitor formed on the capacitor-forming surface of the MOS transistor and including upper and lower electrode layers of Pt and a dielectric layer sandwiched between the upper and lower electrode layers. The ferroelectric capacitor has a cross-section that is generally trapezoid in shape, and that has an inclined side which forms an angle of greater than 45 degrees and less than 90 degrees with the capacitor-forming surface of the MOS transistor.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.

Abstract: A NAND type flash memory device includes a semiconductor substrate, word lines, first and second selection lines, tunnel insulation layers, and selection gate insulation layers. The semiconductor substrate includes a memory transistor region and a selection transistor region. The word lines are arranged in the memory transistor region of the semiconductor substrate, and the selection lines are arranged in the selection transistor region of the semiconductor substrate. The tunnel insulation layers are interposed between the word lines and the semiconductor substrate, and the selection gate insulation layers are interposed between the selection lines and the semiconductor substrate and have a thinner thickness than the thickness of the tunnel insulation layers. Also, the selection gate insulation layers have a thinner thickness in their center region than in their edge portions.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Abstract: The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.

Abstract: This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. A second series capacitive structure disposed in a second insulating trench can be employed to terminate the device.

Abstract: A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure.

Abstract: A nanowire capacitor and methods of making the same are disclosed. The nanowire capacitor includes a substrate and a semiconductor nanowire that is supported by the substrate. An insulator is formed on a portion of the surface of the nanowire. Additionally, an outer coaxial conductor is formed on a portion of the insulator and a contact coupled to the nanowire.

Abstract: a phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change layer formed on top of the nanowires. Therefore, a reset or a set current consumed by the PRAM device is significantly reduced.

Abstract: Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then, an immersion plating process is used to replace the atoms of the sacrificial layer with atoms of a desired metal, such as platinum, thereby creating a metal cap isolated within the via. The advantages of planarization to isolate material within recessed via are thus obtained without having to planarize or otherwise etch the desired metal. The cap layer can be further reacted to form a barrier compound prior to forming a capacitor over the plug. Advantageously, the plug structure resists oxidation during fabrication of overlying capacitors that incorporate high dielectric constant materials.

Abstract: Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.

Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.

Abstract: A nonvolatile semiconductor memory according to an example of the present invention is provided with a memory cell having a floating gate electrode and a control gate electrode, and a select gate transistor having a select gate electrode and connected in series to the memory cell. A cell unit is comprised with the memory cell and the select gate transistor. A bird's beak of the edge at the memory cell side of the select gate electrode is larger than a bird's beak of at least one edge of the floating gate electrode.

Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first-stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Abstract: A method for manufacturing and operating a nonvolatile memory in which a floating gate is formed on a silicon substrate to reduce the difference in heights between a memory region and a logic region so that a process margin is assured.

Abstract: The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate, and each of the recess is interposed between two adjacent dielectric strips. The bit lines are respectively formed on the dielectric strips. The dielectrically stacking multi-layer comprising a charge-trapping layer is disposed on the bit lines and the recesses. The word lines are formed on the dielectrically stacking multi-layer and intersecting to the bit lines. When a voltage is applied to the bit lines, a plurality of inversion regions are respectively generated on the substrate.