Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.

Abstract: A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

Abstract: A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.

Abstract: A pin grid array package, comprising a substrate, a chip mounted abutting said substrate, and a plurality of pins electrically connected to said substrate, each pin comprising a substantially flat disc at an end of the pin opposite the substrate, said disc oriented perpendicular to said pin. The substrate contains metal traces to transfer electrical signals between the chip and each pin, wherein said disc is usable to provide each pin an electrical connection to a structure external to the package.

Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

Abstract: A printed wiring board is provided which includes an interlayer dielectric layer formed on a substrate from a curable resin having flaky particles dispersed therein. The printed wiring board is excellent in cooling/heating cycle resistance and packaging reliability while maintaining a satisfactory heat resistance, electrical insulation, heat liberation, connection reliability and chemical stability. Also a method of producing a printed wiring board is proposed in which an imprint method using a mold having formed thereon convexities corresponding to wiring patterns and viaholes to be formed being buried in an interlayer dielectric layer is used to form the wiring patterns and viaholes by transcribing the concavities of the mold to the interlayer dielectric layer. The imprint method permits to form the wiring patterns and viaholes but assures an easy and accurate transcription without any optical transcription or complicated etching.

Abstract: This invention is novel structure of an over-current protection device and manufacturing method thereof. The over-current protection device is formed with a main body with a lead frame and a ceramic fiber lead wound by a metal wire exteriorly, by coating the exterior of the whole lead with a thermally-insulating material, and then cladding the lead with a flame retardation material having an electrical insulation characteristic.

Abstract: A multichip circuit module includes a main board, at least one carrier substrate mounted on and in electrical contact with the main board, and at least one semiconductor chip arranged on the carrier substrate and in electrical contact therewith. The carrier substrate has at least one cavity on an assembly surface for receiving the semiconductor chip. The cavity includes connecting contacts which join with associated bumps on the semiconductor chip using a flip-chip technique. The assembly surface of the carrier substrate is placed on a contact surface of the main board, and a filling material is provided between the contract surface of the main board and the assembly surface of the carrier substrate.

Abstract: A MEMS package and methods for its embodiment are described. The MEMS package has at least one MEMS device mounted on a flexible and foldable substrate. A metal cap structure surrounds the at least one MEMS device wherein an edge surface of the metal cap structure is attached to the flexible substrate and wherein a portion of the flexible substrate is folded under itself thereby forming the MEMS package. A meshed metal environmental hole underlying the at least one MEMS device provides enhanced EMI immunity.

Abstract: A semiconductor device mountable to a substrate includes: a semiconductor die; an electrically conductive attachment region having a first attachment surface and a second attachment surface, the first attachment surface arranged for electrical communication with the semiconductor die; an interface material having a first interface surface and a second interface surface, the first interface surface in contact with the second attachment surface of the electrically conductive attachment region; a thermally conductive element in contact with the second interface surface; and a housing at least in part enclosing the semiconductor die and affixed to the thermally conductive element. The thermally conductive element and the housing form exterior packaging of the semiconductor device. Heat is removable from the semiconductor die to the exterior packaging via a thermal conduction path formed by the electrically conductive attachment region, the interface material, and the thermally conductive element.

Abstract: A thermally conductive material that includes an alloy which includes indium, zinc, magnesium or a combination thereof is described herein. Also, a semiconductor package comprising a thermal interface material which includes solder and particles dispersed throughout the solder, the particles being of thermal conductivity greater than or equal to about 80 W/m-K is described herein. In one described embodiment, a semiconductor package includes a thermal interface material which includes at least one lanthanide element. In yet another embodiment disclosed herein, a solder preform construction includes a solder and a structure within the solder, the solder being of a first composition and the structure being of a second composition which has a lower melting point than the first composition.

Abstract: A thermionic or thermotunneling gap diode device consisting of two silicon electrodes maintained at a desired distance from one another by means of spacers. These spacers are formed by oxidizing one electrode, protecting certain oxidized areas and removing the remainder of the oxidized layer. The protected oxidized areas remain as spacers. These spacers have the effect of maintaining the electrodes at a desired distance without the need for active elements, thus greatly reducing costs.

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract: In accordance with the invention, a multicolor LED assembly with improved color mixing comprises an assembly of closely-packed LED dice of different colors packaged for high temperature operation and arranged to minimize same-color adjacency to promote color mixing. The assembly of dice is encapsulated in a dispersive medium such as a transparent medium with entrained dispersive particles. The packaged assembly preferably includes a layer having light dispersing particles deposited directly on the LED.

Abstract: A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

Abstract: A semiconductor power module has at least one power semiconductor chip (2) which can be controlled by the field effect and has a plurality of fail-safe, small-area SiC power diodes (D1 to D8). The function of a large-area SiC power diode chip which is susceptible to failure is distributed over these small-area, parallel-connected SiC power diode chips (D1 to D8) in such a way that their total area of active SiC diode areas (F1 to F8) corresponds to an area extent of a large-area non-fail-safe SiC power diode chip.

Abstract: Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing the first wire-bonded die. That is, the first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.

Abstract: The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters (100) disposed within printed circuit boards (104). The heat sink (110, 200) is a thermal conductive material disposed within a cavity (102) of the printed circuit board (104) and is thermally coupled to a bottom surface (112) of the electrical-to-optical transmitter (100). A portion of the thermal conductive material extends approximately to an outer surface (120, 122 or 124) of a layer (114, 116 or 118) of the printed circuit board (104). The printed circuit board may comprise a planarized signal communications system or an optoelectronic signal communications system. In addition, the present invention provides a method for fabricating the heat sink wherein the electrical-to-optical transmitter disposed within a cavity of the printed circuit board is fabricated. New methods for flexible waveguides and micro-mirror couplers are also provided.

Abstract: A semiconductor device includes: a semiconductor substrate having a first face in which a hole is formed; an insulating section made of an insulating material, the insulating material accommodated in the hole; and a wire having a turning pattern and arranged on the insulating section.

Abstract: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The group of mating bumps is positioned such that if the alignment bump engages each of the mating bumps, the die is appropriately positioned relative to the substrate at that location where the alignment bump engages the group of mating bumps. In some embodiments, the alignment bump extends from the substrate while in other embodiments the alignment bump extends from the die. The alignment bump on the substrate (or die) may be part of a plurality of alignment bumps such that each alignment bump engages a different group of mating bumps on the die (or substrate).

Abstract: External connection terminals 27 which are electrically connected to semiconductor chips 11-1, 11-2, 12-1, 12-2 and also protrude beyond the semiconductor chips 11-1, 11-2, 12-1, 12-2 are disposed on a substrate 13 of the side to which the plural semiconductor chips 11-1, 11-2, 12-1, 12-2 are connected.

Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.

Abstract: A semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of preparing a chip having a plurality of conductive bumps formed on an active surface thereof; preparing a tape having a first surface and an opposed second surface, wherein the tape has a plurality of through holes at positions corresponding to the conductive bumps; forming an adhesive layer on the first surface of the tape, and disposing a plurality of leads on the second surface of the tape, so as to make an end of each of the leads covers a corresponding through hole; mounting the active surface of the chip to the adhesive layer on the first surface of the tape and allowing each of the conductive bumps to be received in a corresponding through hole; and performing a heat pressing process to bond the ends of the leads to the conductive bumps in the corresponding through holes.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: An integrated circuit package and method exploit the volume enclosed by the package substrate vias. In one embodiment, an integrated circuit package includes a first substrate having electrically conductive layers formed on substantially parallel surfaces of the first substrate, a second substrate having electrically conductive layers formed on substantially parallel surfaces of the second substrate, a substrate via formed through the first substrate and the second substrate to form an electrical connection between at least two electrically conductive layers of the first substrate and between at least two electrically conductive layers of the second substrate, an electrical component having a first end and a second end inserted into the substrate via so that the first end extends at least partially inside the first substrate and the second end extends at least partially inside the second substrate, and an electrically insulating layer formed between the first substrate and the second substrate.

Abstract: A multilayer wiring structure for connecting a semiconductor device is disclosed which is obtained by forming metal wirings on a substrate in which the semiconductor device is formed. The wiring structure free from such conventional problems that insulation between wirings next to each other is damaged or insulation resistance between wirings next to each other is deteriorated by generation of leakage current when fine metal wirings are formed in a porous insulating film. A method for producing such a wiring structure is also disclosed. In the metal wiring structure on the substrate in which the semiconductor device is formed, a insulating barrier layer (413) containing an organic matter is formed between an interlayer insulating film and a metal wiring. This insulating barrier layer reduces leakage current between wirings next to each other, thereby improving insulation reliability.

Abstract: Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.

Abstract: A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being

Abstract: A modular containment system which has a plurality of stackable building elements, including two or more peripheral sidewall members, a roof and a base. Means are provided for coupling each of the building elements to an adjoining building element. The building elements are stacked such that the two or more peripheral sidewall members are stacked on top of the base and the roof is stacked on top of the two or more sidewall members.

Abstract: A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the second conductive layer. An interlayer insulator has a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on the first layered film. The interlayer insulator is formed covering the first conductive layer and the second conductive layer.

Abstract: Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer and including copper or a copper alloy.

Abstract: A bumpless chip package including at least a chip and an interconnection structure is provided. Wherein, the chip has a die pad arrangement disposed on an active surface of the chip. The die pad arrangement includes a plurality of point-shaped pads and at least a non-point-shaped pad. The area of the non-point-shaped pad is greater than or equal to the area of two point-shaped pads. The chip is embedded within the interconnection structure. The interconnection structure has an inner circuit and a plurality of contact pads. The contact pads are disposed on a contact surface of the interconnection structure. Moreover, at least one of the point-shaped pads and the non-point-shaped pad is electrically coupled to at least one of the contact pads through the inner circuit. Furthermore, the non-point-shaped pad with a larger cross-sectional area for power or ground signal can enhance the electric characteristic of the bumpless chip package.

Abstract: A voltage regulator on a first chip is embedded in a core. The voltage regulator on a chip and the core are part of an integral package. The package can include a microelectronic device on a second chip. The voltage regulator is disposed on a bumpless, build-up layer structure. The voltage regulator has a first active surface and the microelectronic device has a second active surface. The first active surface faces the second active surface.

Abstract: The invention relates to an electronic module with a plurality of IC chips staked densely. The electronic module includes a substrate with an electrode formed thereon and at least one spacer disposed on the substrate. The electronic module also includes an IC chip disposed on the spacer and electrically connected to the substrate. The IC chip has a size larger than the spacer. The substrate and the IC chip forms a space therebetween. The invention miniaturizes and minimizes circuit connections and configurations between the IC chips and chip components to minimize electric resistance and inductance, thereby enhancing product capabilities. Also, the invention achieves miniaturization and integration of mobile products such as mobile phones to improve product competitiveness.

Abstract: A disclosed semiconductor device comprises a substrate, an element on the substrate and a sealing structure for sealing the element. The sealing structure has a structure such that a partition wall made of a metallic material formed on the substrate by a plating method so as to surround the element and a cap portion disposed on the partition wall are bonded via a bonding layer made of an inorganic material.

Abstract: Improvement in the mountability of a semiconductor device is aimed at. By preparing a package substrate which has a plurality of lands of NSMD structure, and the taking-out wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is aimed at.

Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached face down to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.

Abstract: The carburetor prevents an air-fuel mixture from becoming excessively lean and prevents a fuel pressure from becoming unstable, thereby making it possible to stably supply a fuel to an engine, in a diaphragm-type carburetor with a pressure regulating means. A diaphragm-type carburetor includes a fuel pump using a pulsation pressure generated in a crank chamber of an engine or an intake pipe as a driving force, and a metering chamber having a diaphragm and a lever mechanism and provided with fuel at a desired constant pressure. The diaphragm-type carburetor includes a bubble discharge path connecting the metering chamber to other predetermined discharge portions and with a check valve in each of an inlet side and an outlet side.

Abstract: Replacement of the fuel metering jets of an internal combustion engine carburetor, such as a Holley.RTM. or Demon.RTM. Carburetor is greatly simplified by fuel float bowls which permit the jets to face upward. The jets are removed through access holes in the upper wall of the float bowl by a screwdriver/gripping tool. The float has access holes which are aligned to the upper wall holes to provide direct access to the fuel metering jets.

Abstract: A speed-increasing machine for water includes a frame member, a plurality of buoyant members mounted to the lower end of the frame member, a motor mounted to the center of the frame member, and a shielding cover mounted outside the motor. A rotating shaft of the motor is attached to a guide vane set. The guide vane set has a plurality of guide plates for guiding the circulating water current. When driving the motor, the vanes rotate to circulate the water in the cultivation pool, to thereby uniformly increase the dissolved oxygen in the cultivation pool.

Abstract: A carburetor utilizing a compact main fuel delivery device that provides fine droplets of fuel spread across an airflow orifice. The main fuel delivery device does not require the use of a main jet or emulsion well prior to the point of the fuel interacting with the atmosphere of the air flow orifice or venturi. The airflow orifice and other mixture forming components of the carburetor are contained within plates and formed by the assemblage of the plates. A centrally located bolt provides the securing and sealing force necessary for operation of the carburetor. The entire above the fuel level mixture controlling systems can be removed from the carburetor after unfastening the central bolt. It is not necessary to drain the carburetor of fuel to change the jetting or other settings of the carburetor.

Abstract: The present invention provides an aeration device comprising a rectangular elastic porous body, a support base supporting the elastic porous body from below and having an orifice for pressurized air, and a securing component which secures the elastic porous body to the support base integrally, wherein the support base comprises a supporting portion supporting the elastic porous body from below and an attaching portion connected to the supporting portion and attaching the supporting portion to a pressurized air distribution pipe, the rectangular elastic porous body having a box shape having an opening portion, and the supporting portion being disposed in an elastic porous body. In addition, the present invention provides an aeration system comprising two or more above described aeration devices installed on a pressurized air distribution pipe, wherein each aeration device is disposed contacting mutually with no space between.

Abstract: There is provided a method of sealing and molding an optical device with resin by employing a die including a top piece, a bottom piece, an intermediate piece, and a mold release film pinched between the bottom and intermediate pieces and thus tensioned as prescribed to cover the bottom piece's cavity, when the bottom piece is heated, and the mold release film expands and thus closely contacts the cavity's entire surface along the cavity's geometry so that the optical device can be sealed in transparent set resin shaped as desired.

Abstract: The inventive device includes a first shell holder (6) for fixing a first shell (12), a second shell holder (27) for fixing a second shell (29), a first support (1) on which the first shell holder (6) is mounted and a second support (2) on which the second shell holder (27) is mounted, the first (1) and second (2) supports being pivotable with respect to each other. When the first (1) and second (2) supports are in a first relative position thereof they are arranged oppositely to each other, thereby bringing the first (12) and second (29) shells into a predetermined relative moulding position thereof. When the first (12) and second (29) shells are brought into the second relative position thereof, the first (1) and second (2) supports are removed from each other by pivoting motion.

Abstract: To effectively prepare granular urea that constantly has a moisture concentration of 0.3 wt % or less in the product and has a large grain load strength to be hardly crashed. In a granulating process for preparing granular urea from an aqueous urea solution using a fluidized bed method or a fluidized, spouted bed method, an aqueous urea solution having an urea concentration of 94-98.5 wt % is used, and an operation temperature of the fluidized bed is controlled in a range of 110-120° C. to accelerate drying of a granulated product, thereby giving a granular urea product having moisture of 0.3 wt % or less in the product.

Abstract: A process for the production of green ceramic preforms for dental parts involves introducing a model into ceramic slip in a slip container for coating the model. Ceramic slip is controllably drawn off from the slip container and the coated model removed. An apparatus for producing green ceramic preforms includes an opening in the slip container through which flow of the ceramic slip is controllable. The green ceramic preform may be used to produce a dental part. Conduit means are so arranged on the slip container that ceramic slip can be controlledly drawn off out of the slip container through the conduit means.