Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.

Abstract: A thin film transistor includes a one conductive type semiconductor layer (11); a source region (12) and a drain region (13) which are separately provided in the semiconductor layer; and a gate electrode (14) provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width (Ws) of the junction face between the source region and the channel (16) which is provided between the source region and drain region, is different from the width (Wd) of the junction face between the above channel region and the drain region.

Abstract: A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.

Abstract: A substrate for an electronic device formed in a group III nitride material system comprises a layer of silicon carbon and a layer of silicon carbon germanium over the layer of silicon carbon, the layer of silicon carbon and the layer of silicon carbon germanium forming a substrate for a device formed in the group III nitride material system.

Abstract: The invention relates to a white light emitting LED lamp. The LED lamp comprises an LED emitting blue light and luminescent layer for converting a part of the blue light into light having a longer wavelength. According to the invention either a dye is provided for absorbing a part of the blue light emitted by the LED or a light reflecting layer is provided for selectively reflecting a part of the blue light emitted by the LED. Thus the proportion of the blue light is reduced which results in a reduced color temperature without having a negative effect on the color rendering and only reducing the total luminous flux by a small amount, which is more efficient than using a thicker luminescent coating.

Abstract: A semiconductor light-emitting device includes a light-emitting layer and a light extraction layer formed on the light-emitting layer and made of a resin material containing particles. The maximum size of each of the particles contained in the light extraction layer is smaller than the wavelength of emitted light penetrating through the light extraction layer.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. In the CMOS image sensor, a device isolation layer is formed in a substrate to define an active region, and a photodiode is formed in the active region. A floating diffusion region is formed at a position spaced apart from the photodiode, and first and second gates are overlapped with one end of the photodiode and one end of the floating diffusion region, respectively. A third gate is disposed between the first gate and the second gate and overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region. An insulating layer is formed on the resulting structure where the third gate is formed. A buried contact has a first contact and a second contact, which are sequentially stacked to pass through the insulating layer and the third gate and to connect the third gate to the floating diffusion region disposed under the third gate.

Abstract: In an array of LEDs coupled between a transparent substrate and an electrode, a light emitting surface of each LED is in electrical contact with a region of acicular ITO. By contacting the light emitting surface of the die, the acicular ITO also provides light scattering. The contact regions are interconnected to form the array. The acicular ITO acts as a ballast resistance for each die and the resistance can be trimmed for more uniform current among the LEDs. Because each LED is individually ballasted, the LEDs in an array can be driven in any pattern or all simultaneously at a consistent brightness.

Abstract: Includes a stem with a hole, a dielectric sealed into the hole of the stem and including a pair of pin insertion holes, and a pair of high frequency signal pins that penetrate and fit into the pair of pin insertion holes of the dielectric, and constituting differential lines connected to an optical semiconductor element.

Abstract: A semiconductor apparatus includes a substrate; m electrically conductive layers formed on the substrate, m being an integer of 2 or more, potentials of the m electrically conductive layers being capable of being independently controlled; and semiconductor thin films having at least one semiconductor device respectively. The semiconductor thin films are bonded on surfaces of the m electrically conductive layers respectively.

Abstract: A semiconductor light emitting element has a first conductive-type cladding layer, an undoped active layer, a second conductive-type cladding layer, and a second conductive-type current spreading layer that are formed on a first conductive-type semiconductor substrate. The second conductive-type cladding layer has a first dopant suppressing layer formed at a portion in the second conductive-type cladding layer, the portion being not in contact with the active layer. The first dopant suppressing layer has a dopant concentration lower than a region in the vicinity of the first dopant suppressing layer.

Abstract: An LED lighting source preventing heat deterioration and improving luminous efficiency includes a mounting substrate having a wiring pattern on a first main surface thereof and a plurality of LED bare chips, each composed of a first semiconductor layer and a second semiconductor layer having respectively different conductivity, an active layer disposed therebetween, and a metal electrode on the first semiconductor layer and substantially equal in area thereto, and each LED bare chip being joined to the wiring pattern according to flip chip mounting of the metal electrode to form a junction between the wiring pattern and the metal electrode. Each junction is formed so that an area thereof is at least 20% of the area of the metal electrode. Thermal resistance from the active layers through to a second main surface of the mounting substrate, which is a back surface thereof, is set to 3.0 9C./W or lower.

Abstract: An optical semiconductor device includes a first light receiving region and a second light receiving region provided on a substrate and the first and second light receiving regions include light receiving elements, respectively. A first anti-reflection film is formed in the first light receiving region of the substrate and a second anti-reflection film is formed in the second light receiving region of the substrate. The reflectance of the first anti-reflection film for a first wavelength range of light is lower than the reflectance of the second anti-reflection film for the first wavelength range of light and the reflectance of the second anti-reflection film for a second wavelength range of light which is different from the first wavelength range of light is lower than the reflectance of the first anti-reflection film for the second wavelength range of light.

Abstract: A light emitting diode is provided. The diode includes: a substrate; a first nitride gallium layer disposed above the substrate; a first electrode provided at one portion of and above the first nitride gallium layer; an active layer provided above the first nitride gallium layer, for emitting light; a second nitride gallium layer provided above the active layer; and transparent electrodes spaced apart from one another above the second nitride gallium layer.

Abstract: A semiconductor light-emitting device has a first conductivity type semiconductor layer (3, 4), a luminous layer (5) formed on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer (8) formed on the luminous layer, and a transmissive substrate (9) which is formed on the second conductivity type semiconductor layer (8) and is pervious to light coming from the luminous layer (5). The transmissive substrate (9) has a carrier concentration lower than that of the second conductivity type semiconductor layer (8).

Abstract: A first cladding layer of a first conductivity type formed above a crystal substrate, an active layer formed above the first cladding layer, a diffusion prevention layer formed on the active layer and preventing an impurity from diffusing into the active layer, an overflow prevention layer of a second conductivity type, the second conductivity type being different from the first conductivity type, which is formed on the diffusion prevention layer and prevents an overflow of carriers implanted into the active layer, and a second cladding layer of the second conductivity type formed above the overflow prevention layer are provided.

Abstract: An optoelectronic chip having a semiconductor body (14), which contains a radiation-emitting region (2), and a partial region (3) in which the surface (13) of the semiconductor body (14) is curved convexly toward a carrier (10). The lateral extent (2r) of the radiation-emitting region (2) is less than the lateral extent (2R) of the partial region (3). A method for producing such a chip is also described.

Abstract: A nitride-based semiconductor light emitting device with improved characteristics of ohmic contact to an n-electrode and a method of fabricating the same are provided. The nitride-based semiconductor light emitting device includes an n-electrode, a p-electrode, an n-type compound semiconductor layer, and an active layer and a p-type compound semiconductor layer formed between the n- and p-electrodes. The n-electrode includes: a first electrode layer formed of at least one element selected from the group consisting of Pd, Pt, Ni, Co, Rh, Ir, Fe, Ru, Os, Cu, Ag, and Au; and a second electrode layer formed on the first electrode layer using a conductive material containing at least one element selected from the group consisting of Ti, V, Cr, Zr, Nb, Hf, Ta, Mo, W, Re, Ir, Al, In, Pb, Ni, Rh, Ru, Os, and Au.

Abstract: A light emitting diode package is provided. The light emitting diode package comprises a submount substrate which includes a mounting region having side walls inclined upwardly, first and second cavities formed around the mounting region, and first and second grooves extending between the mounting region and the first and second cavities on an upper surface of the submount. The package further comprises first and second bump pads formed on a bottom surface of the mounting surface, first and second bonding pads formed on a bottom surface of the first and second cavities, respectively, first and second conductive lines formed along a bottom surface of the first and second grooves for connecting the first and second bump pads to the first and second bonding pads, respectively, and a light emitting diode mounted on the mounting region so as to be connected to the first and second bump pads.

Abstract: It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an electrode main entirely or mostly of silver having high reflection efficiency is formed in contact with a nitride semiconductor layer. A semiconductor element comprises a nitride semiconductor layer, an electrode connected to said nitride semiconductor layer, and an insulating film covering at least part of said electrode, wherein the electrode comprises: a first metal film including silver or a silver alloy and in contact with the nitride semiconductor layer; and a second metal film completely covering the first metal film, and the insulating film comprises a nitride film.

Abstract: A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the semiconductor die, the L-shaped area having first and second inner sides that are respectively disposed adjacent first and second sides of the control circuit. At least one of the first and second output transistors is coupled to the control circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A semiconductor device includes a field effect transistor and a pn junction diode formed on a substrate. The field effect transistor has a source electrode, a drain electrode and a gate electrode formed on an element forming layer including a plurality of nitride semiconductor layers. The diode includes a p-type nitride semiconductor layer selectively formed on the element forming layer and an ohmic electrode, and has a pn junction formed between an n-type region of a two-dimensional electron gas generated on a heterojunction interface and a p-type region of the p-type nitride semiconductor layer. The diode is electrically connected to the gate electrode and forms a current path for allowing an excessive current caused in the gate electrode to pass.

Abstract: A gate insulating film is formed using a plasma on a three-dimensional silicon substrate surface having a plurality of crystal orientations. The plasma gate insulating film experiences no increase in interface state in any crystal orientations as compared with tat in Si (100) crystal orientation and has a uniform thickness even at corner portions of the three-dimensional structure. By forming a high-quality gate insulating film using a plasma, there can be obtained a semiconductor device having good characteristics.

Abstract: A semiconductor rectifier has a semiconductor layer formed on a substrate, an electric field reduced layer of conductive type contrary to that of the semiconductor layer, which is formed on the semiconductor layer positioned on a bottom portion of a trench formed on a portion of the semiconductor layer, a first electrode connected on the semiconductor layer adjacent to the trench by Schottky junction, a second electrode which is connected on sidewalls of the trench by Schottky junction, electrically conductive with the first electrode and made of a material different from that of the first electrode, and a third electrode formed on the substrate at opposite side of the semiconductor layer.

Abstract: A semiconductor device includes a surface layer on the side of a first principal surface of a p-semiconductor substrate, a high side n-isolation-diffused region and a low side n-isolation-diffused region formed apart from each other by a distance that is shorter than the diffusion length of electrons in the p-semiconductor substrate. In a region between the high side n-isolation-diffused region and the low side n-isolation-diffused region, a p-region is formed which has a higher impurity concentration than the p-semiconductor substrate. A first electrode in contact with the p-region and a second electrode in contact with a second principal surface of the p-semiconductor substrate are brought to be at the ground potential. This, at switching of a low side IGBT, makes a charging or discharging current flowing from the high side n-isolation-diffused region flow toward the back surface of the substrate to be taken out from the second electrode.

Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.

Abstract: A memory cell arrangement, which has a size of 8F2 per memory cell, wherein F is a unit of length, comprises a plurality of active regions along a first direction in a semiconductor substrate, a plurality of parallel buried word lines along a second direction in the semiconductor substrate, a plurality of parallel bit lines with a folded bit line arrangement along a third direction at the surface of the semiconductor substrate, and a plurality of storage capacitors. The buried word lines run through the active regions, two of the buried word lines that are spaced apart from one another and from the isolation trenches run through a respective active region, and the buried word lines are insulated from a channel region in the semiconductor substrate by a gate dielectric layer. The bit lines run perpendicular to the second direction, wherein each bit line runs through an associated active region and makes contact with the relevant source zone of the associated active region.

Abstract: A driving method is applied to a solid-state imaging apparatus having photoelectric conversion portions, transfer portion for reading out signal charges, and an excess charge draining portion for draining charges exceeding a saturation charge amount that is set by a reference voltage. One of driving modes is selected from a full pixel mode in which accumulated signal charges are detected individually for each pixel and a pixel mixing mode in which signal charges of a predetermined number of pixels are mixed to be detected. In the full pixel mode, the draining portion is supplied with the reference voltage having the same value during a charge accumulation period and a read transfer period for read transferring charges. In the pixel mixing mode, the draining portion is supplied with the reference voltage having a low level during the charge accumulation period and the reference voltage having a high level during the read transfer period.

Abstract: In one aspect of the present invention, a light sensor is provided in the active pixel sensor cell for sensing incident radiation. The voltage corresponding to the photon-generated or other radiation-generated charge in the active pixel sensor cell is stored on a storage node via a sample-and-hold capacitor. Additional elements, such as source-follower transistors, may reside between the sensing element and the sample-and-hold capacitor. The signal is read via a readout source-follower (RSF) transistor. The readout source-follower drain is connected to the row select switch while its drain is connected to the output node on the column output bus. This configuration couples the storage node to the gate-source capacitance of the readout source-follower transistor. This allows the voltage on the storage node to increase proportionally to the increase in voltage on the readout node when the row select is closed and thus enables the drain current to flow through the RSF to the column output bus.

Abstract: A drive unit for a charge coupled device, which includes a plurality of transfer electrodes arranged to intersect a transfer direction of information charge, and stores and transfers information electric charge using potential wells formed in a semiconductor substrate by voltages applied to the transfer electrodes. As at least one of the transfer electrodes is used as a selected transfer electrode, the drive unit causes the at least one transfer electrode to undergo a cycle of switching from an ON state to an OFF state a number of times continuously to transfer the information electric charge.

Abstract: There is provided a solid-state image pickup device including: a pixel array portion which includes a plurality of unit pixels each having a photoelectric conversion element and an output transistor for outputting a signal according to charge obtained by photoelectric conversion of the photoelectric conversion element; a comparing portion which compares the signal output from each of the unit pixels with a ramp-shaped reference signal; a measuring portion which starts an operation in synchronization with the supply of the reference signal to the comparing portion, performs the operation until the comparison output of the comparing portion is inverted, and measures a time until the comparison of the comparing portion is finished; and a detecting portion which detects a predetermined image pickup condition and fixes the comparison output of the comparing portion to a state before the comparison starts when the image pickup condition is detected.

Abstract: A multiport memory cell (200, 300, 600) includes a first word line (WL1) coupled to a gate electrode of a first transistor (201, 301, 601). A second word line (WL2) is coupled to a gate electrode of a second transistor (202, 302, 602). Importantly, the memory cell (200, 300, 600) includes a conductive path (215, 315) between an electrically floating body (426) of the first transistor (201) and an electrically floating body (426) of the second transistor (202). The first word line (WL1) may overlie a first portion of a common body (426) and the second word line (WL2) may overlie a second portion of the common body (426). The common body (426) may be positioned vertically between a buried oxide layer (427) and a gate dielectric layer (430) and laterally between first and second source/drain regions (401, 407) formed in a semiconductor layer (425).

Abstract: The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With such an exposure mask, various light exposures can be more accurately controlled, which enables a resist to be processed into a more accurate shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps.

Abstract: A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.

Abstract: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D? of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1?(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region.

Abstract: Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the gate electrode via the gate insulating film; a semiconductor layer having the first conductivity type, being adjacent to the base layer, and facing the gate electrode via the gate insulating film without contacting the source layer; and a contact layer having the second conductivity type, contacting the source layer and base layer, having a top plane continuing with the top plane of the source layer, and having two or more peaks in an impurity concentration value profile in a depth direction from the top plane thereof, the peaks being positioned shallower than a formed depth of the source layer.

Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

Abstract: A semiconductor device includes a metal oxide semiconductor (MOS) transistor including two source/drain regions located at a surface layer side of the semiconductor substrate, a stress-inducing film formed so as to cover the source/drain region of the MOS transistor, the stress-inducing film applying stress to a channel region formed between the source/drain regions and having an opening corresponding to an electrical connection region of the source/drain regions, the opening having a first dimension with respect to a propagation direction of a charge carrier moving within the channel region of the MOS transistor and a second dimension with respect to a direction perpendicular to the propagation direction of the MOS transistor, the first dimension being larger than the second dimension.

Abstract: A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region of the second conductivity type. The first and second impurity regions can be independently formed to affect multiple parameters of the pixel sensor cell.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor layout structure is described. The CMOS image sensor layout structure includes a substrate, a plurality of light sensing devices, a plurality of transistors and a plurality of color-filtering film layers. The substrate has a pixel array region comprising a plurality of pixels. Each pixel has a light sensing region and an active device region. The pixels are isolated from one another by isolation structures and the light sensing regions have different sizes. The light sensing devices are defined separately within the respective light sensing regions. The transistors are disposed within the respective active device region. The color-filtering film layers are disposed separately above the pixels to form a color-filtering array.

Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.

Abstract: A pixel cell and imager device, and method of forming the same, where the pixel cell has a plurality of metallization and via layers formed over a photosensitive region. The metallization and via layers form a step-like light tunnel structure that augments the photosensitive region's ability to capture light impinging on the photosensitive region.

Abstract: A semiconductor imaging device includes a photodetection region formed of a diffusion region of a first conductivity type formed in an active region of a silicon substrate at a first side of a gate electrode such that a top part thereof is separated from a surface of the silicon substrate and such that an inner edge part invades underneath a channel region right underneath the gate electrode, a shielding layer formed of a second conductivity type at a surface of the silicon substrate at the first side of the gate electrode such that an inner edge part thereof is aligned with a sidewall surface of the gate electrode at the first side, a floating diffusion region formed in the active region at a second side of the gate electrode, and a channel region formed right underneath said gate electrode, wherein the channel region includes a first channel region part formed adjacent to the shielding layer and a second channel region part formed adjacent to the floating diffusion region, wherein the second channel region

Abstract: Provided is a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. In an image sensor including an array of pixels, each pixel includes: a standard photo-sensing and charge storage region formed in a first region under a surface portion of a substrate and collecting photo-generated carriers; a second charge storage region formed adjacent to the surface portion of the substrate and separated from the standard photo-sensing and charge storage region; and a potential barrier formed between the first region and a second region underneath the first region and diverting the photo-generated carriers from the second region to the second charge storage region.

Abstract: In a CMOS image sensor and method of fabricating the same, the CMOS image sensor is comprised of a pixel array generating image signals and a peripheral circuit processing the image signals. In the method, a substrate is provided having a pixel region and a peripheral circuit region. A photo-receiving element and at least one transistor are formed on the pixel region of the substrate and a transistor is formed on the peripheral circuit region of the substrate. A silicide barrier pattern is formed to cover a region where the photo-receiving element is formed. A silicide layer is formed on a predetermined region of the substrate. An interlevel insulation film is formed on the silicide barrier layer. At least one contact hole penetrating the interlevel insulation film is formed, the at least one contact hole exposing a predetermined region of the silicide layer.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes a photodiode region and a transistor region that have a first concentration and are formed on an active region of a first conductive type semiconductor substrate. Additionally, the CMOS image sensor includes a second conductive-type doping region that has a first depth and a second concentration, formed in the photodiode region and having a plurality of parallel, spaced apart portions (or bars) therein; and a high concentration first conductive-type doping region formed in the photodiode region having a second depth shallower than the first depth and a third concentration higher than the second concentration.

Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Abstract: In a magnetic memory 1, a magneto-resistivity effect element 4 is disposed adjacently to a wire 5 for producing a writing magnetic field and further a ferromagnetic body 20 is disposed so as to cover at least part of the wire 5 and consequently orient the state X of magnetization of this ferromagnetic body 20 in one direction. According to this invention, it is made possible to homogenize the magnetic property during the course of writing and implement the writing work efficiently.