Abstract: Disclosed are an isolation structure and a method for forming the same. The present isolation structure includes a substrate having a first semiconductor layer having a first lattice parameter, a second semiconductor layer having a second lattice parameter larger than the first lattice parameter, and a strained semiconductor layer; a well in the substrate; a plurality of isolation layers in the strained semiconductor layer and the second semiconductor layer, defining an active region; and a plurality of punch stop layers under the isolation layers.

Abstract: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.

Abstract: In a semiconductor device having a plurality of fuses and a method of fabricating the same, the semiconductor device comprises an inter-layer dielectric layer on a semiconductor substrate; a plurality of fuses on the inter-layer dielectric layer, an inter-metallic dielectric layer on the plurality of fuses and the inter-layer dielectric layer, a passivation layer on the inter-metallic dielectric layer, fuse windows exposing portions of a top surface and sidewall surfaces of the plurality of fuses, and a fuse barrier pattern between adjacent ones of the plurality of the fuses.

Abstract: The present invention provides a fuse structure. The fuse structure comprises a substrate, a plurality of conductive layers, a plurality of dielectric layers and a plurality of conductive plugs. The novel fuse structure includes a plurality of fuse units, and a new layout of the fuse units to increase the pitch between the fuse units, preventing the fuse structure from failing when misalignment of the laser beam and thermal scattering of the laser beam damage the second layer of the fuse structure in the laser blow process, thus increasing reliability and yield.

Abstract: A semiconductor device includes a semiconductor substrate including an active element or an integrated circuit and a plurality of connection electrodes to be electrically connected to the integrated circuit; a first resin layer formed on a surface of the semiconductor substrate on which the connection electrodes are formed in such a manner avoiding the connection electrodes; a connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes; a Cu wiring layer connected at one end thereof to the connection wiring layer and formed on the surface of the first resin layer; a passive element composed of the connection wiring layer and the Cu wiring layer; a second resin layer for covering a surface of the Cu wiring layer; and an external terminal electrically connected to some of the plurality of connection electrodes and formed such that a portion of the second resin layer protrudes from the second resin layer.

Abstract: One embodiment of an integrated circuit includes a substrate and a SiWNi thin film resistor formed on the substrate.

Abstract: A first (e.g. replaceable or disposable) dielectric spacer formed on a sidewall of a dummy emitter mandrel is removed after a raised extrinsic base layer and covering dielectric layer are formed. Thereafter, a second dielectric spacer is formed within the opening that results. As a result, the second dielectric spacer, which is not subjected to RIE processing, provides a desired level of isolation and tighter emitter final critical dimension than that which could be achieved through the technique described in the prior art. In a particular embodiment, an additional layer of silicon nitride is disposed over a passivation oxide layer as a sacrificial layer which protects the passivation oxide layer from being reduced in thickness and/or being undercut during the RIE process and one or more cleaning processes conducted after the RIE process.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: A vertical silicon controlled rectifier (SCR) that directs an electro-static discharge (ESD) current directly to ground from the input/output pad. The vertical SCR is includes a vertical NPN and a vertical PNP that creates a very good SCR exhibiting very low ohmic on-resistance. The vertical SCR provides a low on-resistance and fast turn on, and can be adjusted to alter the trigger voltage value, holding voltage and how it is triggered. It can be optimized to trigger under ESD events and discharge the ESD current effectively to ground.

Abstract: The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer. This method includes forming a step of defined height around the periphery of the wafer, with the step having a mean thickness that is less than that of the wafer; and selectively implanting atomic species through a face of the wafer but not through the step to form an implanted zone at a defined implant depth with the film being defined between the face of the wafer and the implanted zone. The implantation of atomic species into the step can be prevented by forming a protective layer at least over the step or by masking the step. The invention also relates to a wafer obtainable by the method.

Abstract: A semiconductor device includes a substrate having a bottom metal line formed therein; a nitride layer and an oxide layer having a trench and a via hole, the via hole exposing the bottom metal line; a barrier metal layer formed inside the trench and the via hole; a seed layer formed on the barrier metal layer inside the trench and the via hole; and a copper line formed on the seed layer inside the trench and the via hole.

Abstract: A vapor phase deposition apparatus includes a chamber, a support table disposed in the chamber and adapted to support a substrate in the chamber, a first passage connected to the chamber and adapted to supply gas to the chamber to form a film on the substrate, and a second passage connected to the chamber and adapted to discharge the gas from the chamber. The support table includes a first depressed portion and a second depressed portion formed in a bottom part of the first depressed portion, a bottom face of the second depressed portion for supporting the substrate.

Abstract: A composition of matter and a structure fabricated using the composition. The composition comprising: a resin; polymeric nano-particles dispersed in the resin, each of the polymeric nano-particle comprising a multi-arm core polymer and pendent polymers attached to the multi-arm core polymer, the multi-arm core polymer immiscible with the resin and the pendent polymers miscible with the resin; and a solvent, the solvent volatile at a first temperature, the resin cross-linkable at a second temperature, the polymeric nano-particle decomposable at a third temperature, the third temperature higher than the second temperature, the second temperature higher than the first temperature, wherein a thickness of a layer of the composition shrinks by less than about 3.5% between heating the layer from the second temperature to the third temperature.

Abstract: A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of the first side or the second side of the semiconductor device along a second direction. The chip level contact portions extend along the first direction. Ends of the chip level contact portions are aligned along a line extending along the second direction. This leadframe can be included with a semiconductor chip in a packaged integrated circuit.

Abstract: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

Abstract: The present invention relates to a method for making a package structure having recession portion on the surface thereof. The method comprises: (a) providing a lead frame having a plurality of package units, each package unit having a plurality of leads and a die paddle; (b) providing an upper mold and a lower mold for clamping the lead frame, wherein the upper mold and the protruding block of the lower mold clamp the first portions of the leads so as to prevent molding compound bleeding to the upper surfaces of the first portions during mold filling operation, for improving the product yield; (c) injecting a molding compound between the upper mold and the lower mold, and forming a plurality of accommodation spaces; (d) attaching a plurality of chips onto the die paddles; (e) electrically connecting the chips to the first portions of the leads; (f) sealing the accommodation spaces; and (g) segregating the package units.

Abstract: Disclosed herein are a metallic laminate, including (i) a metal layer and (ii) a polyimide resin layer having a coefficient of thermal expansion of 19 ppm/° C. or less and a glass transition temperature of 350° C. or more, laminated on the metal layer, and a method of manufacturing the same. According to this invention, the metallic laminate has a good external appearance, having no foam on the polyimide resin layer.

Abstract: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.

Abstract: To provide a TAB tape carrier that can provide improved adhesion of a conductive pattern to an insulating base layer, while strengthening a connection between gold terminals of a semiconductor device and connection terminals covered with a tin plating layer, and can prevent the conductive pattern from sinking into the insulating base layer. In the TAB tape carrier, an insulating base layer is formed by laminating a thermoplastic polyimide resin layer of 4 ?m thick or less on a thermosetting polyimide resin layer, and a conductive pattern having inner leads covered with a tin plating layer is formed on a surface of the thermoplastic polyimide resin layer. In this TAB tape carrier, even when the gold terminals of the semiconductor device are press-bonded to the inner leads covered with the tin plating layer at high temperatures and pressures, the conductive pattern can be prevented from sinking into the insulating base layer.

Abstract: To provide a chip on flex (COF) tape having an improved precision of cumulative pitches while retaining bending properties. [Means to Solve the Problems] A chip on flex (COF) tape having a wiring pattern comprising a plurality of wirings arranged in parallel formed on the surface of a flexible insulating film, wherein a dimension retention pattern is formed on said surface of said flexible insulating film and/or the surface of the side of the film opposite thereto so as to cross the width direction of at least two of said wirings arranged in parallel in the vicinity of the connecting portion of said wiring pattern with a semiconductor chip and/or the connecting portion with an external device.

Abstract: In some embodiments a semiconductor device is described that includes, on a single die, both a functional circuit and a power-gating circuit. The power-gating circuit may be used to control the power delivered to core circuit elements on the semiconductor device. The power may be provided to and possibly from the power-gating circuit using underutilized die connection elements. Other embodiments are otherwise disclosed herein.

Abstract: A method, apparatus, and system with a subassembly for simple integration of high power integrated electronics, the subassembly including an integrated circuit package, an integrated circuit package cooling device and a printed circuit board with coupled power delivery components.

Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

Abstract: A semiconductor wafer is provided with a wiring structure, and semiconductor chip positions arranged in rows and columns. The semiconductor wafer has at least one coating (6) as a self-supporting dimensionally stable substrate layer (4), and/or as a wiring structure composed of conductive, high-temperature-resistant material. The coating material (6) of the substrate layer (4) and/or of the wiring structure has a ternary carbide and/or a ternary nitride and/or carbon.

Abstract: A balance filter packaging chip having a balun mounted therein and a manufacturing method thereof are provided. The balance filter packaging chip includes a device substrate; a balance filter mounted on the device substrate; a bonding layer stacked on a certain area of the device substrate; a packaging substrate having a cavity formed over the balance filter, and combined with the device substrate by the bonding layer; a balun located on a certain area over the packaging substrate; and an insulator layer for passivating the balun. Accordingly, the present invention can reduce an element size and simplify a manufacturing process.

Abstract: A semiconductor stack block contains either stacked semiconductor chip size semiconductor devices or semiconductor devices with semiconductor chips in a plastic housing composition, the semiconductor chips and the plastic housing composition having a coplanar area. Arranged on the active top side of the semiconductor chips and the plastic housing composition is an areal wiring structure, by which device interconnects are led to an individual edge of the semiconductor devices. The edges with the ends of the device interconnects form the underside of the semiconductor stack block, external contact areas being arranged on the ends of the device interconnects, the external contact areas carrying external contacts.

Abstract: The invention relates to a package, e.g. a blister package, comprising two spaced apart first and second walls formed and joined to each other to define a cavity between them, said walls having peripheral edges and being sealed together at a peripheral joint essentially along the edges wherein a portion of said peripheral joint comprises at least two conductive surfaces and an electrically weakable adhesive. The invention further relates to an apparatus for supplying electrical power to the package.

Abstract: The productivity of an IC card is to be improved. In a memory card of the type in which a memory body having a wiring substrate and a semiconductor chip mounted on a main surface of the wiring substrate is held so as to be sandwiched in between a first case and a second case, a planar outline of the memory body is smaller than half of a planar outline of the memory card. The memory body is disposed so as to be positioned closer to a first end side as one short side of the memory card with respect to a midline between the first end side and a second end side as an opposite short side of the memory card positioned on the side opposite to the first end side. The other area than the memory body-disposed area in the first and the second case is used as another functional area.

Abstract: The present invention relates to a method and apparatus for producing a chip arrangement. In one embodiment, the method includes providing a first chip having an electrically operable structure, of providing at least one through-via through the first chip, and of arranging at least one bond wire through the through-via in the first chip.

Abstract: In a multi-chip semiconductor package, a rectangular wiring die has a wiring pattern layer, and respective four sides of the wiring die is dimensionally identical to those of a first rectangular semiconductor die. The wiring die is mounted on the first semiconductor die so that the respective sides of the wiring die coincide with those of the first semiconductor die. A second rectangular semiconductor die has respective four sides dimensionally smaller than those of the wiring die, and the second semiconductor die is mounted on the wiring die so that the second semiconductor die occupies an inner area portion completely included in an area which are defined by the sides of said wiring die, the first and second semiconductor dies are electronically communicated with each other through the wiring pattern layer of the wiring die.

Abstract: A semiconductor chip 11 comprising an element formation layer 36 which is formed on a first main surface 35A of a semiconductor substrate 35 and has a semiconductor element, through electrodes 15, 16 which are electrically connected to the semiconductor element and extend through the semiconductor chip 11, and a patch antenna 33 formed on the side of a second main surface 35B of the semiconductor substrate 35 are disposed, and the patch antenna 33 is electrically connected to the through electrode 15 electrically connected to a line for power feeding of the semiconductor element.

Abstract: A method for fabricating a copper-based circuit module is described. The module is built on a copper sheet and has isolated feedthroughs fabricated using a glass frit. High density interconnection circuits are built on the copper sheet, including wells for accepting bumped devices such as integrated circuit chips. The modules can be stacked to form electronic subsystems, with cooling channels optionally provided between pairs of modules.

Abstract: One embodiment of a microelectronic component system includes a base adapted for supporting a microelectronic component, a membrane sealed to the base, and a glass lid built-up on the membrane and hermetically sealing the membrane.

Abstract: A semiconductor component comprises a substrate that includes wiring on a first surface. A chip is mounted on a second surface of the substrate by a die attach, the second surface opposite the first surface. A bond channel in the center of the substrate allows for electrical connection of contact pads on the wiring with bond pads arranged in a center row on the chip by wire loops. A housing made of a mold compound surrounds a backside of the chip and parts of the substrate adjacent to the wiring. The semiconductor component further comprises a rigid prepreg layer covering, as well as the wiring of the substrate and the prepreg layer being provided with openings. Each opening is arranged in such a manner that the contact pads are accessible, and solder balls are mounted on each of the contact pads through the openings.

Abstract: A package includes a thermal solution to thermal couple to a semiconductor device to remove heat generated by the semiconductor device, and a device to electrically isolate at least a portion of the thermal solution from the semiconductor device. The package also includes a biasing device to apply a voltage to a body of the semiconductor device.

Abstract: An LED package includes a substrate having an electrically conductive portion and an electrically non-conductive portion composed of an oxide of the conductive portion; an LED mounted on the conductive portion and electrically connected to the conductive portion; a first electrode disposed on the non-conductive portion and electrically connected to the LED by a wire; and a second electrode disposed on the substrate and electrically connected to the LED.

Abstract: A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a semiconductor structure. The system includes a container to hold at least one semiconductor chip having surfaces to be in contact with a fluid. The system also includes a transducer and a heat exchanger disposed within the container and operably positioned with respect to each other to perform a thermoacoustic cooling process. In this system, the transducer is adapted to generate sound waves within the fluid such that compression and decompression of the fluid provides a temperature gradient across the semiconductor chip to transfer heat from the semiconductor chip to the heat exchanger, and the heat exchanger is adapted to remove heat from the fluid in the container. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: A semiconductor device for radio frequencies of more than 10 GHz having a semiconductor chip is disclosed. In one embodiment, the semiconductor chip, on its active top side, having a radio-frequency region and a low-frequency region and/or a region which is supplied with DC voltage. In one embodiment, the low-frequency region and/or the region which is supplied with DC voltage of the semiconductor chip is directly embedded in a plastic housing composition, the plastic housing composition is arranged such that it is spaced apart from the radio-frequency region on the active top side of the semiconductor chip.

Abstract: The present invention is directed to improve high frequency characteristics by reducing inductance of a source. In an HEMT assembled in a power amplifier device, each of a drain electrode, a source electrode, and a gate electrode is constructed by a base portion and a plurality of fingers projected in a comb-teeth shape from the base portion, and the fingers of the electrodes mesh with each other. In the source electrode, a width of the fingers positioned at both ends of the plurality of fingers is wider than a width of each of the fingers positioned between both ends. The width of each of the fingers positioned at both ends is a width equal to or larger than a sum of the widths of the plurality of fingers positioned between both ends, and the width of the base portion is wider than that of each of the fingers positioned at both ends. An electrode pad provided for the source base portion and an external electrode terminal are connected to each other via a conductive wire.

Abstract: Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are intelligently arranged to reduce the loop inductance of corresponding signal and power supply bond wires.

Abstract: A wiring substrate includes a substrate, a first film, and a second film formed between the substrate and the first film, and an empty space is formed between at least a part of the second film and the substrate.

Abstract: A method for fabricating a bonding pad 45 includes disposing a droplet L including a liquid containing a conductive material on a substrate P by a droplet ejection method and solidifying the disposed droplet L to forms the pad. The bonding pad 45 formed has a cylindrical shape and includes a concave part 47.

Abstract: One embodiment of an integrated circuit includes a substrate, an electrical device positioned above the substrate, and a bond bad positioned above and aligned along a vertical axis with the electrical device such that the electrical device is positioned between the substrate and the bond pad.

Abstract: A semiconductor device comprises at the wafer level one or more ferrite structures adapted to dampen high frequency noise potentially apparent at signal lines and termination points within the semiconductor device. Related methods of forming said ferrite structures are also disclosed.

Abstract: A semiconductor device including: a semiconductor chip having an electrode; a plurality of resin protrusions formed on a surface of the semiconductor chip on which the electrode is formed, heights of the resin protrusions increasing as a distance from a center of the surface of the semiconductor chip increases; and an interconnect electrically connected to the electrode and formed over one of the resin protrusions.

Abstract: A construction for attaching an optical fiber to an electro-optic chip is described. The construction includes support for the optical fiber, optionally provided by an aperture in a supporting copper sheet. High density interconnection circuits are fabricated on the copper sheet. Pillar-in-well connections are used between the electro-optic chip and the interconnection circuits, with electrical connections for signals and power, and thermal connections at increased density for cooling the chip. An electronic subsystem employing stacked modules is described, with optical ports at each of the modules.

Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.

Abstract: A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is formed on the interconnect layer 14. Chip-connecting electrodes 17, external electrode pads 18 and the resin stopper patterns 19 are formed in the insulating resin layer 16. The chip-connecting electrodes 17 are provided in the mounting region D1. The external electrode pads 18 are provided outside the mounting region D1. The resin stopper patterns 19 are provided between the mounting region D1 and the external electrode pads 18.

Abstract: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.