Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

Abstract: An electronic component and method of production thereof is presented. The electronic component includes a first insulation layer, an upper metal layer on the first insulation layer, an electrically conductive structure integrated into the first insulation layer and formed as a capacitor with a first metal strip sequence, and a second metal strip sequence. Each of the first and second sequences are arranged congruently one above another and are connected to one another by via connections. The second sequence is arranged on both sides of the first sequence at identical lateral distances. The metal strips of the first and second sequences are arranged at the same level and are connected to different electrical potentials. The electrically conductive structure mechanically stabilizes the insulation layer under the action of mechanical force such as bonding of the upper metal layer or mounting of the electronic component.

Abstract: A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second control voltage sources respectively, the non-linear resistances forming a voltage divider network which sets the operating voltage of the floating gate.

Abstract: The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Abstract: Apparatus and methods are provided. Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a memory device, and second conductive straps are respectively connected only to second portions of second word lines of the memory device, where each first word line is adjacent at least one second word line. One or more contacts can be used to connect a conductive strap to its respective word line.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes.

Abstract: In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.

Abstract: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation regions, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

Abstract: A semiconductor device which, even when a vertical transistor is adopted, is able to prevent a product yield from decreasing and performance from deteriorating, and at the same time, to achieve high-density integration of chips and high performance. The semiconductor device includes: a semiconductor substrate; a tower-like gate pillar formed on the semiconductor substrate via an insulation layer and including a channel region formed so as to be positioned between impurity diffusion regions in a vertically extended direction with respect to a principal side of the substrate; a gate insulation film formed on an outer surface of the gate pillar; and a gate electrode film including multiple conductive layers formed on an outer surface of the gate insulation film.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

Abstract: A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the exposed regions of the substrate. During formation, each contact region has a first growth rate in a first direction and a second growth rate in a second direction. While each contact region is being selectively formed on the respective exposed region, the contact region is heated to increase the first growth rate of the contact region in the first direction relative to the second growth rate of the contact region in the second direction. The first growth rate may be a vertical growth rate and the second growth rate may be a lateral growth rate. The contact may be heated by applying electromagnetic radiation to an upper surface of the substrate and not applying the radiation to the vertical portions of the contact region to thereby increase the vertical growth rate relative to the lateral growth rate.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: Unit cells of a static random access memory (SRAM) are provided including an integrated circuit substrate and first and second active regions. The first active region is provided on the integrated circuit substrate and has a first portion and a second portion. The second portion is shorter than the first portion. The first portion has a first end and a second end and the second portion extends out from the first end of the first portion. The second active region is provided on the integrated circuit substrate. The second active region has a third portion and a fourth portion. The fourth portion is shorter than the third portion. The third portion is remote from the first portion of the first active region and has a first end and a second end. The fourth portion extends out from the second end of the third portion towards the first portion of the first active region and is remote from the second portion of the first active region. Methods of forming SRAM cells are also described.

Abstract: An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

Abstract: One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2O3 film comprises: depositing an In film using a PVD process, typically with a power in the range of 200 to 300 watts; forming a film including In overlying a substrate material; simultaneously (with the formation of the In-including film) heating the substrate material, typically the substrate is heated to a temperature in the range of 20 to 200 degrees C.; following the formation of the In-including film, post-annealing, typically in an O2 atmosphere; and, in response to the post-annealing: forming an In2O3 film; and, controlling the resistivity in the In2O3 film. For example, the resistivity can be controlled in the range of 260 to 800 ohm-cm.

Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

Abstract: A contact sensor chip package includes a substrate, a contact sensor chip, a ground member and an encapsulation. The contact sensor chip is disposed on the substrate, and the contact sensor chip has a sensor area. The ground member is disposed on the ground pad of the substrate, and the ground member is electrically connected to the ground pad. The encapsulation covers the contact sensor chip and the ground member, wherein the sensor area of the contact sensor chip and a portion of the ground member are exposed out of the encapsulation.

Abstract: The flash cell includes a silicon substrate; a floating gate formed on a predetermined area of the silicon substrate; a control gate formed on the floating gate and the silicon substrate; a piezoelectric layer formed on the control gate; and an upper electrode formed on the piezoelectric layer. The flash cell brings the control gate in contact with the floating gate, instead of electrically removing electrons contained in the floating gate, resulting in a charge equilibrium state. Therefore, the flash cell completely solves the over-erasing problem. If a voltage signal is applied to the flash cell, the flash cell uses the displacement of piezoelectric/electrostrictive materials. The displacement occurs according to the received voltage, such that the flash cell implements at high speed compared to conventional electric erasing methods.

Abstract: The present invention is aimed at enabling a spin-transfer magnetization switching in the random access magnetic memory by reducing a switching current density in the spin-transfer magnetization switching to an order smaller than 10 MA/cm2 and without causing breakdowns neither in the memory element which uses a TMR film nor in the element selection FET. The memory layer in the magnetoresistance effect element comprises a magnetic film having a value of saturation magnetization in a range from 400 kA/m to 800 kA/m. The memory layer comprises a magnetic film which contains one or more magnetic elements selected from the group of, for example, cobalt, iron and nickel, and which further contains a non-magnetic element. The non-magnetic element is contained at a ratio of, for example, 5 at % or more and less than 50 at %. A memory layer 12 in the memory cell has a dimension less than 200 nm?.

Abstract: An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

Abstract: A ferromagnetic thin-film based array of directed magnetic field generating structures having a plurality of toroidally shaped layer stacks each with a pair of ferromagnetic material layers separated by an intermediate layer of nonmagnetic material. Electrical connections are made to opposite sides thereof. A serpentine first side electrical conductor is folded back so as to have parallel branches and together zigzag to cross over each stack on one side thereof. A serpentine second side electrical conductor, also folded back so as to have parallel branches, can be further provided with these branches together zigzagging to cross each stack on an opposite side thereof. These first and second side electrical conductors can be electrically joined to form an array electrical conductor.

Abstract: This invention proposes a stable magnetic memory device that is equipped with a storage cell having a MTJ, wherein variation in the coercive force (Hc) of a ferromagnetic free layer is suppressed, and a switching characteristic of a bit of a MRAM is improved, and there is no write error. Namely in a magnetic memory device equipped with a first wiring, a second wiring (bit line) intersecting with the first wiring, and a storage cell for writing/reading information of a magnetic spin at an intersecting area of the first wiring and the second wiring, a partial sidewall portion electrically connecting to the storage cell of the second wiring (bit line) has a forward tapered form having a contact angle relative to a top surface of the storage cell being 45 degrees or more.

Abstract: A ultrathin magnetoelectric transducer and its manufacturing method are provided which enable the quality of mounting to be inspected nondestructively, and can reduce a footprint. The magnetoelectric transducer has a substrate composed of a nonmagnetic substrate, and includes bottom surface connecting electrodes whose leads have a first thickness, and side electrodes which are exposed by dicing and have the first thickness. A more sensitive Hall element has a high-permeability magnetic substrate as the substrate, and includes the bottom surface connecting electrodes whose leads have the first thickness, and the side electrodes exposed by the dicing and having the first thickness. The bottom surface connecting electrodes of the leads with the first thickness are formed across the internal electrodes of adjacent magnetoelectric transducers with maintaining the first thickness. The side electrodes with the first thickness are formed by cutting the center between the adjacent magnetoelectric transducers.

Abstract: An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material.

Abstract: A semiconductor component, such as a humidity sensor, which has a semiconductor substrate, such as, for example, made of silicon, a first electrode and a second electrode and at least one first layer that is accessible for a medium acting from the outside on the semiconductor component, the first layer being arranged at least partially between the first and the second electrode. To reduce the costs for producing the semiconductor component the first layer has pores into which the medium reaches at least partially.

Abstract: An organic Schottky diode includes a polycrystalline organic semiconductor layer with a rectifying contact on one side of the layer. An amorphous doped semiconductor layer is placed on the other side of the polycrystalline organic semiconductor layer, and it acts as a buffer between the semiconductor layer and an ohmic contact layer.

Abstract: A fuse structure for memory cell repair in a RAM device. The fuse structure includes a substrate, a fuse layer over an isolation region on the substrate, a charge protection circuit electrically connected to one side of the fuse layer, and two conductive layers overlying the substrate and electrically connected to the charge protection circuit and the other side of the fuse layer respectively.

Abstract: A semiconductor component, which functions according to the principle of charge carrier compensation, has incompletely ionized dopants that are additionally provided in a semiconductor body of the semiconductor component. When a reverse voltage is applied, the degree of compensation changes as a function of time and the breakdown voltage of the semiconductor component increases in a manner governed by the degree of compensation. The invention furthermore relates to a circuit configuration and to a method for doping a compensation layer according to the invention.

Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.

Abstract: The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible to breaking. The unique system also offers an improved structure for handling thinned wafers and reduces the number of processing steps. This results in improved yields and improved process efficiency.

Abstract: A semiconductor substrate is partitioned along scribing lines so as to form a plurality of IC regions encompassed by seal rings, wherein a passivation opening is formed in the scribing line in which a monitoring element is formed within a monitoring element region, which is encompassed by secondary seal rings, which are constituted by metal layers, oxidation layers and via holes. The secondary seal rings are formed to encompass the periphery of the monitoring element, which can thus precisely monitor characteristics of integrated circuits because it is possible to prevent water and impurities from infiltrating into the monitoring element region which is thus stabilized in characteristics.

Abstract: The invention provides highly reliable semiconductor devices, methods for manufacturing the same, circuit substrates and electronic devices. A semiconductor substrate is provided that includes: an integrated circuit and a pad defining a through hole electrically connected to the integrated circuit. A convex section is formed at a first surface where the pad is formed in a region that overlaps the through hole in the semiconductor substrate. A dielectric layer is formed on an inner surface of the convex section. An electrical connection section is provided having a conductive section disposed inside the dielectric layer and a wiring section disposed on the first surface to be electrically connected to the conductive section. An end surface of the conductive section is exposed through a second surface of the semiconductor substrate on the opposite side of the first surface.

Abstract: A lead frame (1) has a first portion (2) adapted to have a semiconductor device (10) mounted thereon and a second portion (3) including a main member (5), a number of first contact members (6) and a number of second contact members (7). The first and second contact members (6, 7) depend from the main member (5). The second portion (3) at least partially surrounds the first portion (6). The first contact members (6) extend form the main member (5) in a direction away for the first portion (2) and the second contact members (7) extend from the main member (5) in a direction towards the first portion (2).

Abstract: A leadframe for a surface-mountable radiation-emitting component, preferably a light-emitting diode component, having at least one chip connection region and at least one external connection strip. The leadframe is formed in planar fashion and a deformation element, preferably a spring element, is arranged between the chip connection region and the external connection strip. The deformation element enables an elastic or plastic deformation of the leadframe in the plane of the leadframe. A housing, a surface-mountable component and an arrangement having a plurality of such components are furthermore specified.

Abstract: Packaging assembly method and systems include the use of a plastic substrate and one or more compliant fasteners, which can be connected to the plastic substrate, such that the compliant fastener provides an electrical connection to one or more electrical components. A plastic leadframe can therefore be formed, which is based upon the plastic substrate and the compliant fastener for attachment to other electrical components. The plastic substrate itself can function as a plastic trace or plastic substrate trace, and can be formed from plastic material such as thermoplastic or a thermoset material. The compliant fastener itself can be pushed into the plastic substrate at a connection point thereof for attachment of the compliant fastener to the plastic substrate. The connection point can be formed in the plastic substrate as one or more round holes, slots, rectangular holes or complex shapes. An interface is therefore for med between the plastic trace and the compliant fastener.

Abstract: A plurality of semiconductor chips (14) each having a first main surface (14b) formed with electrode pads (21) and a second main surface (14c) opposite to the first main surface are respectively mounted on a chip mounting surface (12a) larger in area than the second main surface, of a wafer-shaped mounting substrate (12) at equal intervals so as to extend along first and second trenches (18a, 18b) defined in the chip mounting surface with these trenches as target lines. Thereafter, solder balls (25) electrically connected to the electrode pads of the semiconductor chips are disposed on their corresponding wiring patterns 34 that extend from above first regions (100) located above the semiconductor chips, of a surface region of an encapsulating layer (32) covering the semiconductor chips to above second regions (200) that surround the first regions. Afterwards, the encapsulating layer and the mounting substrate are cut and thereby fractionized into semiconductor devices each having a fan-out structure.

Abstract: A leadless semiconductor package mainly comprises a leadless lead-frame, a chip, a silver paste and a plurality of electrically conductive wires. The lead frame includes a chip paddle and a plurality of leads surrounding the chip paddle wherein the chip paddle has a cavity serving as a chip disposal area and a grounding area surrounding the cavity, and at least there is one recession formed on the grounding area. Besides, the chip is disposed in the cavity so that the back surface of the chip faces the chip paddle and attached onto the chip paddle via the silver paste. Moreover, the chip is electrically connected to the leads. As mentioned above, the grounding area has at least one recession formed therein, so the contact area of the leadless lead-frame with the encapsulation will be increased to enhance the attachment of the encapsulation to the leadless lead-frame.

Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.

Abstract: A memory card structure comprising a substrate, a plurality of memory chips, some molding compound and an ultra-thin plastic shell is provided. To fabricate the memory card, a substrate having a first surface and a second surface is provided. The first surface has a plurality of outer contacts and the second surface has a cavity and a plurality of inner contacts around the cavity. The outer contacts and the inner contacts are electrically connected to each other. The memory chips are stacked up in the same area inside the cavity. Furthermore, the memory chips are electrically connected to the inner contacts. Then, the memory chips and the inner contacts are encapsulated. Thereafter, the ultra-thin plastic shell is placed over the second surface and attached to the substrate. That portion of the ultra-thin plastic shell covering the memory chips has a thickness of about 0.1˜0.4 mm.

Abstract: A memory card comprising a leadframe having a die pad, and an insert having a plurality of contacts. Attached to the die pad is a semiconductor die which is electrically connected to the contacts of the insert. A body covers the die pad and the semiconductor die and partially covers the insert such that the contacts are exposed in an exterior surface of the body.

Abstract: A semiconductor structure includes flip chips or other semiconductor devices that are mounted on printed circuit boards. The printed circuit boards are stacked to increase the circuit density of the semiconductor structure. The printed circuit boards include cavities or openings to accommodate the flip chips or semiconductor devices and thus reduce the overall size of the semiconductor structure. The flip chips or semiconductor devices from adjacent printed circuit boards may extend into the cavities or openings or simply occupy the cavities or openings from the same printed circuit board.

Abstract: A power array includes a plurality of FET power assemblies and each FET power assembly has at least one field effect transistor mounted to a ciruit board. The circuit boards are arranged atop each other. A power supply pin extends through the circuit boards and is connected to a power input of each field effect transistor. A power output of each FET power assembly is connected to a power output pin which extends through each of the circuit boards. A heat sink is mounted to the power array beneath the lowest FET power assembly and is thermally connected to the field effect transistors of each FET power assembly. A method of assembling a power array including a plurality of FET power assemblies with at least one field effect transistor.

Abstract: An intermediate chip for electrically connecting semiconductor chips includes: a substrate having a first side and a second side; a trans-substrate conductive plug which projects to the first side of the substrate; a post electrode which is displaced from the trans-substrate conductive plug in plan view on the second side of the substrate; and wiring which is disposed in or on the substrate for coupling the trans-substrate conductive plug and the post electrode.

Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

Abstract: A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the first conductive pattern of the flex circuit such that the integrated circuit chip packages are positioned upon respective ones of opposed top and bottom surfaces of the flex substrate. Alternatively, one of the integrated circuit chip packages may be positioned upon the top surface of the flex substrate and electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached in a non-conductive manner to the bottom surface of the flex substrate such that the conductive contacts of such integrated circuit chip package and the leads collectively define a composite footprint for the chip stack.

Abstract: A multi-chip circuit module on which semiconductor chips are loaded and which is provided with circuit patterns, input/output terminals or the like for interconnecting the semiconductor chips. A multi-layered wiring section (2) is formed by respective unit wiring layers (8) to (12) in such a manner that an upper unit wiring layer is layered on a surface-planarized subjacent unit wiring layer and connected to one another by inter-layer connection by a via-on-via structure. A semiconductor chip (6) mounted on this multi-layer wiring section (2) is polished along with the sealing resin layer (7) for reducing the thickness.