Abstract: A magnetic field measurement apparatus which reduces an interference magnetic field entering into a pick-up coil is provided. The magnetic field measurement apparatus includes a superconducting quantum interference device (SQUID) magnetometer having a pick-up coil for picking up a magnetic field generated from an examination object, a SQUID control unit for controlling the SQUID magnetometer, a magnetometer for picking up the interference magnetic field, a magnetometer control unit for controlling the magnetometer, a modulation circuit, a current converter, a current amount adjusting device, a coil which is positioned outside the pick-up coil and through which the current thus adjusted by the current amount adjusting device flows, a demodulation circuit, a low-pass filter (LPF) for extracting a low frequency element of the output voltage from the demodulation circuit, and a subtraction circuit for subtracting the output of the LPF from the output of the SQUID control unit.

Abstract: An expert system is included in a downhole processor designed to acquire and process NMR data downhole in real time. The downhole processor controls the acquisition of the NMR data based at least in part on instructions transmitted downhole from a surface location and at least in part on evaluation of downhole conditions by the expert system. The downhole conditions include drilling operation conditions (including motion sensors) as well as lithology and fluid content of the formation obtained from other MWD data. The wait time, number of echos, number of repetitions of an echo sequence, interecho time, bandwidth and shape of the tipping and refocusing pulses may be dynamically changed. Data processing is a combination of standard evaluation techniques. Selected data and diagnostics are transmitted uphole. The expert system may be implemented as a two stage neural net. The first stage does the formation evaluation and the second stage controls the NMR pulse sequence.

Abstract: A ferromagnetic lens in the presence of a DC magnetic field and a smaller AC magnetic field creates a localized minimum of the magnitude of the magnetic field vector of the combined magnetic field in a volume defined in free space away from the lens referred to as the focus volume. The localized minimum can be nonzero, and can create conditions for spin resonance in the focus volume. The focus volume defined in free space away from the lens can be very small, providing excellent resolution for magnetic resonance imaging, for example.

Abstract: The invention relates to an open magnetic resonance imaging (MRI) magnet system (1) for use in a medical imaging system. The open MRI magnet system has two main coil units which are accomodated, at some distance from each other, in a first housing (2) and in a second housing (3), respectively. Between the two housings, an imaging volume (6) is present wherein a patient to be examined is placed. A gradient coil unit (9, 10) facing the imaging volume is present near a side of each of the two housings. Functional connections of the gradient coil units (9, 10), such as electrical power supply lines (13, 14) and cooling channels (15, 16) are provided in a central passage (4, 5) which is present in each of the two housings. As a result, these functional connections do not reduce the space in the imaging volume available for the patient.

Abstract: Bi-planar coil assemblies are disclosed which have DSV's whose centers are offset by distances D from the origins of x,y,z-coordinate systems, where said origins of x,y,z-coordinate systems are coincident with the geometric centers of the coils. The distances D can be of the order of 10-20 centimeters or more. The bi-planar coil assemblies can be used in MRI applications to reduce the feeling of claustrophobia experienced by some subjects. The assemblies also can facilitate the imaging of various joints, including the wrist, elbow, ankle, or knee.

Abstract: A resonator system for generating a radio frequency (RF) magnetic field in a volume under investigation of a magnetic resonance (MR) arrangement, comprises a number N of individual resonators (2) which surround the volume under investigation and which are each disposed on a flat dielectric substrate (1) around a z-axis, wherein the individual resonators (2) have windows (8) through each of which one individual RF field is generated in the volume under investigation in single operation of the individual resonators (2) and, through cooperation among the individual resonators (2), a useful RF field (7) is generated in the volume under investigation, wherein a remote RF field (6) is asymptotically generated far outside of the resonator system, and the spatial distribution of the useful RF field (7) is substantially mirror-symmetrical relative to a first plane A which contains the z-axis, and that of the asymptotic remote RF field (6) is substantially mirror-symmetrical relative to a second plane B which contains

Abstract: A detuning circuit unit for antennas of a magnetic resonance apparatus has at least two identical detuning modules that are connected in a cascade circuit and can be simultaneously activated with a control signal of a control signal source, and a circuit component to terminate a last of the detuning modules of the cascade circuit. An advantage is in the modular and cascadable use of the identical detuning modules, such that PIN diodes used as radio frequency switches are serially fed current in a first operating state and are supplied in parallel with a blocking voltage in a second operating state.

Abstract: A well logging tool and method are disclosed comprising a conductive mandrel, an antenna array disposed around the conductive mandrel, wherein the antenna array comprises a plurality of antennas disposed on insulating supports and at least one contact spacer, the at least one contact spacer having at least one conductor channel having a contact assembly disposed therein, a sleeve disposed over the antenna array, wherein the sleeve includes at least one electrode assembly, the at least one electrode and the contact assembly adapted to provide a radially conductive path from an exterior of the well logging tool to the conductive mandrel and wherein the electrode assembly comprises a first conductor exposed to the exterior of the well logging tool and at least one second conductor conductively connected to the first conductor and exposed to an inner surface of the sleeve, wherein at least one of the first conductor or the second conductor being in sealed contact with the sleeve to prevent the passage of fluid th

Abstract: A method and a device for determining the state of a vehicle battery in which the battery voltage is measured and information regarding the state of the vehicle battery is derived from the measured battery voltage by means of an integration procedure. A variable weighting factor is taken into account in the integration procedure.

Abstract: A patch panel system including a patch panel having a first outlet including a first conductive tab and a device having a second outlet including a second conductive tab. A patch cord has a first plug having a first screen for contacting the first tab and a second plug having a second screen for contacting the second tab. The patch cord includes a conductor electrically connecting the first screen and the second screen. An analyzer is electrically connected to the first tab and detects a connection between the first tab and the second tab along the conductor.

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract: An electrical scanning probe microscope (SPM) apparatus. The SPM apparatus is equipped with an atomic force microscope with an infrared laser source, a position-sensitive photo-detector (PSPD) to provide a topographic image, a charge-coupled device (CCD) monitor for optical alignment, and an electrical scanning sensor operatively coupled to the atomic force microscope to acquire synchronous two-dimensional electrical images. The photoperturbation effects induced by stray light and perturbation of the contrast of SCM images can thus be ameliorated.

Abstract: The present invention provides a semiconductor test device that can output a higher voltage as a driver output without increasing power consumption of a high-speed driver, so as to test a device under test. In order to achieve this, the semiconductor test device for switching a driver output between a plurality of voltages and a higher voltage that is higher than said plurality of voltages and outputting said driver output to test a device under test, includes: a first buffer portion operable to output said plurality of voltages by a push-pull circuit of an emitter follower serving as a source and an emitter follower serving as a sink; and a second buffer portion operable to output said higher voltage by a push-pull circuit of said emitter follower serving as said sink of said first buffer portion and an emitter follower serving as a source of said higher voltage.

Abstract: One embodiment of the invention relates to a test structure for testing an integrated circuit with a tester unit that has one or more connecting lines to connect the integrated circuit, wherein a test signal and/or a supply voltage is applied to the integrated circuit for the purposes of testing, and an interference unit connected to at least one of the connecting lines which applies an interference signal to the connecting line to reduce the quality of the test signal and/or the quality of the supply voltage.

Abstract: A leakage inverter has a switching delay in one direction that is directly proportional to the drain or gate leakage current of either an n-type or p-type device. For one aspect, a leakage ring oscillator includes an odd number of inverters including at least one leakage inverter such that the frequency of oscillation of the leakage ring oscillator is directly proportional to local device leakage. For another aspect, a leakage ring oscillator may be used to indicate temperature and/or temperature variation on a die.

Abstract: Low threshold current switch comprising a sensing transformer, a voltage multiplier and a switch enables monitoring a very low electric current in a power cable.

Abstract: Data is serially transferred from an IC1 to an IC2 through a plurality of data transmission paths. Elastic buffers are connected to the plurality of signal paths corresponding the plurality of data transmission paths. A skew adjustment circuit cancels a skew of data strings generated between the plurality of signal paths by a synchronizing process in the elastic buffer. Cancellation of a skew is executed on the basis of a buffer status and a control signal representing process contents in the elastic buffer. A skew generated between the plurality of signal paths of the system having the elastic buffer is canceled.

Abstract: There is provided a semiconductor integrated circuit device with a filer circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein the filter circuit includes: a first delay circuit activated within a certain period after each rising edge timing of input logic signals to delay the rising edge; a second delay circuit activated within a certain period after each falling edge timing of the input logic signals to delay the falling edge; and an output driver controlled by outputs of the first and second delay circuits to output delayed logic signals to an output node in response to the input logic signals.

Abstract: A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

Abstract: A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.

Abstract: There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality of transistors formed respectively in a plurality of semiconductor layers and a plurality of logic blocks formed in each of the plurality of semiconductor layers and connected to each of the plurality of signal lines. The first switch block is a programmable switch block capable of changing the connection topology among the plurality of signal lines.

Abstract: A programmable application specific integrated circuit (ASIC) for implementing operations that involve a plurality of computational functions. The programmable ASIC comprises a plurality of fixed functions and programmable switch logic. Each of the plurality of fixed functions is parameterized such that its operational characteristics are programmable using different operating parameters. In addition, each of the plurality of fixed functions inputs and outputs data in accordance with common interface rules. The programmable switch logic is configurable to link two or more of the fixed functions in a sequence to perform desired operations. The fixed functions are implemented using “hard” or fixed digital logic gates such as those in an ASIC.

Abstract: The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs. Proposed logic units, as separate units or a chain of units, which are mainly comprised of look-up tables, multiplexers, and latches, implement different mathematical and logical functions. Having two outputs, the embodiments of the logic unit can operate in a split mode and perform two separate logic and/or arithmetic functions at the same time. Chains of the proposed logic units, wherein every other unit is clocked by one of the two half clock cycles and utilizes local interconnections instead of traditional routing channels, add to efficiency and speed, and reduce required real estate.

Abstract: An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Abstract: Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

Abstract: A programmable logic device (PLD) includes a plurality of segments, a plurality of segment-enable registers, and a configuration controller. Each segment-enable register is arranged to be set to a first value in response to resetting of the PLD. Each segment includes configurable logic that is associated with a respective segment-enable register. In addition, each segment is arranged to enable the configurable logic in response to a second value for the associated segment-enable register. The configuration controller is adapted to program the respective configurable logic in each segment to perform a respective function based on configuration data and to set each segment-enable register to the second value.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets.

Abstract: A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.

Abstract: This invention enables a USB 1.1 device and a USB 1.1 host to communicate seamlessly with a USB OTG device. The invention complies with both USB 1.1 and OTG specifications. The invention includes the USB 1.1 host, USB 1.1 device and mixed signal circuits to implement USB OTG functions. The mixed signal components are controlled by the USB 1.1 device microcontroller. The invention is a cost effective implementation compared to a custom ASIC design for USB OTG implementation.

Abstract: Various embodiments for differential output circuits with reduced transistor sizes and reduced DC currents provide efficient and flexible differential driver circuits. AC current boosting enables the switching transistors that drive the output nodes to be smaller in size. The AC current boost circuitry is shared by both switching current paths in the differential output circuit to reduce size and parasitic effects. Similarly, DC current circuitry is also shared by both switching current paths. The AC boost circuit and the DC bias circuit are made programmable to enable the output circuit to support multiple I/O standards with different specifications.

Abstract: A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connected to the clock signal, and an output signal s2, an OR circuit having a first input connected to the data input, a second input connected to s2, and an output signal s3, and a FLIP-FLOP circuit whose first input is connected to s2, whose second input connected to s3, and whose output is OUT Q.

Abstract: A non-inverting domino register including a domino stage, a storage stage, a keeper circuit and an output stage. The domino stage includes evaluation logic, coupled between evaluation devices at a pre-charged node, which evaluates a logic function. The storage stage drives a first preliminary output node and includes a pull-up device and a pull-down device both responsive to the pre-charged node, and a second pull-down device responsive to the clock signal. The keeper circuit is a cross-coupled pair of inverters coupled between the first preliminary output node and a second preliminary output node. The output stage includes a pair of pull-up and pull-down devices for driving an output node. The first pull-up device and the first pull-down device are both responsive to the pre-charged node, and the second pull-up device and the second pull-down device are both responsive to the second preliminary output node.

Abstract: A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.

Abstract: A sense amplifier latch that is operable to interface with high common-mode input voltages with wide ranges for all process variations. The sense amplifier latch comprises a cross-coupled latch having first and second rail signals; a pre-charge device; an equalization device; pass devices for enabling input devices to receive pad and reference inputs. In the present invention, the input devices comprise push-pull impedance dividers are used to preserve the input difference voltage while dramatically lowering the common-mode output voltage. The outputs of the impedance dividers are fed to the cross-coupled latch of the sense amplifier using n-channel pass gates.

Abstract: An operational amplifier has a bias circuit, a differential amplifier, an output stage, and a feed forward circuit. The bias circuit provides a reference. The differential amplifier is coupled to a pair of input terminals and provides a differential output based on the first and second inputs. The output stage responds to the reference and to the differential output so as to supply a current to an output terminal. The feed forward circuit responds to the differential output in order to increase and decrease current to the output terminal. As a result, the feed forward circuit extends the dynamic range of the operational amplifier.

Abstract: A multi-phase signal generating apparatus is provided for readily generating multiple phase signals. The multi-phase signal generating apparatus comprises a signal data storage which stores a plurality of data segments for determining a predetermined period of one signal. A data segment selector circuit selects segments for constituting the phase signals from a plurality of data segments stored in the signal data storage for determining the predetermined period of a signal in each of a plurality of segment intervals which make up a phase signal cycle for generating a phase signal. Each phase signal generator circuit forms each phase signal using a plurality of selected segments for each phase signal during a plurality of segment intervals.

Abstract: A load sensing buffer circuit for providing a buffered clock signal with controlled switching current noise (di/dt) in which the input clock signal is selectively gated to provide successively generated source and sink current components as part of the buffered output signal, with the timing of such current components being dependent upon load capacitance.

Abstract: A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.

Abstract: Provided is a temperature-compensated bias circuit for a power amplifier, in which a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q3) and an emitter terminal of the third transistor is connected to a first diode (D1).

Abstract: A dual loop voltage regulation circuit of power supply chip is provided, comprising a capacitor for providing a voltage signal, a comparator for comparing a first reference voltage signal and the voltage signal to output forward or backward trigger signal, a first switch triggered by a forward trigger signal, a second switch triggered by a backward trigger signal, a first operational amplifier generating a first drive signal while the first and second switches are on, a first transistor switch triggered to be on by a first drive signal to provide a current source loop, a third switch triggered by a forward trigger signal, a fourth switch triggered by a backward trigger signal, a second operational amplifier generating a second drive signal while the third and fourth switches are on, and a second transistor switch triggered to be on by a second drive signal to provide a current sink loop.

Abstract: A bandgap voltage reference circuit (1) produces a bandgap voltage reference (Vref) on an output terminal (3) relative to a common ground voltage terminal (4). The circuit (1) develops a PTAT voltage across a primary resistor (r3) which is reflected and gained up across an output resistor (r4) and summed with a CTAT voltage to produce the voltage reference (Vref). A first circuit comprising a PTAT voltage cell (15) having first and second transistor stacks of first and second transistors (Q1,Q2) and (Q3,Q4) operated at different current densities develops a PTAT (2?Vbe) across a first resistor (r1). The PTAT voltage developed across the first resistor (r1) is applied to an inverting input of a first op-amp (A1), the output of which is coupled to a first end (9) of the primary resistor (r3).

Abstract: A programmable/tunable active low-pass filter at least has the resistors, capacitors and shunt control devices. It uses the linear property of the MOSFET to implement the shunt control devices. Based on the first-ordered linear analysis of the transfer function of the active-RC filter, it is found that the cut-off frequency of the active-RC filter can be tuned via the effective small-signal current controlled by the shunt control devices. Therefore, the filter of the present invention allowed users for fine tune the cut-off frequency linearly through the shunt control devices when the variation of the environment or procedure parameters of manufacture (i.e. thermo-effects) cause the cut-off frequency drift, thus, the cut-off frequency can be kept in a constant value. In addition, it needs the different cut-off frequency from the different application.

Abstract: A current conveyor circuit with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the power supply before the output signal becomes affected.

Abstract: A chopper-stabilized current-mode instrumentation amplifier comprises first and second input amplifiers coupled to respective input nodes and arranged to produce respective currents in response to a differential input voltage applied to the input nodes; the currents are coupled to an output node. To reduce gain errors that might otherwise arise due to the parasitic capacitances of the on- and/or off-chip devices and/or structures making up the input amplifiers, the invention includes gain correction circuitry coupled to the IA. The gain correction circuitry replicates at least some of the parasitic capacitances, and provides compensation currents to the IA which reduce both input- and output-referred gain errors that might otherwise arise.

Abstract: A power supply for a guitar amplifier and the guitar amplifier and method of operating the guitar amplifier. The power supply includes an alternating current power input having a secondary winding and a filament winding, an output and a first vacuum tube rectifier coupled between the secondary winding of the power input and the output for rectifying the alternating current at the power input. At least a second rectifier is provided which is selectively couplable in parallel with the first vacuum tube rectifier. The at least one second rectifier can be a vacuum tube rectifier with each of the first and second rectifiers having a cathode continually energized by the filament winding, a solid state rectifier or both. The output amplifier has an output transformer having a primary winding with a center tap and with a first pair of vacuum tube amplifiers having their cathodes being coupled together and their plates coupled to the primary winding on opposite sides of the center tap.

Abstract: A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.

Abstract: According to one exemplary embodiment, a circuit arrangement includes a power amplifier configured to receive an RF input signal. The circuit arrangement further includes a control circuit configured to receive and convert the RF input signal to an output DC voltage. The control circuit includes a voltage amplifier coupled to a peak detector circuit, where the peak detector circuit outputs the output DC voltage. The circuit arrangement further includes an analog control bias circuit coupling the output DC voltage to a bias input of the power amplifier. The output DC voltage causes the power amplifier to have a quiescent current that increases in a way that is substantially logarithmic with respect to the amplitude of the RF input signal. An increase in the RF input power can cause a substantially linear increase in the output DC voltage, where the RF input power is measured in dBm.

Abstract: A pre-distorter that compensates for amplitude and phase distortion created by an amplifier. During a training session, the amplifier is stimulated with input signals of pre-selected amplitude and phase at various temperatures and the amplifier output is captured and converted into data sets. Polynomials are then fitted to the data sets and inverses of the polynomials are determined. The coefficients of the inverse polynomials are then saved for each temperature. During operation, the amplifier temperature is predicted based on the amplifier input signal and the coefficients associated with the predicted temperature are selected to be applied to the input signal to compensate for amplitude and phase distortion caused by the amplifier.

Abstract: An RF amplifier system employing an analog predistortion module is disclosed. The disclosed analog predistortion module is based on zero crossings of the gain error curves (AM—AM and AM-PM curves minus DC). The hardware structure uses the product of first-order functions avoiding the need for large differential swings in the coefficients to shape the lower part of the gain curves. The higher-order nonlinear functions are preferably derived from a single envelope detector. An equal number of multipliers are preferably used in each path when the order of the magnitude and phase corrections are equal or differ by one, thus reducing delay mismatches between the magnitude and phase correction signals.