Abstract: An optical pickup unit comprising: a circuit connected to a light emitting device emitting light; and a counterpart circuit connected to the circuit, the circuit being soldered to the counterpart circuit.

Abstract: An apparatus and method for a silicon-based Micro-Electro Mechanical System (MEMS) device, including a pair of silicon cover structures each having a substantially smooth and planar contact surface formed thereon; a silicon mechanism structure having a part thereof that is movably suspended relative to a relatively stationary frame portion thereof, the frame portion being formed with substantially parallel and spaced-apart smooth and planar contact surfaces; a relatively rough surface disposed between the contact surfaces of the covers and corresponding surfaces of the movable part of the mechanism structure; and wherein the contact surfaces of the cover structures form silicon fusion bond joints with the respective contact surfaces of the mechanism frame.

Abstract: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and either the cover or the substrate includes an aperture.

Abstract: A method of fabricating a suspended beam in a MEMS process, said method comprising the steps of: (a) etching a pit in a substrate, said pit having a base and sidewalls; (b) depositing sacrificial material on a surface of said substrate so as to fill said pit; (c) removing said sacrificial material from a perimeter region within said pit and from said substrate surface surrounding said pit; (d) reflowing remaining sacrificial material within said pit such that said remaining sacrificial material contacts said sidewalls; (e) depositing beam material on said substrate surface and on said reflowed sacrificial material; and (f) removing said reflowed sacrificial material to form said suspended beam.

Abstract: A method of fabricating a CMOS image sensor is disclosed, by which image sensor characteristics are enhanced. In one aspect, the method includes forming a plurality of photodiodes in the photodiode region of a semiconductor substrate; stacking a first insulating layer over the semiconductor substrate including the photodiodes; forming a metal pad on the insulating layer in the pad region of the substrate; forming a second insulating layer over the semiconductor substrate including the metal pad; selectively etching exposed portions of the second insulating layer, using a mask, to form simultaneously a pad opening in the pad region and a trench in the photodiode region; selectively etching portions of the second insulating layer and the first insulating layer under the trench; and forming a slope on lateral sides of at least the second insulating layer.

Abstract: A fabricating method of the thin film array is provided. The thin film transistor array includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, an etch barrier layer and a plurality of pixel electrodes. The scan lines and the data lines are disposed over the substrate to define a plurality of pixel areas. Each thin film transistor is disposed in one of the pixel areas and driven by the corresponding scan line and data line. The etch barrier layer including a plurality openings is disposed over the scan line or a common line. Each pixel electrode electrically connected to the corresponding thin film transistor is disposed in one of the pixel areas, wherein a portion of each pixel electrode is coupled to the corresponding scan line through one of the openings to form a storage capacitor.

Abstract: In accordance with an embodiment the invention, there is a device manufacturing method. The method can comprise providing a substrate comprising a radiation-sensitive material disposed thereon and directing a beam of radiation through an aperture such that the radiation produces at least two illumination poles. The method can also comprise exposing the substrate to the at least two illumination poles using off-axis illumination and varying a size of a first illumination pole of the at least two illumination poles with respect to a second illumination pole of the at least two illumination poles.

Abstract: A Carbon NanoTube (CNT) structure includes a substrate, a CNT support layer, and a plurality of CNTs. The CNT support layer is stacked on the substrate and has pores therein. One end of each of the CNTs is attached to portions of the substrate exposed through the pores and each of the CNTs has its lateral sides supported by the CNT support layer. A method of vertically aligning CNTs includes: forming a first conductive substrate; stacking a CNT support layer having pores on the first conductive substrate; and attaching one end of the each of the CNTs to portions of the first conductive substrate exposed through the pores.

Abstract: In a method for manufacturing a compound semiconductor device, a principal surface of a SiC wafer, on which a compound semiconductor device is located, is bonded to a support substrate with an adhesive having a softening point higher than 200° C. A via hole is formed dry etching, including supplying a fluorine-containing etching gas to a rear side of the SiC wafer. Thereafter, the support substrate and the adhesive are removed. Preferably, the adhesive is formed by reacting one material coating the principal surface of the SiC wafer, and another material coating the support substrate.

Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.

Abstract: The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies.

Abstract: A high performance electric device which uses an adhesive layer over a substrate. A color filter is over a substrate, and an adhesive layer is also located over the substrate and color film. An insulating layer is over the adhesive layer, and thin film transistors cover the insulating film and the color filters. Light emitting elements cover the thin film transistors and emit light through the substrate that is through the adhesive layer and color filter. The substrate may be plastic, thus increasing the heat resistance.

Abstract: A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the conductive layer serves as programmable material, that in a low impedance state, electrically couples conductive structures. A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract: A method of forming a thin film transistor on a substrate including an insulating layer and layers of etchable material over the insulating layer by depositing a layer of photoresist made of polymers that are altered by actinic energy. In the method, an amine cross-linking agent is used with portions of the photoresist. The photoresist is differentially exposed to actinic energy to convert portions of the photoresist and portions are removed. Etching is selectively performed, followed by development of the remaining photoresist, followed by additional etching.

Abstract: A thin film transistor includes a semiconductor layer formed on a polycrystalline silicon layer crystallized by a super grain silicon (SGS) crystallization method. The thin film transistor is patterned such that the semiconductor layer does not include a seed or a grain boundary created when forming the semiconductor layer on the polycrystalline silicon layer.

Abstract: The present invention relates to a manufacturing method of a thin film transistor array panel. the method includes forming a gate line including a gate electrode on a substrate, forming a first insulating layer on the gate line, forming a semiconductor layer on the first insulating layer, forming an ohmic contact on the semiconductor layer, forming a data line including a source electrode and a drain electrode on the ohmic contact, depositing a second insulating layer, forming a first photoresist on the second insulating layer, etching the second insulating layer and the first insulating layer using the first photoresist as an etching mask to expose a portion of the drain electrode and a portion of the substrate, forming a pixel electrode connected to an exposed portion of the drain electrode using selective deposition, and removing the first photoresist.

Abstract: A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second etching process is executed with an etchant comprising oxygen to etch the doped semiconductor layer and the semiconductor layer, and the first resist layer undergoes ashing during etching so as to become a second resist layer with a channel pattern. The third etching process is another wet etching, and the second conducting layer is etched again using the second resist layer as the etching mask. The fourth etching process is executed to dry etch the doped semiconductor layer using the second resist layer as the etching mask.

Abstract: A liquid crystal display device includes (a) a first substrate, (b) a second substrate spaced away from and facing the first substrate, (c) a liquid crystal layer sandwiched between the first and second substrates, (d) a transistor formed on the first substrate, (e) a wiring layer formed on the first substrate and electrically connected to the transistor, (f) a reflection electrode formed on the first substrate, an external incident light being reflected at the reflection electrode towards a viewer, and (g) a compensation layer formed directly on the wiring layer. The reflection electrode does not cover the wiring layer therewith, and the compensation layer has almost the same height as a height of the reflection electrode, the height being measured from a surface of the first substrate.

Abstract: Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.

Abstract: A method for fabricating an electronic device is disclosed, the method comprising depositing a first layer of insulator over a substrate, depositing a first layer portion over the insulator using a printing technique, and removing a portion of the insulator using a photo-exposure technique or an etching technique, using the first layer portion as a mask. A vertical short channel thin film transistor is also disclosed, the transistor comprising a substrate, a first electrode formed over the substrate, a first layer of insulator formed over a portion of the first electrode, a second electrode formed over the first layer of insulator, a semiconductor layer forming a channel between the first and second electrodes, a dielectric layer formed over the semiconductor layer, and a gate electrode formed over the dielectric layer, wherein the gate electrode spans at least a part of the channel between the first and second electrodes.

Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

Abstract: Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101s, a protective film 102, and the silicon nitride film 103. A gate insulating film 109 is then formed on the inner walls of the gate trenches 108, and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108. The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.

Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

Abstract: An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.

Abstract: A conventionally followed technique of manufacturing a liquid crystal display device is a method for forming various types of coatings over an entire surface of a substrate and for removing the coatings with a small region left by etching, which requires wasting a material cost and treating a large quantity of waste. A liquid crystal display device is manufactured by forming at least one or more of patterns necessary for manufacturing a liquid crystal display device by a method capable of selectively forming a pattern. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition prepared for a specific purpose is employed as the method capable of selectively forming a pattern.

Abstract: A dynamic random access memory (DRAM) includes a substrate, an active device and a deep trench capacitor. A trench and a deep trench are formed in the substrate. The active device is disposed on the substrate. The active device includes a gate structure and a doped region. The gate structure is disposed on the substrate and fills the trench. The doped region is disposed in the substrate at a first side of the gate structure. The deep trench capacitor is disposed in the deep trench of the substrate at a second side of the gate, and the second side is opposite to the first side. In addition, an upper electrode of the deep trench capacitor is adjacent to the bottom of the trench.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

Abstract: A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer by remote plasma nitrogen (RPN).

Abstract: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4 F2.

Abstract: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.

Abstract: The invention relates to a semiconductor device (10) with a substrate and a semiconductor body (1) comprising a first FET (3) with a source (2) and a drain (3) that are provided with connection regions (2B, 3B) of a metal silicide, and that are connected to source and drain extensions (2A, 3A) bordering a channel region (4) below a gate (6) and having a smaller thickness and a lower doping concentration than the source (2) and the drain (3). The source (2) and drain (3) and the source and drain extensions (2A, 3A) are connected to each other by means of an intermediate region (2C, 3C) of the first conductivity type having a thickness and a doping concentration ranging between the thickness and doping concentration of the source (2) and drain (3) and the extensions (2A, 3A) thereof.

Abstract: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.

Abstract: A memory transistor and a high breakdown voltage MOS transistor are easily formed on the same semiconductor substrate without changing the operational characteristics of the memory transistor. The process of forming the tunnel insulation film of the memory transistor and the process of forming the gate insulation film of the MOS transistor are performed separately. Concretely, an insulation film to be a part of the tunnel insulation film and a silicon nitride film are formed on the whole surface, and then the silicon nitride film in a MOS transistor formation region is selectively removed using a photoresist layer. Then, the MOS transistor formation region is selectively oxidized using the remaining silicon nitride film as an anti-oxidation mask to form the gate insulation film of the MOS transistor having a selected thickness.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: A microelectronic device comprises a substrate and a transistor. The transistor comprises a channel region in the substrate, a recess in the channel region, a first dielectric layer and a second dielectric layer. The first dielectric layer comprises a first dielectric material and is deposited at the bottom of the recess. The second dielectric layer comprises a second dielectric material and is deposited at a sidewall of the recess. The dielectric constant of the first dielectric material is higher than the dielectric constant of the second dielectric material. A gate electrode is positioned in the recess and is electrically insulated from the channel region by the first and second dielectric layers.

Abstract: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Y?m/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.

Abstract: To provide a polishing composition which allows high-speed polishing while etching and erosion are prevented and the flatness of metal film is maintained, there is provided a a polishing composition, comprising (A) a compound having three or more azole moieties, (B) an oxidizing agent, and (C) one or more species selected from among an amino acid, an organic acid, and an inorganic acid.

Abstract: A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step of depositing a layer of a meltable material on a wafer surface. The material is then pressed using a transparent mold while shining a light pulse through the transparent mold to melt the deposited layer of meltable material. A flow of the molten layer material fills the holes and trenches, and conforms to surface features on the transparent mold. The transparent mold is subsequently removed.

Abstract: A semiconductor device includes a semiconductor substrate and first and second trenches. The first trench with a high aspect ratio is formed in a surface of the semiconductor substrate and has a bottom, two sidewalls and an open end. The first trench is formed so that at the bottom side, an inclination of each sidewall relative to the bottom has a first angle approximate to a right angle and at the bottom side, the inclination of each sidewall relative to the bottom has a second angle smaller than the first angle. The second trench has a lower aspect ratio than the first trench. The second trench has a bottom, two sidewalls and an open end and is formed so that an inclination of each sidewall relative to the bottom is substantially uniform from the bottom side to the open end side and has a third angle which is approximate to the second angle.

Abstract: Provided herein are methods and apparatuses for analog molecules, particularly polymers, and molecular complexes with extended confirmations. In particular, the methods and apparatuses are used to identify sequence information in molecules or molecular ensembles which is subsequently used to determine structural information about the molecules. Further, provided herein are various methods of forming probes and films for making such probes of nanoscale dimension.

Abstract: A method of processing a wafer includes a masking process for providing a mask on a surface of a film-formed wafer except for a wafer peripheral portion, and polishing process for spraying a processing liquid containing an inorganic material onto the wafer peripheral portion. According to the method of processing a wafer, it is possible to easily remove impurities existing on a wafer peripheral portion.

Abstract: The present invention provides a method of forming recesses on a substrate, the method including forming on the substrate a patterning layer having first features; trim etching the first features to define trimmed features having a shape; and transferring an inverse of the shape into the substrate.

Abstract: Provided are a wafer having an indicator for a first die and a method of attaching a die of the wafer. The wafer includes an indicator formed on a back surface at a position corresponding to a position of a first die on a front surface, for indicating the position of the first die. The method of attaching the die of the wafer includes forming an indicator for a first die, comparing positions of the indicator and the first die, and attaching the die of the wafer. In forming the indicator, the indicator is formed on a back surface of the wafer for indicating the position of the first die. In comparing the positions, the position of the first die formed on a front surface of the wafer is compared with the position of the indicator formed on the back surface of the wafer. If a position error between the positions of the first die and the indicator is smaller than a reference value, the attaching of the die of the wafer performed.

Abstract: A semiconductor device includes a semiconductor chip and an adhesive film between the back side of the semiconductor chip and a chip pad of a leadframe. The adhesive film includes a film core and adhesive layers that cover both sides of the film core. The film core includes a brittle, fragile hard material.

Abstract: Apparatuses and methods for improved fluidic self assembly (FSA). An apparatus performing an improved FSA method can include one or more of a block deposition and clearing section, a drying section, a lamination section and an inspection section. In a specific embodiment, each of these sections are connected in series but distinctly separate. The deposition and clearing section can additionally include dispenser nozzles, rolling pins, and a cross-flow jet pump nozzle, as well as other components.

Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.

Abstract: Disclosed are a chemical vapor deposition apparatus capable of improving gap-fill characteristics, an operating method thereof, and a method of manufacturing a semiconductor device. The chemical vapor deposition apparatus includes a first induction coil installed on an upper portion of a chamber to feed a first power having a first radio frequency (RF) into the chamber; an electrostatic chuck corresponding to the first induction coil so as to feed a second power having a second RF into the chamber, in which the substrate is laid on the electrostatic chuck; and a gas nozzle for feeding a reaction gas into the chamber. The second RF is in a range of from 0.1 to 100 KHz.

Abstract: The present invention provides a method for manufacturing a compound semiconductor substrate. The method for manufacturing a compound semiconductor substrate comprises the steps of: (a) epitaxially growing a compound semiconductor functional layer 2 on a substrate 1, (b) bonding a support substrate 3 to the compound semiconductor functional layer 2, (c) polishing the substrate 1 and a part of the compound semiconductor functional layer 2 on the side which is in contact with the substrate 1, to remove them, (d) bonding a thermally conductive substrate 4 having a thermal conductivity higher than that of the substrate 1 to the exposed surface of the compound semiconductor functional layer 2 which is provided in the step (c) to obtain a multilayer substrate and (d) separating the support substrate 3 from the multilayer substrate.

Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.