Abstract: Rather than depositing a heater material into a pore, a heater material may be first blanket deposited. The heater material may then be covered by a mask, such that the mask and the heater material may be etched to form a stack. Then, the region between adjacent stacks that form separate cells may be filled with an insulator. After removing the mask material, a pore is then formed in the insulator over the heater. This may then be filled with chalcogenide to form a phase change memory.

Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1?xGex layer on a substrate, a strained channel layer on the relaxed Si1?xGex layer, and a Si1?yGey layer; removing the Si1?yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

Abstract: In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate.

Abstract: A method of manufacturing contact hole is provided. First, a mask layer is formed on a substrate and a plurality of trenches is formed in the mask layer along two directions that cross over each other. The depth of the trenches is not greater than the thickness of the mask layer. However, there is an opening in the mask layer in the place where the trenches cross over each other. The opening exposes the substrate. Part of the substrate exposed by the opening is removed to form a contact hole in the substrate. In photolithography, it is easier to form lines than to form dots. Hence, the dimensions of contact holes are more precisely controlled.

Abstract: An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.

Abstract: An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition.

Abstract: A first insulating film is formed on a substrate or a lower metal wiring, and a first metal layer is formed on the first insulating film. A second insulating film and a third insulating film are formed on the first insulating film and the first metal layer, and the third insulating film and the second insulating film are selectively slope-etched by using a first photosensitive film mask to form a sloped pad opening portion. A barrier metal layer and a pad metal layer are formed over the substrate, and the pad metal layer and the barrier metal layer are selectively etched by using a second photosensitive film mask to form a bonding pad. A fourth insulating film is formed over the substrate, and the fourth insulating film is selectively etched by using a third photosensitive film mask to expose a part of the bonding pad.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such that the trench is filled in with the metal layer; (D) forming the interconnection by removing an excess metal layer outside the trench; (E) modifying a surface of the insulating film to form a modified layer on the insulating film; and (F) forming a metal film selectively on the interconnection by using plating solution after the (E) modifying process.

Abstract: The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via hole is partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the via hole. A substantially conformal sacrificial layer is deposited on the top surface of the dielectric stack and in the recess. Then, a photoresist layer is deposited on the sacrificial fill. A trench etch mask overlaying the via hole, is developed in the photoresist layer. This mask is etched through the sacrificial layer that is formed on the top surface of the dielectric stack as well as through the sacrificial fill and sacrificial layer that is present in the via hole.

Abstract: Emulsion compositions containing a silicone polymer and organic polymer as an alloy and/or hybrid emulsion can be made by (i) first forming an emulsion containing a silicone polymer by emulsion polymerization in which (a) the ring of a cyclic siloxane oligomer is opened, in which (b)an hydroxy endblocked siloxane oligomer is condensed, using an acid or base catalyst in the presence of water, or in which (c) an hydrogen endblocked siloxane oligomer and a vinyl endblocked siloxane oligomer are reacted by hydrosilylation using a catalyst; (ii) adding to the emulsion in (i) the components for preparing an emulsion containing an organic polymer by free radical emulsion polymerization of an ethylenically unsaturated organic monomer, and (iii) heating the emulsion. The resulting coalesced compositions produce polymer blends or alloys whose properties are influenced by the composition and morphology of the hybrid emulsion particles.

Abstract: The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a planarized top surface. The dielectric layer is not planarized at this stage of the process. A pre-planarizing thickness profile of the non-planarized dielectric layer is determined and recorded. An interconnect line trench is then etched through the dielectric layer. A sandwich layer including a conductive Cu diffusion barrier layer and a Cu seed layer is deposited in the trench and on the dielectric layer. A Cu comprising metal is deposited in the sandwich lined trench. A Cu metal overburden is thereby deposited on the section of the sandwich layer that is positioned on the dielectric layer. A first CMP process is used to remove the Cu overburden and the Cu seed layer that is formed in the sandwich layer portion on the dielectric layer.

Abstract: Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.

Abstract: Disclosed is a method of forming a dual damascene pattern. The method can include forming a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a cap insulating layer on a substrate, forming a preliminary via hole exposing a part of the first etch stop layer by patterning the insulating layer structure, and forming a sacrificial layer pattern in the preliminary via hole. After forming a mask pattern on the cap insulating layer, a trench is formed by patterning the cap insulating layer, the second dielectric layer and a part of the sacrificial layer. The sacrificial layer pattern and the mask pattern are removed in-situ through an ashing process, thereby forming a via hole.

Abstract: A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive patterns. A hard mask including an amorphous carbon layer and an oxide based layer are formed in sequential order over the insulation layer and the conductive pattern. The amorphous carbon layer and the oxide layer are selectively etched to form a mask pattern. The insulation layer is etched using the mask pattern as a mask to form a contact hole.

Abstract: A method of etching a carbon-containing layer on a semiconductor substrate using a Si-containing gas and a related method of fabricating a semiconductor device in which a plurality of contact holes having excellent sidewall profiles are formed by etching an interlayer insulating layer using a carbon-containing layer pattern formed in accordance with the invention and having a width of several tens of nm as an etch mask are provided. To etch a carbon-containing layer to be used as a second etch mask, a first mask pattern is formed on the carbon-containing layer to partially expose a top surface of the carbon-containing layer. The carbon-containing layer is then anisotropically etched with a plasma of a carbon-etching mixture gas formed of O2 and a Si-containing gas using the first mask pattern as a first etch mask to form the carbon-containing layer pattern.

Abstract: Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based semiconductor device. The method for manufacturing the nitride based single crystal substrate includes forming a nitride based single crystal layer on a preliminary substrate; forming a polymer support layer by applying a setting adhesive material having flowability on the upper surface of the nitride based single crystal layer and hardening the applied adhesive material; and separating the nitride based single crystal layer from the preliminary substrate by irradiating a laser beam onto the lower surface of the preliminary substrate. The method for manufacturing the nitride based single crystal substrate is applied to the manufacture of a nitride based semiconductor device having a vertical structure.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.

Abstract: A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.

Abstract: An apparatus of chemical mechanical polishing has a polishing machine, a first thickness metrology and a second thickness metrology. The first thickness metrology is connected with the polishing machine, and the second thickness metrology is connected with the polishing machine. Since the thickness of the first material layer and the second material layer after polishing process can be separately measured by the first thickness metrology and the second thickness metrology in-situ, the difference of film thickness between wafers can be reduced.

Abstract: This disclosure is concerned a method of manufacturing a semiconductor device which includes providing an dielectric film on a substrate; providing a mask material on the dielectric film; etching the dielectric film using the mask material; performing a first treatment of removing a metal residue generated by etching the dielectric film; performing a second treatment of making a sidewall of the dielectric film formed by etching the dielectric film hydrophobic; and performing a third treatment of removing a silicon residue generated by etching the dielectric film.

Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.

Abstract: A method of manufacturing a semiconductor device, includes forming a sacrifice film on an etching target film, forming an etching mask on the sacrifice film, etching the etching target film using the etching mask as a mask, removing the sacrifice film to allow the etching mask to adhere to the etching target film, and removing the etching mask.

Abstract: A method for forming a metal silicide over a substrate is provided. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system of the first tool system is broken. The substrate is transferred from the first tool system into a second tool system. A metal silicide layer is formed over the substrate in the second tool system.

Abstract: A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

Abstract: A resist film removing method for removing a resist film disposed on a substrate and having a cured layer at a surface includes covering the surface of the resist film with a protection film; causing popping in the resist film covered with the protection film; denaturing the resist film and the protection film after causing popping, to be soluble in water; and performing purified water cleaning to remove from the substrate the resist film and the protection film denatured to be soluble in water.

Abstract: A composition for removing an insulation material and related methods of use are disclosed. The composition comprises about 1 to 50 percent by weight of an oxidizing agent, about 0.1 to 35 percent by weight of a fluorine-containing compound, and water. The insulation material comprises at least one of a low-k material and a protection material.

Abstract: A wafer having a metal layer inclding salicide regions and unreacted metal regions disposed thereon is provided. Subsequently, an acidic solution is provided to remove the unreacted metal regions. Following that, a cold APM solution is used to remove particles subsequent to using the acidic solution to remove the unreacted metal regions. Finally, a mega sonic energy is applied to the wafer together with the cold APM solution or separately.

Abstract: A photoresist coating apparatus, medium, and method for efficiently spraying a liquid photoresist to maintain an atmosphere of ionized solvent vapor between a substrate and a spray nozzle of an upper portion by using a vapor inducing pipe supplying ionized solvent vapor, with the atmosphere being maintained by differently biasing a lower portion supporting the substrate and a plate of the upper portion. Photoresist can be evenly coated over the entire surface of the substrate while reducing the loss of sprayed photoresist droplets.

Abstract: An organometallic complex represented by the structure: wherein M is a metal selected from Group 4 of the Periodic Table of the Elements and R1-4 can be same or different selected from the group consisting of dialkylamide, difluoralkylamide, hydrogen, alkyl, alkoxy, fluoroalkyl and alkoxy, cycloaliphatic, and aryl with the additional provision that when R1 and R2 are dialkylamide, difluoralkylamide, alkoxy, fluoroalkyl and alkoxy, they can be connected to form a ring. Related compounds are also disclosed. CVD and ALD deposition processes using the complexes are also included.

Abstract: A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating laye

Abstract: A dielectric material layer is formed on a carrier material. A gas mixture containing at least one precursor comprising a metallic element is alternately circulated with an oxidant gas in contact with the carrier material under first oxidizing conditions so as to form a first sub-layer having dielectric qualities. A gas mixture containing the same precursor then is circulated in contact with the first sub-layer under second oxidizing conditions being more strongly oxidizing than the first oxidizing conditions so as to form a second sub-layer having dielectric qualities.

Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Abstract: The invention refers to a pre-metal dielectric semiconductor structure comprising a substrate, having features on a surface of the substrate, wherein the features are spaced from at least one gap between the features. The gap is filled with an advantageous layer combination. The layer combination comprises at least one spin-on dielectric layer. Additionally a further insulating layer is disposed or a further silicate glass layer doped with phosphorus is arranged. Using this layer combination, the filling of the gap with less or no voids and advantageous chemical and/or mechanical and/or electrical features is attained.

Abstract: A method of forming an electrically insulating layer (130) on a compound semiconductor (110) comprises: providing a compound semiconductor structure; preparing an upper surface (111) of the compound semiconductor structure to be chemically clean; forming a template (120) on the compound semiconductor structure using a first precursor in a metalorganic chemical vapor deposition (MOCVD) system or a chemical beam epitaxy (CBE) system; and introducing oxygen and a second precursor to the MOCVD system in order to form the electrically insulating layer.

Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Abstract: A method and apparatus for low temperature deposition of doped silicon nitride films is disclosed. The improvements include a mechanical design for a CVD chamber that provides uniform heat distribution for low temperature processing and uniform distribution of process chemicals, and methods for depositing at least one layer comprising silicon and nitrogen on a substrate by heating a substrate, flowing a silicon containing precursor into a processing chamber having a mixing region defined by an adaptor ring and one or more blocker plates and an exhaust system heating the adapter ring and a portion of the exhaust system, flowing one or more of a hydrogen, germanium, boron, or carbon containing precursor into the processing chamber, and optionally flowing a nitrogen containing precursor into the processing chamber.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: An electrical adapter (100) in accordance with the present invention includes a first connector (20), a second connector (30) and an adapting device (10) electrically interconnecting with the first and the second connectors. The adapting device includes a first printed circuit board (120) defining a number of first through holes (121), a second printed circuit board (130) defining a number of second through holes (131) in alignment with the first through holes, a number of conductive pins (110) inserting through the first and the second through holes, and a conductive shell (140) enclosing the first and the second printed circuit boards and attached to at least one of the first and the second printed circuit boards.

Abstract: A right angle coaxial connector comprises a unitary body, (1) having a dielectric insulating member (4) secured along a longitudinal tubular bore extending along axis F-F through said unitary body (1) and holding a predominantly longitudinal inner conductor (2), having male ends (2A, 2B), in its correct position along the bore's central axis F-F with an integral perpendicular node (2B) lying along the axis E-E, a shell (6) extending along a lateral axis E-E having dielectric insulating member (8) secured along a lateral tubular bore extending through said shell (6) and holding a lateral inner conductor (7) having female ends (7A, 7B), where said unitary body (1) and shell (6) are fixably joined at a pair of interfaces (B, C) and the corresponding male (2B) and female (7A) ends of the respective inner terminals (2, 7) are releasably attached to one another.

Abstract: According to one embodiment, signal processing equipment comprising a second circuit conducting signal processing by the first supply voltage generated in the first circuit, a fourth circuit conducting signal processing by the second supply voltage generated in the third circuit, a standard ground terminal to which each ground terminal of the second and fourth circuits connect, and a circuit board leading the first and second supply voltage generated in the first and third circuits to the second and fourth circuits respectively, and forming a plain ground pattern to which each ground terminal from the first to fourth circuits connects.

Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.

Abstract: An embodiment of the present invention is a Land Grid Array (LGA) socket. A first L-shaped area has a first center, a first outer long side, and a first outer short side. The first L-shaped area contains a first set of contacts oriented in a first direction. A second L-shaped area has a second center, a second outer long side, and a second outer short side and is located symmetrically to the first L-shaped area. The second L-shaped area contains a second set of contacts oriented in a second direction opposite to the first direction such that pressing a device on the first and second sets of contacts results in approximately zero force and moment.

Abstract: An electrical connector assembly (100) includes an electrical connector (2) with a first plurality of holes (230) thereon, a heat sink (3) mounted onto the electrical connector and including a second plurality of holes (300) thereon, a substrate (4) mounted onto the electrical connector and including a third plurality of holes (400) thereon. The second plurality of holes and the third plurality of holes are aligned with and in communication with the first plurality of holes. A plurality of pin-like elements (1) is respectively insertable into the first plurality of holes, the second plurality of holes and the third plurality of holes so as to hold the heat sink, the electrical connector and the substrate together. Since the substrate is needed to define a single group of holes in correspondence with the pin-like elements, much more room is available on the substrate for active and passive electronic elements to be equipped therewith.

Abstract: A male contact, a connector assembly of the type used to electrically connect electrical devices includes male contacts, and a method of manufacturing an electrical connector are disclosed.

Abstract: An electric contactor includes an insulating main body and a plurality of conducting terminals. Several terminal accommodating holes are formed on the insulating main body. Each accommodating hole has a first conducting terminal and a second conducting terminal connected together, and the first and second conducting terminals can move relative to each other. The first and second conducting terminals are made of different materials. The first conducting terminal is made of material with a higher conductivity, while the second conducting terminal is made of material with a larger tensile strength. The conducting terminals have a high conductivity, a simple structure, can effectively reduce the inductive effect, and can be densely arranged, thereby meeting the requirement of high-frequency circuits and realizing high transmission of electronic component and circuit board.

Abstract: A power transmission chain (1) has links (11), pins (14), and interpieces (15). The links (14) each have a front and a back insertion parts (12, 13) through which the pins are inserted. The pins (14) and the interpieces (15) connect links (11) that are arranged side by side in the lateral direction of the chain such that the front insertion part (12) of one of the links (11) and the rear insertion part (13) of the other link (11) correspond to each other, and the connection is made such that that the links (11) are bendable in the longitudinal direction. The locus of a contact position of a pin (14) and an interpiece (15) is an involute of a circle. Two or more kinds of sets of a pin (14) and an interpiece (15) having different radii of base circles of involutes are formed, and these sets of a pin (14) and an interpiece (15) are randomly arranged.

Abstract: A snap-on tab assembly for electrically grounding a fluid separation device comprising a main body having a first surface for securing the main body to the separation device without the aid of a tool and a second surface for maintaining the main body in continuous electrical contact with the separation device and a tab extending from the main body to provide a grounding connection for discharging static electricity from the separation device.