Abstract: Disclosed herein is a nitride semiconductor light emitting device, which is improved in luminance and reliability. The light emitting device, comprises an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer sequentially formed on a substrate, an n-side electrode formed on a portion of an upper surface of the n-type nitride semiconductor layer, and at least one intermediate layer formed between the substrate and the n-type nitride semiconductor layer. The intermediate layer has a multilayer structure of three or more layers having different band-gaps, and is positioned below the n-side electrode.

Abstract: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.

Abstract: An HF control bi-directional switch component of the type having its gate referenced to the rear surface formed in the front surface of a peripheral well of the component, including two independent gate regions intended to be respectively connected to terminals of a transformer having a midpoint connected to the rear surface terminal of the component.

Abstract: A semiconductor device comprises a substrate defining a recessed active region; a fin active region connected to the recessed active region and extending above the recessed active region. The fin active region includes first, second, third, fourth, and fifth sides, the first and second sides being proximate the recessed active region, the fifth side being an upper side of the fin active region, the third side being provided between the first side and the fifth side, the fourth side being provided between the second side and the fifth side. A gate insulation layer is formed over the first, second, third, fourth, and fifth sides of the fin active region. A gate electrode layer is formed over the gate insulation layer to substantially surround the first, second, third, fourth, and fifth sides of the fin active region.

Abstract: The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

Abstract: Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N? (P?) type epitaxial region on a N+ (P+) type substrate and forming a trench in the N? (P?) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+ (N+) type doped polysilicon region and N+ (P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.

Abstract: The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and hi

Abstract: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

Abstract: An ultrafast recovery diode. In a first embodiment, a rectifier device comprises a substrate of a first polarity, a lightly doped layer of the first polarity coupled to the substrate and a metallization layer disposed with the lightly doped layer. The ultrafast recovery diode includes a plurality of wells, separated from one another, formed in the lightly doped layer, comprising doping of a second polarity. The plurality of wells connect to the metallization layer. The ultrafast recovery diode further includes a plurality of regions, located between wells of said plurality of wells, more highly doped of the first polarity than the lightly doped layer.

Abstract: A semiconductor device operating at a frequency between 0.8 GHz and 300 GHz includes an active region that is positioned on a semi-insulating GaAs substrate; a gate electrode that is positioned in the active region; and a source electrode and a drain electrode that are positioned on the surface of the active region facing each other with the gate electrode positioned between the source electrode and the drain electrode. A drain side active region, which is a part of the active region and positioned between the gate electrode and the drain electrode, increases in width in the direction to the drain electrode from the gate electrode.

Abstract: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.

Abstract: A semiconductor device having a lateral channel with contacts on opposing surfaces thereof. The semiconductor device includes a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes an isolation layer above the conductive substrate, a lateral channel above the isolation layer and a drain contact above the lateral channel. The semiconductor device further includes a gate located in a gate recess interposed between the lateral channel and the drain contact and a drain formed by at least one source/drain contact layer interposed between the lateral channel and the drain contact. The drain is offset on one side of the gate by a gate-to-drain separation distance. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the source contact and the lateral channel.

Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Abstract: A CMOS image sensor and a method of manufacturing the same are provided. The method is capable of reducing a distance between a micro-lens and a photodiode and simplifying the manufacturing process for the CMOS image sensor. In an embodiment, the interlayer dielectric layers of high level metal lines (e.g. third level and higher metal lines) can be selectively removed from the sensing section of a semiconductor substrate. The color filter layers and microlenses can be formed on the sensing section after the interlayer dielectric layers of the high level metal lines have been selectively removed.

Abstract: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray toward a light receiving element the without transmitting it to the wiring layer, the infrared ray entering from a light transparent substrate toward the wiring layer through a semiconductor substrate. The reflection layer is formed at least in a region under the light receiving element uniformly or only under the light receiving element. Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.

Abstract: A circuit for controlling an internal voltage of a semiconductor memory apparatus including a deep power down signal input unit, which receives a deep power down signal indicating that a deep power down mode is starting, and supplies the received signal to a level shifter; and one or more level shifters, each of which performs level shifting from a first voltage to a second voltage or sinks the second voltage to a ground voltage in response to the input of the deep power down signal.

Abstract: A CMOS image sensor and method of manufacturing same is provided. The CMOS image sensor can include: photodiodes formed on a semiconductor substrate for generating a charge according to an amount of incident light; a first planarization layer formed on the semiconductor substrate; a plurality of color filter layers formed on the first planarization layer, an upper surface of each of the color filter layers being curved; and a plurality of microlenses formed on the plurality of color filter layers.

Abstract: A CMOS (complementary metal oxide semiconductor) image sensor and method of fabricating the same is provided. The CMOS image sensor can include: a semiconductor substrate in which an active region and a device isolation region are defined; a photodiode region including a first region and a second region extending from the first region formed on the active region, wherein impurity ions of a first conductivity type and impurity ions of a second conductivity type are implanted in the first region, and impurity ions of the first conductivity type are implanted in the second region; and a transistor and an impurity diffusion region of a first conductivity type formed on a transistor region of the active region.

Abstract: The present invention provides always stably sampling a high quality image irrespective of the displacement of a subject, with a simpler arrangement.

Abstract: Embodiments relate to a complementary metal oxide semiconductor (CMOS) image sensor. According to embodiments, the CMOS image sensor may include a semiconductor substrate, an interlayer insulating layer, a color filter layer, an overcoat layer, and a plurality of microlenses. The semiconductor substrate may include a plurality of photodiodes and transistors with a constant interval. The color filter layer may be formed on the interlayer insulating layer, and respective color filters of the color filter layer correspond to respective photodiodes. The overcoat layer may have rounded trenches at a portion corresponding to each photodiode and may be formed on a surface of the semiconductor substrate. Each of the plurality of microlenses may have a convex lens shape and is formed inside the trench.

Abstract: Embodiments relate to an image sensor. In embodiments, the image sensor may include a semiconductor substrate formed with a plurality of photodiodes, an interlayer dielectric layer formed on the semiconductor substrate, a color filter layer formed on the interlayer dielectric layer, a planar layer formed on the color filter layer, and a micro-lens formed on the planar layer. A hole having a predetermined pattern is formed on a top surface of the interlayer dielectric layer. The hole having the prescribed pattern may be formed in the interlayer dielectric layer. Accordingly, an adhesive force between the interlayer dielectric layer and the color filter layer formed on the interlayer dielectric layer may be improved. This may enable fabrication of an image sensor having high-sensitivity without causing a defective pixel.

Abstract: A solid-state image sensor capable of suppressing generation of cross talk or a dark current and improving transfer efficiency of electrons (signal charge) can be obtained. This solid-state image sensor includes a plurality of pixels and a transfer gate electrode arranged in each of the plurality of pixels. An OFF-state voltage of the transfer gate electrode located on a boundary part between the pixels during an imaging period is lower than an OFF-state voltage of the transfer gate electrode located on the boundary part between the pixels during a transfer period.

Abstract: Embodiments relate to a method for forming an isolation trench of a semiconductor device. In embodiments, a method for forming an isolation trench of a semiconductor device may include forming a mask layer pattern on a semiconductor substrate, forming an organic material layer on the semiconductor substrate and the mask layer, and forming an isolation trench having a width defined by the mask layer pattern and an organic material spacer layer formed by etching the organic material layer through an etching process for the organic material layer and the semiconductor substrate.

Abstract: An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to the first epitaxial layer. A plurality of trenches is recessed into the first epitaxial layer, each of which is coupled to the metallization layer. The device also includes a plurality of wells each doped with a second dopant type, wherein each well is formed beneath and adjacent to a corresponding trench. A plurality of oxide layers is formed on walls and a bottom of a corresponding trench. A plurality of channel regions doped with the first dopant is formed within the first epitaxial layer between two corresponding wells. Each of the plurality of channel regions is more highly doped with the first dopant than the first epitaxial layer.

Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain is obtained through non symmetric placement of stress inducing structures as part of the gate electrode. Silicon nitride layers may be placed on one side of the gate electrode in a compressive mode, or on the other side of the gate electrode in a tensile mode to obtain similar results.

Abstract: Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.

Abstract: Embodiments relate to a semiconductor device that may include a gate stack formed on an upper portion of an active region in a semiconductor substrate, the gate stack including a gate insulating layer and a gate, a first shallow impurity region formed on both sides of the gate in the semiconductor substrate, a gate spacer layer formed on one side of the gate stack, and a second deep impurity region formed in the semiconductor substrate by using the gate spacer layer as a mask, in which the gate is formed by implanting p-type ions.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an active area defined on a semiconductor substrate by a first isolation layer and a second isolation layer, a diode in the active area placed at one side of the first isolation layer, a transfer gate formed at one side of the diode, and an electrode on the diode and the transfer gate.

Abstract: Embodiments relate to a method for manufacturing a semiconductor substrate. According to embodiments, a gate oxide layer may be formed on a semiconductor substrate. Also, a well region may be formed in the semiconductor substrate including the gate oxide layer. Then, after forming a gate electrode on the semiconductor substrate, a liner layer may be formed on the semiconductor substrate. Next, the semiconductor substrate including the liner layer may be annealed to form an annealed liner layer. Finally, an interlayer insulation layer may be formed on the annealed liner layer.

Abstract: Embodiments relate to a MOS varactor and a method for manufacturing the same, in which an ion implantation process for adjusting a threshold voltage may be omitted so as to lower the surface density of an N type well, thereby expanding a tuning range. The MOS varactor may include a semiconductor substrate having an active area and a field area, in which an isolation layer is formed on the field area, an N type well formed at the active area of the semiconductor substrate, a gate insulating layer and a gate electrode formed at an upper side of the N type well, and an N type impurity area formed in the N type well at both sides of the gate electrode, wherein an impurity surface density of the N type well is in a range of 1016 atoms/cm3 to 1017 atoms/cm3.

Abstract: An exemplary thin film transistor substrate (200) includes a substrate (201), a gate (212), a gate insulating layer (203), an amorphous silicon layer (214), a pixel electrode (216), a drain (217), and a source (218). The gate is formed at the gate. The gate insulating layer is formed at the gate. The amorphous silicon layer is formed at the gate insulating layer. The transparent conductive layer is formed at the amorphous silicon layer. The pixel electrode is formed at the amorphous silicon layer. The drain is formed at the pixel electrode. The source is formed at the transparent conductive layer.

Abstract: An image sensor may include at least one of: a semiconductor substrate including a plurality of photodiodes and a pad section; a protective layer formed over a semiconductor substrate including a trench pattern; an interlayer dielectric layer formed over a cell area of a protective layer; a color filter layer formed over an interlayer dielectric layer to allow light having a specific wavelength band to pass through; a planar layer formed over a color filter layer; and/or a micro-lens formed over a planar layer to guide light into photodiodes.

Abstract: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.

Abstract: A CMOS image sensor and method of manufacturing the same are provided. In one embodiment, the CMOS image sensor includes: an interlayer dielectric layer formed on a semiconductor substrate including a plurality of photodiodes and transistors; a plurality of color filter isolation layers formed on the interlayer dielectric layer; a color filter layer comprising a first color filter, a second color filter, and a third color filter formed on the interlayer dielectric layer, wherein a portion of the first color filter and a portion of the second color filter are formed on one of the plurality of color filter isolation layers, and wherein a portion of the second color filter and a portion of the third color filter are formed on another of the plurality of color filter isolation layers; and microlenses formed on the color filter layer.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes a semiconductor substrate having a photodiode region and a transistor region defined therein, first and second gate electrodes formed on the photodiode region of the semiconductor substrate with a gate insulating layer interposed therebetween, the first and second electrodes connected in a “?” shape spaced a predetermined interval from each other, a first conductivity type diffusion region formed in the photodiode region including between the first and second gate electrodes, spacer insulating layers formed on sidewalls of the first and second gate electrodes, and a floating diffusion region formed in the transistor region.

Abstract: Provided is a CMOS image sensor. The CMOS image sensor can include a semiconductor substrate, a blue photodiode region, a red photodiode region, a green photodiode region, an overcoat layer, and microlenses. The substrate can have a first photodiode region, a second photodiode region, and a transistor region. The blue photodiode region is formed having a predetermined depth in the first photodiode region. The red photodiode region is formed in the first photodiode region having a depth greater than that of the blue photodiode region with a gap separating the red photodiode region from the blue photodiode region. The green photodiode region is formed in the second photodiode region having a depth between the depths of the blue and red photodiode regions. The overcoat layer is formed on the semiconductor substrate, and microlenses are formed on the overcoat layer to correspond to the first and second photodiode regions.

Abstract: Embodiments relate to a vertical-type CMOS image sensor, a method of manufacturing the same, and a method of gettering the same, in which source and drain regions are expanded to improve grounding and gettering effects. In embodiments, the vertical-type CMOS image sensor may include a silicon substrate, a first photodiode formed in a prescribed part of the silicon substrate, a first epitaxial layer formed on the silicon substrate, a second photodiode formed on the first epitaxial layer to overlap the first photodiode, a second epitaxial layer formed on the first epitaxial layer, a third photodiode formed on the second epitaxial layer to overlap the second photodiode, and first to third grounded dummy moats formed by implanting impurities into uniform parts on the silicon substrate, the first epitaxial layer, and the second epitaxial layer.

Abstract: A CMOS image sensor is provided. The CMOS image sensor includes: a photodiode region formed in an active region of a substrate; a transistor formed on a transistor region of the active region of the substrate; a low-concentration diffusion region formed on the photodiode region while being spaced apart from a device isolation region of the substrate; a high-concentration diffusion region formed in the low-concentration diffusion region; and a floating diffusion region formed in a drain region of the transistor.

Abstract: Disclosed are a CMOS image sensor and a method for manufacturing the same. The CMOS image sensor includes a photodiode area and a floating diffusion area formed on a semiconductor substrate, a transistor formed on the semiconductor substrate between the photodiode area and the floating diffusion area, an isolation layer formed below the transistor, and a channel area formed between the transistor and the isolation layer.

Abstract: A method for manufacturing a CMOS image sensor is provided. The method includes: forming a photodiode on a semiconductor sustrate; forming a color filter layer on the photodiode; forming a planar layer on the color filter layer; forming a first microlens on the planar layer; and forming a second microlens on the first microlens. According to the preferred embodiment, a reflow process can be avoided in the forming of the microlenses.

Abstract: A CMOS image sensor includes a photodiode, and a plurality of transistors for transferring charges accumulated at the photodiode to one column line, wherein at least one transistor among the plurality of transistors has a source region wider than a drain region, for increasing a driving current.

Abstract: A pixel which may prevent the voltage of a floating diffusion region of the pixel from being outside a desired or predetermined driving voltage range by adjusting the equivalent capacitance of the floating diffusion region may be provided. The pixel may include a photodiode which may convert light energy into photocarriers, a transfer transistor which may transfer the photocarriers accumulated in the photodiode to a floating diffusion region, a select transistor which may transmit a data signal to the exterior in response to a selection control signal, the transmitted data signal having a voltage which may vary according to the voltage of the floating diffusion region, and/or at least one capacitor which may be connected between the floating diffusion region and the select transistor and which may adjust the equivalent capacitance of the floating diffusion region.

Abstract: A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Abstract: A semiconductor device includes an active region including a surface region and a first recess formed below the surface region, the active region extending along a first direction; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the active region along a second direction orthogonal to the first direction; a second recess formed in the device isolation structure to receive a given portion of the gate line into the second recess; a first junction region formed in the active region beneath the first recess and on a first side of the gate line; and a second junction region formed on a second side of the gate line and above the first junction region, wherein the first and second junction regions define a vertical-type channel that extends along lateral and vertical directions.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A dielectric layer for electronic devices is disclosed herein. The dielectric layer comprises inorganic nanoparticles dispersed in a polymer selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. The layer improves the carrier mobility and current on/off ratio of an electronic device incorporating it, especially a thin film transistor.

Abstract: A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-volatile memory transistor can be formed from this basic structure by adding a high-K dielectric constant film with an embedded metal nano-dot layer between the tunnel insulator and the gate stack.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.