Patents Issued in June 28, 2007
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Publication number: 20070145456Abstract: A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below the control gate line. An island conductive line is formed between the first and second floating gates and within the isolation films. The island conductive line extends along the first direction and is configured to receive a voltage in order to prevent interference between the first and second floating gates.Type: ApplicationFiled: June 30, 2006Publication date: June 28, 2007Applicant: Hynix Semiconductor Inc.Inventor: Keun Lee
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Publication number: 20070145457Abstract: A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.Type: ApplicationFiled: November 22, 2006Publication date: June 28, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shieh Huang, Jiun Chen, Lien Tsai
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Publication number: 20070145458Abstract: A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating-film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate-electrode, generated due to the floating gate electrode.Type: ApplicationFiled: December 20, 2006Publication date: June 28, 2007Inventor: Yoshinobu Asami
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Publication number: 20070145459Abstract: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.Type: ApplicationFiled: December 22, 2006Publication date: June 28, 2007Inventors: Geun-sook Park, Sang-bae Yi, Soo-cheol Lee, Ho-ik Hwang, Tae-jung Lee
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Publication number: 20070145460Abstract: Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside the trench and protruding upward from the substrate, a charge storage layer between the control gate and an inner wall of the trench, and a pair of insulating spacers formed on opposite sidewalls of the control gate with the charge storage layer therebetween. Here, the charge storage layer has an oxide-nitride-oxide (ONO) structure. Further, the depth of the trench from the surface of the substrate is greater than that of each of the source and drain diffusion regions.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Sang Lee
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Publication number: 20070145461Abstract: Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.Type: ApplicationFiled: December 27, 2006Publication date: June 28, 2007Inventor: Chang Hua Han
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Publication number: 20070145462Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.Type: ApplicationFiled: February 20, 2007Publication date: June 28, 2007Inventors: Jerome Eldridge, Kie Ahn, Leonard Forbes
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Publication number: 20070145463Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.Type: ApplicationFiled: February 21, 2007Publication date: June 28, 2007Inventor: Kristy Campbell
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Publication number: 20070145464Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.Type: ApplicationFiled: February 21, 2007Publication date: June 28, 2007Inventors: Thomas Voshell, Lucien Bissey, Kevin Duesman
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Publication number: 20070145465Abstract: Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.Type: ApplicationFiled: December 22, 2005Publication date: June 28, 2007Inventors: Tzyh-Cheang Lee, Fu-Liang Yang, Jiunn-Ren Hwang, Tsung-Lin Lee
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Publication number: 20070145466Abstract: A flash memory device and a method of manufacturing the same, wherein a silicon layer having a micro grain is formed between a tunnel oxide layer and a floating gate using a hemi-spherical grain (HSG) method, thereby preventing the dopant of the floating gate from being diffused into the tunnel oxide layer. According to one embodiment, the flash memory device includes isolation structures formed in predetermined regions of a semiconductor substrate, for defining an active region and a field region, a tunnel oxide layer formed on the semiconductor substrate of the active region, and a floating gate formed in a predetermined region on the active region to overlap with a part of the isolation structure, an underlying given portion and the remaining portions of the floating gate having different grain sizes.Type: ApplicationFiled: August 3, 2006Publication date: June 28, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Young Ho Yang
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Publication number: 20070145467Abstract: An EEPROM includes a semiconductor substrate and a device isolation region defining first, second and third active regions in the semiconductor substrate. The EEPROM also includes at least one first insulation region in at least one first trench in the first active region. A floating gate insulation layer is disposed on the at least one first insulation region and the first, second and third active regions and a floating gate conduction layer is disposed on the floating gate insulation layer. Impurity-containing regions may be disposed in each of the first, second and third active regions at respective sides of the floating gate conduction layer. The floating gate insulation layer may include at least one thinned portion proximate the at least one first insulation region, which may aid Fowler-Nordheim tunneling at this site.Type: ApplicationFiled: October 3, 2006Publication date: June 28, 2007Inventors: Geun-sook Park, Byung-sun Kim, Sang-bae Yi, Ho-ik Hwang, Myung-hee Kim, Hye-young Park
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Publication number: 20070145468Abstract: Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Amlan Majumdar, Suman Datta, Been-Yih Jin, Mark Doczy, Robert Chau
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Publication number: 20070145469Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.Type: ApplicationFiled: December 27, 2006Publication date: June 28, 2007Inventor: Chul Jin Yoon
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Publication number: 20070145470Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.Type: ApplicationFiled: February 22, 2007Publication date: June 28, 2007Inventor: Yoshio Ozawa
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Publication number: 20070145471Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.Type: ApplicationFiled: February 22, 2007Publication date: June 28, 2007Inventor: Yoshio Ozawa
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Publication number: 20070145472Abstract: A flash memory cell may include a tunnel oxide layer over a semiconductor substrate with a first tunnel having a first thickness and a second tunnel having a second thickness. A charge storage layer may be formed over a tunnel oxide layer, an insulating layer may be formed over a charge storage layer, and/or a control gate may be formed over an insulating layer. A control gate may be supplied with driving power. A first thickness of a first tunnel may be less than a second thickness of a second tunnel.Type: ApplicationFiled: December 19, 2006Publication date: June 28, 2007Inventor: Cheol Kwak
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Publication number: 20070145473Abstract: A semiconductor device with enhanced heat releasability and low-cost manufacturability is disclosed. This device has a substrate with an electronic circuit disposed on a first principal surface, a semiconductor element which is provided at the first surface of the substrate and electrically connected by wire bonding to the electronic circuit, a metallic core layer which is provided in the substrate and electrically connected to the semiconductor element, a plurality of conductive bumps provided on a second principal surface opposite to the first surface of the substrate, a thermal hardenable sealing resin for sealing at least the semiconductor element and the first surface side of the substrate, and a metal plate provided at the second surface for being electrically connected to the metal core layer. An electronic control module using the device is also disclosed.Type: ApplicationFiled: December 8, 2006Publication date: June 28, 2007Applicant: Hitachi, Ltd.Inventors: Masahiko Asano, Yasuo Akutsu, Masahide Harada, Kaoru Uchiyama, Shinichi Fujiwara, Isamu Yoshida
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Publication number: 20070145474Abstract: A vertical-gate MOS transistor is integrated in a semiconductor chip of a first conductivity type having a main surface, and includes an insulated trench gate extending into the semiconductor chip from the main surface to a gate depth. The trench gate includes a control gate and an insulation layer for insulating the control gate from the semiconductor chip, source and drain regions of a second conductivity type formed in the semiconductor chip, at least one of the source and drain regions being adjacent to the insulation layer and extending into the semiconductor chip from the main surface to a region depth lower than the gate depth. The insulation layer includes an outer portion, extending into the semiconductor chip to a protection depth less than the gate depth, and an inner portion, the outer portion having first thickness and the internal portion having a second thickness less than the first thickness.Type: ApplicationFiled: November 9, 2006Publication date: June 28, 2007Applicant: STMICROELECTRONICS S.R.L.Inventors: Marco Annese, Fabrizio Toia, Pietro Montanini
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Publication number: 20070145475Abstract: A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions. The bottom of each trench is over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.Type: ApplicationFiled: December 21, 2006Publication date: June 28, 2007Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventor: Koh YOSHIKAWA
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Publication number: 20070145476Abstract: Embodiments relate to a semiconductor device. In embodiments, a semiconductor device may include a semiconductor substrate having isolation layers and a well region, a gate electrode formed within a trench having a predetermined depth in the well region, source/drain regions formed at both sides of the trench, respectively, an interlayer dielectric layer formed on the semiconductor substrate to have predetermined contact holes, and metal interconnections formed within the contact holes, respectively.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Jae Hwan Shim
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Publication number: 20070145477Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.Type: ApplicationFiled: February 12, 2007Publication date: June 28, 2007Inventors: Tae-Jung Lee, Soo-Cheol Lee, Dong-Ryul Chang
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Publication number: 20070145478Abstract: A high voltage semiconductor device includes a semiconductor substrate having a high voltage well region; a device isolation film to define an active region of the semiconductor substrate; a drift region formed at an outer periphery of the device isolation film; an impurities region formed under the bottom of the drift region to cover the device isolation film; a gate electrode formed in a predetermined region of the active region; and a source/drain region formed in the drift region on either side of the gate electrode.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Choul Ko
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Publication number: 20070145479Abstract: A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and the first width is equal to a product of the second impurity concentration and the second width. The first width is equal to or smaller than 4.5 ?m. The first impurity concentration is lower than a predetermined concentration satisfying a RESURF condition. A ratio between on-state resistances of the device at 27° C. and at 150° C. is smaller than 1.8.Type: ApplicationFiled: December 27, 2006Publication date: June 28, 2007Applicant: DENSO CORPORATIONInventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Yoshiyuki Hattori, Kyoko Okada
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Publication number: 20070145480Abstract: A method of forming an electrode of a semiconductor device is provided. A material layer comprising an organo-metallic compound is first formed on a substrate. Thereafter, an electrode is formed by irradiating the material layer through utilizing the heating property of laser. Next, the material layer is patterned by utilizing the photochemical or heating properties of laser using a laser. Because laser irradiation is substituted the traditional heating way, it can reduce process temperature. Furthermore, because the laser is used for patterning the material layer to form the electrode, therefore an electrode pattern with a greater precision may be obtained compared to that obtained by using the photolithography process.Type: ApplicationFiled: April 7, 2006Publication date: June 28, 2007Inventors: Hsiang-Yuan Cheng, Yi-Kai Wang, Tarng-Shiang Hu
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Publication number: 20070145481Abstract: A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.Type: ApplicationFiled: December 22, 2005Publication date: June 28, 2007Inventors: Armin Tilke, Jiang Yan, Matthias Hierlemann
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Publication number: 20070145482Abstract: A liquid crystal display device includes a substrate, a gate line and a data line intersected with each other to define a pixel region on the substrate, a thin film transistor having a nanowire channel layer in an intersection region of the gate line and the data line, and a pixel electrode formed in the pixel region.Type: ApplicationFiled: May 17, 2006Publication date: June 28, 2007Inventors: Mi Park, Gee Chae
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Publication number: 20070145483Abstract: A highly-integrated, high-performance semiconductor device with a simplest possible structure can be provided.Type: ApplicationFiled: December 19, 2006Publication date: June 28, 2007Inventor: Mizuki Ono
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Publication number: 20070145484Abstract: A regulator circuit including an output-stage transistor for supplying a current to an external circuit has an electrostatic protection transistor formed in parallel with the output-stage transistor. The base of the electrostatic protection transistor is connected to, for example, the base of the output-stage transistor, or alternatively to a ground line or to the emitter of the electrostatic protection transistor itself.Type: ApplicationFiled: November 2, 2006Publication date: June 28, 2007Inventors: Makoto Hosokawa, Toshihiko Fukushima, Naoki Fukunaga
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Publication number: 20070145485Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.Type: ApplicationFiled: March 2, 2007Publication date: June 28, 2007Inventors: Se-Hoon Oh, Jung-Hee Chung, Jae-Hyoung Choi, Jeong-Sik Choi, Sung-Tae Kim, Cha-Young Yoo
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Publication number: 20070145486Abstract: A semiconductor memory device has a memory cell and a peripheral transistor formed on a substrate. The memory cell is provided with a select transistor formed on the substrate and a capacitor connected to the select transistor. A diffusion layer of the peripheral transistor is connected to an upper layer interconnection through a first contact. Gate electrodes of the peripheral transistor and the select transistor are connected to upper layer interconnections through respective of second contacts. A diffusion layer of the select transistor is connected to any of a bit line and the capacitor through a third contact. Silicide is selectively formed only in the first contact out of the first contact, the second contacts and the third contact.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Eiji Hasunuma
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Publication number: 20070145487Abstract: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Jack Kavalieros, Justin Brask, Suman Datta, Brian Doyle, Robert Chau
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Publication number: 20070145488Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.Type: ApplicationFiled: August 1, 2006Publication date: June 28, 2007Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
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Publication number: 20070145489Abstract: A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Der-Chyang Yeh, Chuan-Ying Lee, Victor Yeh
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Publication number: 20070145490Abstract: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device. In embodiments, a transistor including the gate electrode and a source/drain may be formed between isolation layers and a contact may be connected to the source/drain. A barrier layer may be formed at a boundary between the isolation layer and the source/drain and may physically isolate the isolation layer from the source/drain.Type: ApplicationFiled: December 12, 2006Publication date: June 28, 2007Inventor: Jong Bok Lee
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Publication number: 20070145491Abstract: A semiconductor device includes a substrate in which at least one transistor is formed; an interlayer insulating layer formed over the entire surface of the substrate including the transistor, the interlayer insulating layer having contact holes to expose the electrodes of the transistor; and contact insulating layers formed over the internal walls of the contact holes.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Young Wook Shin
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Publication number: 20070145492Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and a second barrier layer may be formed. The first barrier layer and the second barrier layer may be annealed to form a silicide and combine the first barrier layer and the second barrier layer to form a metal compound.Type: ApplicationFiled: December 8, 2006Publication date: June 28, 2007Inventor: Chee-Hong Choi
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Publication number: 20070145493Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.Type: ApplicationFiled: December 7, 2006Publication date: June 28, 2007Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
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Publication number: 20070145494Abstract: Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher. A PSG (HDP-PSG: Phospho Silicate Glass) film containing a conductive impurity is formed as an interlayer insulating film for burying the gate electrode structures at film-formation temperature of 650° C. or lower by a high-density plasma CVD (HDP-CVD) method.Type: ApplicationFiled: February 22, 2007Publication date: June 28, 2007Applicant: FUJITSU LIMITEDInventor: Hideaki Ohashi
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Publication number: 20070145495Abstract: A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Giuseppe Curello, Sivakumar Mudanai, Nick Lindert, Leonard Pipes, M. Shaheed, Sunit Tyagi
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Publication number: 20070145496Abstract: according to embodiments, a semiconductor device may include a semiconductor substrate in which source and drain regions may be formed, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, a first sidewall insulating layer formed on the side of the gate electrode, a third sidewall insulating layer formed on the side of the first sidewall insulating layer, and a second sidewall insulating layer formed between the first sidewall insulating layer and the third sidewall insulating layer.Type: ApplicationFiled: December 12, 2006Publication date: June 28, 2007Inventor: Eun Jong Shin
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Publication number: 20070145497Abstract: Embodiments relate to a semiconductor device including an impurity region formed in the semiconductor device; an insulating layer formed on the impurity region; and a contact formed to have a certain step difference in the impurity region through the insulating layer.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Young Suk Ko
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Publication number: 20070145498Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Matthew Metz, Mark Doczy, Justin Brask, Robert Chau
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Publication number: 20070145499Abstract: A photovoltaic ultraviolet sensor comprises a zinc oxide single crystal substrate. On the +c face of the zinc oxide single crystal substrate, an ultraviolet receiver is formed. The exemplary ultraviolet receiver includes a Schottky electrode which, when receiving ultraviolet rays, produces a voltage in cooperation with the zinc oxide single crystal substrate. The ultraviolet sensor does not have any sensitivity to the visible rays. The ultraviolet sensor has a relatively fast response of several microseconds.Type: ApplicationFiled: March 23, 2006Publication date: June 28, 2007Applicants: IWATE INFORMATION SYSTEM, CORP., IWATE PREFECTUAL GOVERNMENT, INCORPORATED NATIONAL UNIVERSITY IWATE UNIVERSITYInventors: Mayo Sugibuchi, Kohsuke Takahashi, Shunsuke Goto, Yasube Kashiwaba, Haruyuki Endo, Tatsuo Hasegawa, Fukunori Izumida, Eriko Ohshima
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Publication number: 20070145500Abstract: A CMOS image sensor capable of improving characteristics of the image sensor by preventing damage to a photodiode region and a method for manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate on which a device isolation region and an active region are defined; a photodiode region formed at the active region; a conductive plug formed on the photodiode region for connecting the photodiode region to a metal wiring; and a transistor formed enclosing the conductive plug.Type: ApplicationFiled: December 19, 2006Publication date: June 28, 2007Inventor: Chang Han
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Publication number: 20070145501Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.Type: ApplicationFiled: March 8, 2007Publication date: June 28, 2007Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe D'Arrigo, Rosario Spinella
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Publication number: 20070145502Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.Type: ApplicationFiled: February 26, 2007Publication date: June 28, 2007Inventors: Dmitri Nikonov, George Bourianoff
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Publication number: 20070145503Abstract: An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.Type: ApplicationFiled: February 16, 2007Publication date: June 28, 2007Inventor: Bart Dierickx
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Publication number: 20070145504Abstract: A CMOS image sensor is provided. The CMOS image sensor can include: a plurality of photodiodes formed on a semiconductor substrate; an interlayer dielectric layer formed on an entire surface of the semiconductor substrate having the plurality of photodiodes; color filter layers including multi-layered blue color filter layers formed on the interlayer dielectric layer corresponding to respective photodiodes of the plurality of photodiodes; a planarization layer formed on the semiconductor substrate having the color filter layers; and microlenses formed on the planarization layer.Type: ApplicationFiled: December 26, 2006Publication date: June 28, 2007Inventor: Duk Kim
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Publication number: 20070145505Abstract: Disclosed are an image sensor and a method for manufacturing the same, capable of increasing a light absorbing coefficient by forming a rough surface on a photodiode. The image sensor includes a semiconductor substrate with a plurality of photodiodes thereon having rough upper surfaces, a dielectric layer on the semiconductor substrate, a color filter layer on the dielectric layer, a planarization layer on an entire surface of the semiconductor substrate including the color filter layer, and a plurality of micro-lenses formed on the planarization layer to correspond to the color filter layer.Type: ApplicationFiled: December 27, 2006Publication date: June 28, 2007Inventors: Sang Kim, Jae Han