Abstract: An assembly of image-sensing chip and circuit boardwith inward wire bonding, including an image-sensing chip, a circuit board and a glass board. The circuit board is formed with a window and several wire bonding slots. An image-sensing chip is adhered to the circuit board. A wire bonding area is defined between the periphery of the image-sensing area and the bond pads of the image-sensing chip. By means of the wire bonding area, wires are inward bonded, that is, toward the image-sensing area from the bond pads through the wire bonding slots to the electric contacts of the circuit board. The glass board is disposed on the circuit board to block the window corresponding to the image-sensing area. Glue material is airtight filled around the image-sensing chip and the glass board and in the wire bonding slots of the circuit board for ensuring electric connection between the bond pads and the electric contacts.

Abstract: The present invention provides methods and apparatus for deposition of contact layers for Group IBIIIAVIA solar cells using electrodeposition and/or electroless deposition approaches, and solar cells that result therefrom. In one aspect of the invention, the solar cell that results includes a substrate, a stacked contact layer that includes a bottom film coated on a surface of the substrate and a top film formed by electroplating over the bottom film, wherein the top film comprises at least one of Ru, Ir and Os. A Group IBIIIAVIA compound film formed over the top film. In another aspect of the invention, there is provided a method of depositing a stacked layer of a plurality of films in a plurality of sequentially disposed depositing units onto a continuously moving roll-to-roll sheet, preferably using electroplating of a stacked contact layer.

Abstract: A CMOS image sensor and a fabrication method thereof are provided. The CMOS image sensor includes a semiconductor substrate having an active area and an isolation area; a photodiode area and a transistor area defined on the active area; a plurality of semiconductor patterns formed on the photodiode area; a transistor formed on the transistor area; a first conductive type first diffusion region formed on the photodiode area; a first conductive type second diffusion region formed on the transistor area; and a second conductive type third diffusion region formed on the first diffusion region.

Abstract: A CMOS image sensor and a fabrication method thereof is provided.

Abstract: A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region formed on the photodiode area at a first side of the gate electrode; a high-density second conductive the diffusion region formed on the transistor area at a second side of the gate electrode; an insulating layer formed on the semiconductor substrate at both sides of the gate electrode with a thickness less than a thickness of the gate electrode, but greater than a thickness of a gate insulating layer; and insulating layer sidewalls formed on the insulating layer at both sides of the gate electrode.

Abstract: A CMOS image sensor is provided. The CMOS image sensor includes: a semiconductor substrate having a photodiode region and a floating diffusion region defined thereon; a gate electrode formed inside the photodiode region of the semiconductor substrate; a low concentration impurity region formed on the photodiode region at one side of the gate electrode; and a high concentration impurity region formed at the other side of the gate electrode, including on the floating diffusion region.

Abstract: A photogate structure having increased quantum efficiency, especially for low wavelength light such as blue light. The photogate is formed of a thin conductive layer, such as a layer of doped polysilicon. A nitride insulating cap is formed over the conductive layer. The nitride layer reduces the reflections at the conductor/insulator interface. A pixel cell incorporating the photogate structure also has a buried accumulation region beneath the photogate. A method of fabricating the photogate structure is also disclosed.

Abstract: A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm?1 is less than both the absorbance of infrared radiation at the wave number of 830 cm?1 and the absorbance of infrared radiation at the wave number of 900 cm?1 when the insulating film to which an electric field has never been applied is measured by means of Fourier Transform Infrared Spectroscopy at room temperature.

Abstract: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.

Abstract: An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.

Abstract: Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconductor substrate may have a trench in which a device isolation layer is to be formed. The photodiode may be formed in an active region of the semiconductor substrate, and the first conduction type impurity region may be formed in sidewalls of the trench. The first insulating layer may be formed inside the trench, and a conduction layer may be formed inside the trench and doped with second conduction type impurities. A second insulating layer may be formed inside the trench.

Abstract: A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

Abstract: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the through holes. Bottom surfaces of the bottomed cylindrical portions of the wiring lines serve as connection pad portions.

Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.

Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.

Abstract: embodiments relate to a semiconductor device that may include a continuously formed pad oxide layer and a field oxide layer. The device may include a semiconductor substrate having a trench, an insulating material formed in the trench, a pad oxide layer formed at the active region of the semiconductor substrate and a field oxide layer formed on the insulating material.

Abstract: A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stopper film formed on the gate electrode and first element region to cover the first element region and giving a tensile stress, a second stopper film formed on the gate electrode and second element region to cover the second element region and giving a compressive stress, and a contact connected to the gate electrode on the element isolation insulating film. The first and second stopper films overlap each other at least partially on the element isolation insulating film, and a total thickness of the first and second stopper films on the gate electrode on the element isolation insulating film is smaller than a total thickness outside the gate electrode.

Abstract: Method for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A variable capacitors may employ stops between a moveable electrode and a fixed electrode to reduce and/or prevent electrical shorting between the moveable and fixed electrode. A capacitor may employ a split bottom electrode structure to removing a suspension portion of a moveable top electrode from an RF part of a circuit.

Abstract: In an FPGA of a semiconductor device and a method of forming the FPGA, a first pattern having a voltage selectable conductivity is formed to connect first vias of the semiconductor device in parallel.

Abstract: A metal-insulator-insulator (MIM) capacitor structure is provided. The MIM capacitor includes a top electrode, a bottom electrode and a dielectric layer. The dielectric layer is disposed between the top electrode and the bottom electrode. The main feature for this kind of MIM capacitor is that the bottom electrode includes a conductive layer and a metal nitride with multi-layered structure. The metal nitride with multi-layered structure is disposed between the conductive layer and the dielectric layer. The nitrogen content in the metal nitride with multi-layered structure gradually increases toward the dielectric layer and the metal nitride belongs to the amorphous type. Due to the presence of the metal nitride, the dielectric layer is prevented from crystallization, thereby reducing the current leakage of the MIM capacitor.

Abstract: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer on the insulating layer; an interlayer dielectric layer having a via hole on the lower metal interconnection; and a plug in the via hole.

Abstract: A semiconductor device has an electrode pad, a capacitor and a substrate. The substrate has a given area on which the electrode pad and the capacitor are arranged. The electrode pad and the capacitor are arranged on the substrate so that each of at least two sides of the capacitor and each of at least two sides of the electrode pad is adjacent to each other at a given interval. The capacitor has a connecting side that connects the two sides of the capacitor and faces to the electrode pad. Outside angles of the capacitor formed by the connecting side and the two sides of the capacitor are more than 90 degrees.

Abstract: A power dissipation-optimized high-frequency coupling capacitor is provided for a rectifier circuit as well as a power dissipation-optimized high-frequency rectifier circuit. The elements of the rectifier stages of the inventive high-frequency rectifier circuit are disposed in an optimized manner regarding space such that the coupling capacitors are connected directly to the contact area for the antenna terminal and are arranged around the contact area while taking into account the connecting wires.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.

Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the second conductive ions, a base area in the third well and doped with first conductive ions, an emitter area in the third well and doped with the second conductive ions, an emitter electrode on the emitter area, a first contact plug in contact with the emitter electrode, a second contact plug in contact with the base area, a collector area in the second well and doped with the second conductive ions, and a third contact plug in contact with the collector area.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: A reference voltage generating circuit is disclosed. The reference voltage generating circuit includes a collector layer where collectors of transistors are disposed, a base layer where bases of the transistors are disposed and which base layer is formed on the surface of the collector layer, and plural emitter layers in each of which an emitter of the transistor is disposed and which emitter layers are formed on the surface of the base layer that is common to the emitter layers.

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device that may be capable of improving a step coverage of main chip and scribe lane regions during a formation of an interlayer dielectric are provided. In embodiments, the semiconductor device may include metal layers formed on a substrate including a main chip region and a scribe lane region, respectively, an interlayer dielectric formed on the substrate including the metal layers, a step coverage improving layer formed on an interlayer dielectric of the scribe lane region, a via hole inside the step coverage improving layer and the interlayer dielectric, and a via plug formed by filling the via hole with a metal.

Abstract: A CMP apparatus has a CMP unit for polishing a dielectric layer, a thickness monitoring unit for monitoring a thickness index of the polished dielectric layer, and a thickness correcting unit for further reducing the thickness of the polished dielectric layer in accordance with the thickness index by etching. The CMP unit, the thickness monitoring unit, and the thickness correcting unit are in-situ installed.

Abstract: A method and system for fabricating an electromagnetic radiation shield for an electronics package is disclosed. The electronics package includes a substrate, at least one ground contact feature, and a protective layer. The electronics package is physically coupled to at least one additional electronics package through at least the substrate. The method and system include exposing a portion of the ground contact feature(s) by removing a portion of the electronics package above the ground contact feature(s). The exposing step forms at least one trench above the ground contact feature(s). The method and system also include depositing an electromagnetic radiation shield that substantially covers the electronics package, fills the trench(es), and is electrically connected to the ground contact feature(s).

Abstract: A semiconductor device includes: first and second metal electrodes having inner surfaces facing each other; a semiconductor element sandwiched between the electrodes; and first and second insulation substrates disposed on the electrode and opposite to the semiconductor element, respectively. Each of the insulation substrates is made of ceramics. At least one of the electrodes includes a plurality of layers stacked in a direction parallel to a stacking direction. One layer disposed on a semiconductor element side has a thermal expansion coefficient, which is higher than that of another layer disposed on an insulation substrate side.

Abstract: Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.

Abstract: An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making an electrode structure by providing a substrate; forming a plurality of electrodes on the substrate; growing at least one nano-wire from the edge of a first electrode; and connecting the at least one nano-wire to the edge of a second electrode is also disclosed.

Abstract: A method including modifying a characteristic impedance along a length of a plating bar of a substrate package. An apparatus including a package substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar comprises portions having different characteristic impedance along its length. A system including a computing device including a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar comprises portions having different characteristic impedance along its length.

Abstract: A method for producing a semiconductor product. Semiconductor product components are formed in a semiconductor product region of the substrate. A layer made of low-k material is subsequently formed on the substrate. Electrically conductive interconnects are formed in and/or on the layer made of low-k material. The layer of low-k material is provided in a wiring plane of the semiconductor product region for the electrical insulation of the interconnects from one another. A grid cap region of the substrate is subjected to a spacially delimited treatment such that the value of the dielectric constant is increased in the crossover region. Accordingly, an interconnect to interconnect capacitance is formed as grid cap capacitance from the interconnects arranged in the crossover region and the material and increased value of dielectric constant. Further, the dielectric constant of the low-k material remains unchanged in the semiconductor product region.

Abstract: An integrated circuit is disclosed that includes at least one integrated transmission line for the transmission of a high-frequency differential signal with a number of at least two series-connected line arrangements, each of which has a differential input, a differential output, a first trace, connected to a first terminal of the differential input and a first terminal of the differential output, and a second trace, connected to a second terminal of the differential input and a second terminal of the differential output.

Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.

Abstract: A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface (14) and the plurality of electrical contacts (24) being exposed on opposing sides of the package (10). Features (30) are formed into electrically inactive portions of the integrated circuit die (12) to seal moisture paths and relieve packaging stress. The features (30) are formed by forming a trough (54) partially through the backside (56) of the wafer (40) in alignment with a saw street (48), the trough (54) having a first width; and forming a channel (62) extending from the trough (54) to the electrically active face (42) to thereby singulate the integrated circuit device member, the channel (62) having a second width that is less than the first width.

Abstract: A stack-type semiconductor package includes a first semiconductor package upon which a second semiconductor package is stacked. A layer of a hardened, insulative material, e.g., a no-flow underfill (NUF) material, is disposed between, and mechanically couples the stacked first and second semiconductor packages. The NUF layer covers portions of the first semiconductor package, e.g., the semiconductor die and the substrate of the first semiconductor package, and solder balls of the second semiconductor package that are fused to the substrate of the first semiconductor package. The NUF material is applied onto the semiconductor die and substrate of the first semiconductor package before the second semiconductor package is stacked on the first semiconductor package, and substantially cures after the solder balls of the second semiconductor package are fused to the substrate of the first semiconductor package.

Abstract: A semiconductor device includes an integrated circuit die, wherein a layer of photoresist is permanently disposed on and permanently hermetically seals an active circuit area of a top surface of the inductor die. In one embodiment, the semiconductor device includes a lead frame including a conductive pad and a plurality of conductive leads, wherein the die is attached to the conductive pad, and wherein bonding wires bond the leads of the lead frame to bonding pads of the die, and wherein the die and bonding wires are encapsulated in package material. In another embodiment, solder bumps are provided on the bonding pads, and the die is inverted and the solder bumps are attached to corresponding conductors on a printed circuit board.

Abstract: A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts which extend above a surrounding solder mask layer to facilitate engagement with a test fixture. The posts are immersed within solder joints when the structure is bonded to a circuit panel.

Abstract: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12.

Abstract: A semiconductor component includes at least one semiconductor chip arranged on a mounting substrate and connected thereto via bonding wires. For effective dissipation of heat, a solderable interlayer is arranged on the active upper side of the semiconductor chip and a heat sink is soldered onto the solderable interlayer. A method is also described for producing a semiconductor component with a solderable interlayer disposed on an active upper side of a semiconductor chip and with a heat sink soldered to the solderable interlayer.

Abstract: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the outer peripheral portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.

Abstract: A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

Abstract: A semiconductor structure includes: a carrier plate; a thermosensitive adhesive coupled to a top surface of the carrier plate, which is removable from the carrier plate at a predetermined, defined temperature at which the thermosensitive adhesive loses its adhesive action; semiconductor chips having active top surfaces and back surfaces, where the active top surfaces include contact surfaces disposed on the thermosensitive adhesive; and a plastic embedding compound on the carrier plate, in which the semiconductor chips are embedded.