Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract: The present invention discloses a method for fabricating a semiconductor device, comprising: providing a translucent portion; forming a covering layer comprised of one or more metals on the translucent portion by vapor deposition; providing kinetic energy to the covering layer for forming a periodic mask; forming a periodic structure on the translucent portion by using the periodic mask.

Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.

Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.

Abstract: A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a particular embodiment, the laterally adjacent traces provide shunt capacitance to compensate for an inductance in a signal path to the chip which includes the signal-bearing conductive trace. In a variation thereof, a transmission line or waveguide is provided which includes the signal-bearing conductive trace and reference trace. In further variations, transmission lines are provided which include one or more metal layers of a package element, separated from each other by a thickness of a dielectric element included in the package element or the air gap between the package and a circuit panel.

Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.

Abstract: A method and system for fabricating a interconnect substrate for a multi-component package is disclosed. The multi-component package includes at least one die and a package substrate. The method and system include providing an insulating base and providing at least one conductive layer. The at least one conductive layer provides interconnects for at least one discrete component. The interconnect substrate is configured to be mounted on the at least one die and to have the at least one discrete component mounted on the interconnect substrate.

Abstract: A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die and a second integrated circuit package substrate defining a second plurality of openings, and a third substrate comprising a plurality of conductive projections. Each of the plurality of conductive projections may be disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings.

Abstract: A method is provided of forming a capped chip which includes a conductive interconnect exposed through an opening in the cap. A cap having openings extending between outer and inner surfaces is aligned and joined to a chip. A mass of fusible conductive material is positioned through a first such opening onto a first such bond pad of the chip. The positioned mass is heated to bond the mass to the first bond pad. The steps of positioning and heating the mass form at least a portion of a conductive interconnect extending from the first bond pad at least partially through the first opening.

Abstract: A semiconductor chip according to the present invention is a semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of the surface thereof, and having the surface thereof opposed to and joined to the surface of a solid-state device.

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract: Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.

Abstract: The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers (8) to (12) are adapted so that photo-lithographic processing is implemented to a first insulating layer (22) formed by photosensitive insulating resin material to form via hole grooves (25), and photo-lithographic processing is implemented to a second insulating layer (23) formed by photosensitive insulating resin material on the first insulating layer (22) to form wiring grooves (27).

Abstract: An image sensor module with passive component includes a flexible print circuit board having an upper surface, which is formed with a plurality of electrically circuits, and a lower surface. At least a passive component is arranged on the upper surface of the flexible circuit board. A substrate has a first surface, a second surface, and a penetrated hole. The second surface of the substrate is mounted on the upper surface of the flexible circuit board, so that the passive component is located within the penetrated hole. A chip is mounted on the first surface of the substrate, and is located onto the penetrated hole of the substrate. A plurality of wires are electrically connected the chip to the substrate. A lens holder is mounted on first surface of the substrate, and is formed with an internal thread. And a lens barrel is formed with an external thread screwed on the internal thread of the lens holder, the lens barrel formed with an opening, an aspheric lens, and an infrared filter.

Abstract: A semiconductor device has an improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract: A semiconductor package structure with a heat dissipating stiffener and method of fabricating the same are provided. In one embodiment, the package structure comprises a substrate having a front side and a back side; a semiconductor chip mounted on the front surface of the substrate; a thermally-conductive stiffener mounted over the front surface of the substrate and surrounding the chip, the stiffener having a first portion and a second portion, wherein the first portion is wider than the second portion so as to allow for easy egress of a dispenser into a gap between the chip and the substrate; an underfill layer filled and cured in the gap; and a plurality of solder balls mounted on the back surface of the substrate.

Abstract: A heat dissipation device (1) includes a heat sink (10), a fan (20), and a cooling member (30). The heat sink includes a base, a plurality of fins extending from the base and at least one heat pipe thermally connecting the base and the fins. The cooling member is provided with a fin assembly thereon and includes a cold surface attached to one side of the fins and a condensing portion of the at least one heat pipe to make the one side of the fins and the condensing portion have a lower temperature.

Abstract: A semiconductor device (1) has a semiconductor component (2), a first electrode (6) and a control electrode (7) being arranged on the top side (4). The semiconductor device (1) furthermore has a circuit carrier (3) having a chip island (9) and a plurality of flat conductors (10). The rear side (5) of the semiconductor component (2) is mounted on the chip island (9). The first electrode (6) is electrically connected to a first flat conductor (13) via a first contact clip (16) and the control electrode (7) is electrically connected to a control flat conductor (14) via the second contact clip (19). The upper surface (33) of the first contact clip (16) is at least partly arranged in a plane which is further away from the top side (4) of the semiconductor component (2) than the entire upper surface (34) of the second contact clip (19).

Abstract: A method of making and a high performance reworkable heatsink and packaging structure with solder release layer are provided. A heatsink structure includes a heatsink base frame. A selected one of a heatpipe or a vapor chamber, and a plurality of parallel fins are soldered to the heatsink base frame. A solder release layer is applied to an outer surface of the heatsink base frame. The solder release layer has a lower melting temperature range than each solder used for securing the selected one of the heatpipe or the vapor chamber, and the plurality of parallel fins to the heatsink base frame. After the solder release layer is applied, the heatpipe or the vapor chamber is filled with a selected heat transfer media.

Abstract: A circuit board includes a substrate including electrode patterns formed thereon, first chip components mounted on the substrate and a second chip component mounted on a side of electrodes of the first chip components opposite from the substrate. The second chip component is bonded at one electrode to an electrode of the first chip component and is also bonded at the other electrode to an electrode of the first chip component. By stacking chip components in plural stages, it is possible to mount chip components with a high density on the substrate, thereby enabling reduction of the size of the circuit board.

Abstract: The power semiconductor circuit has a power semiconductor module (2) provided in the form of a flat module. In order to utilize the design possibilities resulting therefrom and to provide a power semiconductor circuit that has an automatable production and a particularly space-saving design, the flat module, with its substrate (11), is glued by a heat conducting adhesive (20) directly onto a heat conducting base plate (1) that acts as a cooling element (5).

Abstract: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Abstract: A multi-chip package sharing a temperature-compensated self-refresh (TCSR) signal and method thereof is disclosed. The multi-chip package may include a plurality of chips. At least one of the plurality of chips may generate a TCSR signal. A remainder of the plurality of chips may be configured to receive the TCSR signal. A pad may be commonly connected to the plurality of chips.

Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract: A control unit having a package in which at least a part of components of a control system controlling specified controlling objects is housed, wherein a pair of protrusions is provided on each of opposite side surfaces of the package, and supporting members which operate as a vibration proof material are provided on each of opposite side surfaces of the package, wherein the pair of protrusions provided each of side surfaces of the package is fitted into a corresponding pair of holes of the supporting members to mount the supporting members on each of opposite side surfaces, and wherein transmission of vibration from the mounting portion to the package is prevented by mounting the package on the mounting portion through the supporting members.

Abstract: A vertical power semiconductor component (1) having a top side (3) and a rear side (4) is provided. The top side (3) has at least one first electrode contact area (8) and at least one control electrode area (9) and the rear side (4) has a second electrode contact area (7). A first metallization (10) having a thickness a is arranged on the first electrode contact area (8). A second metallization (11) having a thickness b is arranged on the control electrode area (9). A third metallization (6) having a thickness c is arranged on the second electrode contact area (7). The thickness a of the first metallization (10) is at least 10 times thicker than the thickness b of the second metallization (11).

Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.

Abstract: The printed wiring board comprises, on at least one surface of an insulating film, a base metal layer and a conductive metal layer formed on the base metal layer, and is characterized in that in a section of the wiring board the bottom width of the conductive metal layer is smaller than the top width of the base metal layer. The circuit device comprises the printed wiring board and an electronic part mounted thereon. The process for producing a printed wiring board comprises bringing a base metal layer and a conductive metal layer into contact with an etching solution capable of dissolving the conductive metal to form a wiring pattern and then sequentially bringing the resultant into contact with a first treating solution capable of dissolving the metal for forming the base metal layer, a microetching solution capable of selectively dissolving the conductive metal and a second treating solution having a different chemical composition from the first treating solution in this order.

Abstract: Embodiments of the present invention include a conductive particle that includes a conductive nickel/gold (Ni/Au) complex metal layer having a phosphorous content of less than about 1.5 weight percent formed on the surface of a polymer resin particle. Methods of forming the same are also included. A conductive particle with a Ni/Au complex metal layer having less than about 1.5 weight percent of phosphorous may have relatively high conductivity while providing relatively good adhesion of the Ni/Au metal layer to the polymer resin particle. Further embodiments of the present invention provide an anisotropic adhesive composition comprising a conductive particle according to an embodiment of the invention.

Abstract: A metal thin film used in fabricating a damascene interconnection of a semiconductor device which exhibits excellent high temperature fluidity during high pressure annealing, and which can fabricate an interconnection for a semiconductor device which has a low electric resistance and stable high quality is provided. Also provided is an interconnection for a semiconductor device. More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal thin film on an insulator film which is formed on a semiconductor substrate and which has grooves formed therein, and filling the metal thin film in the interior of the grooves by a high pressure annealing process are provided.

Abstract: The invention provides a substrate with multi-layer interconnection structure, which includes a substrate and a multi-layer interconnection structure formed on the substrate. The multi-layer interconnection structure is adhered to the substrate in partial areas. The invention also provides a method of manufacturing and recycling such substrate and a method of packaging electronic devices by using such substrate. The invention also provides a method of manufacturing multi-layer interconnection devices.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: There is provided a semiconductor device in which extension units are formed in the ends of a slit that constitutes a slit pattern to relieve stress transmitted between interconnect layers. The embodiments relate to a semiconductor device which includes a first metal layer included on a semiconductor substrate, an interlayer dielectric layer having a low dielectric constant and being formed on the first metal layer, via patterns formed on the interlayer dielectric layer, a second metal layer formed on the interlayer dielectric layer having the low dielectric constant, and slit patterns formed immediately above regions of the second metal layer where the via patterns of the interlayer dielectric layer are not formed, wherein extension units are formed at an end of a slit that constitutes a slit pattern.

Abstract: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.

Abstract: The semiconductor device manufacturing method includes the steps of: applying a first wire including a barrier metal film, a seed film, and a wiring material film in a first wire trench formed in a first interlayer dielectric film; after a second interlayer dielectric film is formed on the first interlayer dielectric film, forming a via hole and a second wire trench in the second interlayer dielectric film so as to expose the wiring material film; applying a barrier metal film on the semiconductor device; and after the barrier metal film on the wiring material film is removed by using, for example, a re-sputtering process, applying a barrier metal film on the wiring material film. The re-sputtering process can remove an oxide film of impurity metal in the seed film applied on the wiring material film.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. The method can include: forming a gate electrode and a source/drain region on a semiconductor substrate; forming a pre metal dielectric insulation layer on the semiconductor substrate, the pre metal dielectric insulation layer including a first insulation layer using a first deposition device and a second insulation layer using a second deposition device, the second deposition device having a relatively higher deposition rate than the first deposition device; and forming a metal pattern on the pre metal dielectric layer, wherein the metal pattern electrically connects to the gate electrode and the source/drain region through the pre metal dielectric insulation layer.

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.

Abstract: A semiconductor device includes a first metal layer formed on a semiconductor substrate and an interlayer insulating layer formed on the first metal layer, wherein a via hole is formed in the interlayer insulating layer. The semiconductor device further includes a second metal filled into the via hole at a predetermined height, a third metal layer pattern formed on the second metal, a silicon layer pattern formed on the third metal layer pattern, a first barrier metal formed on an inner wall of the via hole and on a top side of the silicon layer pattern, a fourth metal filled on the first barrier metal in the via hole, and a fifth metal layer formed on the interlayer insulating layer.

Abstract: In some embodiments a high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous material. Other embodiments are described and claimed.

Abstract: An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal interconnection, a first interlayer dielectric layer formed on the metal interconnection and having a first contact plug, a second interlayer dielectric layer formed on the first interlayer dielectric layer and having a second contact plug, and a third interlayer dielectric layer formed on the second interlayer dielectric layer and having a third contact plug, wherein the first to third contact plugs are connected to each other.

Abstract: A method includes at least one of: forming a metal interconnection in a semiconductor device; forming an inter-metal dielectric layer over a substrate and/or a lower metal layer; forming a photoresist pattern over an inter-metal dielectric layer; forming a via hole by selectively etching an inter-metal dielectric layer using a photoresist pattern as a mask; forming an ionization layer in a via plug by ion implantation on a sidewall of a via hole; forming a barrier metal layer and a via plug in the via hole; and/or forming a metal interconnection. In embodiments, a barrier metal layer may include titanium nitride and/or a via plug may include tungsten.

Abstract: A method of manufacturing a Metal-Insulator-Metal (MIM) capacitor and an MIM capacitor formed by the method are described. The method comprises sequentially forming a dielectric film and an interlayer insulating film on a silicon substrate on which lower copper wiring is formed, forming via holes by selectively etching the interlayer insulating film, and defining a region for the formation of an upper electrode of the capacitor, forming trenches by selectively etching the interlayer insulating film, and forming a capacitor having a lower copper wiring/dielectric film/upper electrode structure by filling the formed trenches with copper and filling the defined region for the formation of the upper electrode with copper.

Abstract: A semiconductor device includes an embedded wire in a first wire trench formed in a first interlayer dielectric film, the embedded wire having a barrier metal, a first seed film, a second seed film, and a copper film. The first seed film is formed by a copper film containing metal, and the second film is formed by a copper film. The second seed film suppresses that the metal contained in the first seed film diffuses into a wiring material film in a manufacturing process.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at least one of an active feature and an interconnect structure disposed within the first substrate, and forming a reactive material on a surface of at least one of the active features.

Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.

Abstract: A semiconductor chip for flip chip bonding, a mounting structure for the semiconductor chip, and methods for forming a semiconductor chip for flip chip bonding and for fabricating a printed circuit board for a mounting structure of a semiconductor chip are provided which may improve connection between a solder bump of the semiconductor chip and a substrate of the printed circuit board without having to use an underfill material. A polymer core of the solder bump may be supported between a 3-dimensional UBM and a 3-dimensional top surface metallurgy, so as to establish connection strength of the solder bump without using underfill material, and to absorb the stresses which may concentrate on the solder bump due to the difference in coefficients of thermal expansion between metals.

Abstract: A chip manufacturing process is disclosed. A wafer having a passivation layer and at least one bonding pad is provided. The surface of the bonding pad is exposed to a first opening of the passivation layer. A first metal layer is formed on the bonding pad exposed by the first opening. A photoresist having a second opening and a photoresist block disposed in the second opening is formed on the first metal layer. The first metal layer corresponding to the second opening has a first surface, and the first metal layer corresponding to the photoresist block has a second surface. A second metal layer is formed on the first surface, and the photoresist block is removed to expose the second surface. A UBM layer is formed on the second metal layer and the second surface of the first metal layer. Finally, a conductive bump is formed on the UBM layer.

Abstract: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the fixing layer. Each of the lead wires has an inner end electrically connected to one of the contacts on the bare chip via an inner connecting window area provided on the adhesive layer corresponding to the contacts on the bare chip, and an outer end extended to one of multiple outer connecting window areas provided on the fixing layer to electrically connect to one of many external conducting bodies implanted in and exposed from the outer connecting window areas, such that no leadframe is needed to enable further reduced volume and decreased packaging cost of the whole chip packaging structure.