Abstract: A radiation-emitting semiconductor component with a semiconductor body, including a first principal surface (5), a second principal surface (9) and a semiconductor layer sequence (4) with an electromagnetic radiation generating active zone (7), in which the semiconductor layer sequence (4) is disposed between the first and the second principal surfaces (5, 9), a first current spreading layer (3) is disposed on the first principal surface (5) and electrically conductively connected to the semiconductor layer sequence (4), and a second current spreading layer (10) is disposed on the second principal surface (9) and electrically conductively connected to the semiconductor layer sequence (4).

Abstract: An LED chip (2) is composed of a p-GaN layer (10), an n-GaN layer (14), and an MQW emission layer (12) that is sandwiched between the GaN layers (10 and 14). Each layer is made of a GaN semiconductor. Light exits the LED chip (2) through the n-GaN layer (14). A p-electrode (16) of the LED chip (2) has a surface profile (24B) defined by a plurality of columnar projections (24A) formed in a uniformly distributed relation on the surface facing toward the p-GaN layer (10). The p-electrode (16) is in contact with the p-GaN layer (10) at the top surface of each projection (24A).

Abstract: A single light source multicolor LED, including a package baseplate having a high heat dissipation effect, and the package baseplate is provided with a heat dissipating layer and a printed circuit. The printed circuit includes an insulating layer, a conductive layer and a covering layer. A surface of the package baseplate is provided with a concavity, interior of which is provided with a light reflecting layer and an array of a plurality of light-emitting chips. Extended electrical contacts of the printed circuit enable the array of the plurality of light-emitting chips within the concavity to be respectively soldered to the conductive layer of the printed circuit, and varied high and low electric potential of the printed circuit produces varied electric currents that control the array of the plurality of light-emitting chips, thereby enabling the package baseplate to produce multicolor varied frequency spectral light from a single light source.

Abstract: A high heat dissipating package baseplate for a high brightness LED, wherein a package baseplate manufacturing process includes a baseplate manufacturing process, a wiring manufacturing process and a package manufacturing process. An arc concavity is formed in a surface of a heat dissipating piece, and a light reflecting layer having light gathering effectiveness is made to cover a surface of the concavity. A light-emitting diode is disposed on the light reflecting layer, a printed circuit board is disposed on the heat dissipating piece, making a package baseplate finished product. The heat from the light-emitting diode is directly conducted away through the heat dissipating piece serving as a thermal conducting medium, thereby shortening the path that heat dissipation must pass through, which increases speed and improves effectiveness of heat dissipation. Moreover, such a configuration is dissimilar to any cup-shaped attachment method of prior art used as a thermal conduction means.

Abstract: A light emitting device includes an active layer structure, which has one or more active layers with luminescent centers, e.g. a wide bandgap material with semiconductor nano-particles, deposited on a substrate. For the practical extraction of light from the active layer structure, a transparent electrode is disposed over the active layer structure and a base electrode is placed under the substrate. Transition layers, having a higher conductivity than a top layer of the active layer structure, are formed at contact regions between the upper transparent electrode and the active layer structure, and between the active layer structure and the substrate. Accordingly the high field regions associated with the active layer structure are moved back and away from contact regions, thereby reducing the electric field necessary to generate a desired current to flow between the transparent electrode, the active layer structure and the substrate, and reducing associated deleterious effects of larger electric fields.

Abstract: Provided an LED package comprising a first package composed of a first region serving as a first electrode and a second region which is formed so as to overlap a portion of the first region, the second region defining a molding material filling cavity; one or more LED chips mounted on the first region of the first package; a second package formed under the second region of the first package, the second package being insulated by the first region and an insulating member so as to serve as a second electrode; conductive wire for electrically connecting the LED chips and the second package; and a molding material filled inside the second region of the first package so as to protect the LED chips and the conductive wire. The first and second packages are formed of aluminum.

Abstract: A semiconductor light emitting device is provided having a highly reliable reflection and electrode layer. The semiconductor light emitting device is manufactured by the steps of: forming an insulating film on a surface of a silicon substrate; forming an adhesion layer made of at least one of Ti and Cr on the insulating film; forming a barrier metal layer made of at least one of Ni, Pt and Pd on the adhesion layer; forming one or more silver alloy portions each constituting a silver alloy layer on the barrier metal layer; and electrically connecting at least one of the silver alloy portions to a semiconductor light emitting device chip.

Abstract: A light emitting die (LED) package is provided which includes a substrate having traces, a LED mounted on the substrate and connected to the traces, and an encapsulant covering the LED. The package includes a lens sitting on the encapsulant and substantially covering the LED. The lens is free to move relative to the substrate.

Abstract: In an optical semiconductor integrated circuit device using a lead frame, a transparent epoxy resin composition for molding an optical semiconductor contains (A) an epoxy resin; (B) a curing agent; (C) a thiol; and (D) an amine-based curing catalyst represented by following Chemical Formula 1: R1: a hydrogen atom (—H), an alkyl group, or a phenyl group R2: an alkyl group (—CH3, —C2H5, —C3H7)

Abstract: A semiconductor device manufacturing method includes the steps of filling a cavity and a resin reservoir hole in a lower metal mold with a liquid-state resin, holding a semiconductor element between the lower metal mold and an upper metal mold, injecting the resin in the resin reservoir hole into the cavity to seal the semiconductor device with the resin. Thus, the semiconductor device having almost no voids and less material loss is manufactured with high accuracy.

Abstract: It is an object to provide a p-type ZnS based semiconductor material having a low resistance which can easily form an ohmic contact to a metallic material. Moreover, the invention provides a semiconductor device and a semiconductor light emitting device which include an electrode having a low resistance on a substrate other than a single crystal substrate, for example, a glass substrate. The semiconductor material according to the invention is used as a hole injecting electrode layer of a light emitting device and has a transparent property in a visible region which is expressed in a composition formula of Zn(1-?-?-?)Cu?Mg?Cd?S(1-x-y)SexTey (0.004???0.4, ??0.2, ??0.2, 0?x?1, 0?y?0.2, and x+y?1).

Abstract: A LED structure with enhanced side-emitting capability is provided. An embodiment of The LED structure comprises, on top of a substrate, a metallic layer, a non-alloy ohmic contact layer, a thick transparent layer, a light generating structure, sequentially arranged in the this order from bottom to top. The metallic layer functions a reflective mirror and is made of a pure metal or a metal nitride for superior reflectivity. The non-alloy ohmic contact layer is interposed between the light generating structure and the metallic layer so as to achieve the required low resistance electrical conduction. The thick transparent layer extracts a significant portion of the light to the sides of the LED structure. The thick transparent layer, made of a semiconductor material or a dielectric material having an refractive index between 1.5 to 3.5, could be located either above, below or both above and below the light generating structure.

Abstract: A solid state light emitting device comprises one or more active layers comprising semiconductor nano-particles in a host matrix, e.g. silicon nano-particles in silicon dioxide or silicon nitride. The incorporation of carbon in the active layers provides a great improvement in performance through shortened decay time and enhance emission spectra, as well as reliability and lifetime. The emission wavelengths from the nano-particles can be made to correspond to the quantization energy of the semiconductor nano-particles, which allows the entire visible range of the spectrum be covered. Ideally an engineered structure of alternating active and buffer material layers are disposed between AC or DC electrodes, which generate an electric field.

Abstract: An object of the present invention is to provide a positive electrode, in which the silver is used, for a compound-semiconductor light-emitting device high in inverse voltage and excellent in stability and productivity. The inventive positive electrode for a compound-semiconductor light-emitting device comprises a reflective layer of a silver alloy.

Abstract: An electronic module has a heat sink with an upper surface and a lower surface, a plurality of leads arranged adjacent the heat sink and at least one circuit element with two vertical semiconductor power switches. The two vertical semiconductor power switches of each circuit element are arranged in a stack and are configured to provide a half-bridge circuit having a node defining an output. The first vertical semiconductor power switch of each of the circuit elements is mounted on the upper surface of the heat sink by an electrically conductive layer such that the lower surface of the heat sink provides the ground contact area of the electronic module.

Abstract: In one embodiment, a Schottky diode structure comprises a Schottky barrier layer in contact with a semiconductor material through a Schottky contact opening. A conductive ring is formed adjacent the Schottky contact opening and is separated from the semiconductor material by a thin insulating layer. Another insulating layer is formed overlying the structure, and a contact opening is formed therein. The contact opening is wider than the Schottky contact opening and exposes portions of the conductive ring. A Schottky barrier metal is formed in contact with the semiconductor material through the Schottky contact opening, and is formed in further+contact with the conductive ring.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer (passivation film) such as SiN provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. According to the present invention, a light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air.

Abstract: A commercially mass-produced, integrated circuit including: a solid substrate of one conductivity type; at least one solid material pocket of a different conductivity type having a side surface and positioned on a selected top surface of the substrate to thereby form a signal-translating, electronic rectifying barrier between the at least one solid material pocket and the selected top surface of the substrate; and a solid state material region adjoining the substrate, the electronic rectifying barrier, and the side surface of the at least one solid material pocket; wherein next to the electronic rectifying barrier the solid state material region has a lateral dimensional accuracy of better than a few hundred atomic layers.

Abstract: A non-volatile memory device and method of fabricating same are disclosed. The memory device comprises; a gate insulating film formed on a semiconductor substrate, a floating gate completely covering the gate insulating film, the floating gate comprising a conductive film pattern and a conductive spacer formed at one side of the conductive film pattern, a tunnel insulating film formed on a portion of the conductive film pattern, the conductive spacer, and extending laterally outward over a portion of the semiconductor substrate adjacent the conductive spacer, a control gate formed on the tunnel insulating film, a first impurity region formed within the semiconductor substrate proximate one side of the conductive film pattern opposite the conductive spacer, and a second impurity region formed within the semiconductor substrate proximate one side of the control gate disposed laterally outward from the floating gate.

Abstract: An optical waveguide structure includes an air-via region that receives an optical signal from an optical source. A photonic crystal cladding region is formed on the surface of the air-via region. The photonic crystal cladding region confines the optical signal within the air-via region and propagates the optical signal along the axial direction while ensuring near complete transmission of the optical signal.

Abstract: A method of manufacturing a flash memory device, one embodiment of which includes the steps of forming a floating gate pattern in which a tunnel oxide film, a first conductive layer, and a nitride film are laminated on a semiconductor substrate of a first region, and forming isolation films on the semiconductor substrate of a second region; stripping the nitride film and then etching the isolation films to a predetermined thickness by a dry etch process; and, sequentially forming a dielectric film, a second conductive layer, and a hard mask film on the entire structure, patterning the hard mask film to form a control gate, and etching the floating gate pattern using the control gate as a mask, thus forming a floating gate. After the nitride film serving as the etch mask for forming the trenches is stripped, the etch process of the isolation films for controlling an EFH is performed under the conditions in which the isolation films are etched while the conductive layer is not etched.

Abstract: A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.

Abstract: A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting t

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.

Abstract: A display device includes a first insulating substrate having thin film transistors; a second insulating substrate of plastic having a black matrix comprising a plurality of horizontal extending portions extending in one directions and a plurality of vertical portions extending at an irregular interval in a second direction perpendicular to the first direction; and a liquid crystal layer located between the first substrate and the second substrate.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensing device includes a semiconductor substrate; a photodiode defined on the substrate; a gate dielectric layer provided over the photodiode and the substrate; a polysilicon interconnect contacting a given area of the photodiode via an opening in the gate dielectric layer; a reset transistor coupled to the photodiode; a source follower transistor coupled to the photodiode; and a select transistor coupled to the source follower transistor. The given area of the photodiode defines a node that is coupled to the reset transistor and source follower transistor.

Abstract: A solid-state image sensor includes pixels and lenses. Each of the pixels on a semiconductor substrate includes a photodetecting section which photoelectrically converts incident light. Each of the lenses condenses the incident light on the photodetecting section. The lenses have a fixed curvature on an incident surface for the incident light. A top of the incident surface of each of the lenses is at a position different from that of a center of a bottom surface of each of the lenses in a direction horizontal to the bottom surface.

Abstract: A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.

Abstract: A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.

Abstract: A semiconductor device includes a semiconductor substrate, a storage pad and a bit line pad on the semiconductor substrate, a first interlayer insulating layer covering the bit line pad and including a bit line contact hole having a width greater than a width of the bit line pad, a barrier insulating layer on sidewalls of the first interlayer insulating layer and upper portions of sidewalls of the bit line pad that are exposed by the bit line contact hole, a bit line plug in the bit line contact hole and on the barrier insulating layer; and a storage plug penetrating the first interlayer insulating layer and contacting the storage pad.

Abstract: An IGBT includes a first silicon region over a collector region, and a plurality of pillars of first and second conductivity types arranged in an alternating manner over the first silicon region. The IGBT further includes a plurality of well regions each extending over and being in electrical contact with one of the pillars of the first conductivity type, and a plurality of gate electrodes each extending over a portion of a corresponding well region. The physical dimensions of each of the first and second conductivity type pillars and the doping concentration of charge carriers in each of the first and second conductivity type pillars are selected so as to create a charge imbalance between a net charge in each pillar of first conductivity and a net charge in its adjacent pillar of the second conductivity type.

Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.

Abstract: The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers being substantially orthogonal relative to first, second and third rows of contact plugs. An opening is etched which passes through each of the conductive layers within the plurality of conductive layers. The opening is disposed laterally between the first and second row of contact plugs. After etching the opening a dielectric material is deposited over the plurality of conductive layers and a second conductive material is deposited over the dielectric material. The invention includes an electronic system including a processor and a memory operably associated with the processor. The memory device has a memory array which includes double-pitched capacitors.

Abstract: A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Abstract: A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells.

Abstract: A non-volatile memory device integrated on semiconductor substrate and having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of active areas formed on the semiconductor substrate equidistant from each other, and having at least a first and a second group of active areas; the non-volatile memory cells integrated in the first group of active areas, each non-volatile memory cell having a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, at least one group of the memory cells sharing a common source region integrated on the semiconductor substrate; and a contact region integrated in the second group of active areas and provided with at least one common source contact of the common source region.

Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Abstract: There are provided a method of fabricating a flash memory device and a flash memory device fabricated thereby. The method of fabricating a flash memory device includes forming an isolation layer defining an active region in a semiconductor substrate, wherein the isolation layer is formed to have a protrusion being higher than a top surface of the active region, and to provide a groove in the active region. A conductive layer pattern is formed in the groove. A buffer layer is formed on the semiconductor substrate having the conductive layer pattern. Then, an oxidation barrier layer pattern having a line shape opening across the active region is formed on the buffer layer. The buffer layer and an upper portion of the conductive layer pattern, which are exposed by the opening, are selectively oxidized to form a mask oxide layer at a cross region of the opening and the active region, and simultaneously to form a buffer oxide layer on the isolation layer adjacent to the mask oxide layer.

Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

Abstract: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.

Abstract: A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source electrode to the drain electrode. The inorganic semiconductor has a stack of 2-dimensional layers in which intra-layer bonding forces are covalent and/or ionic. Adjacent ones of the layers are bonded together by forces substantially weaker than covalent and ionic bonding forces. The dielectric layer is interposed between the gate electrode and the layer of inorganic semiconductor material. The gate electrode is configured to control a conductivity of an active channel part of the layer of inorganic semiconductor.

Abstract: A vertical trench-gate semiconductor device wherein the trench-gates extend in stripes, the source regions extend transversely between the trenchgates in stripes, projection (20) of the source stripes across the trench-gates defines intermediate trench portions (22) between the projected source stripes, and mutually spaced regions (14,14?) of the second conductivity type are to provided immediately below the intermediate trench portions (22) which are connected to source potential. The spaced regions serve to selectively shield portions of the trench-gate from the drain region to suppress their contribution to Cgd and hence Qgd. In particular, they shield those portions of the trenchgate which do not contribute to the channel width of the device, without restricting the current path where a channel is formed.

Abstract: Consistent with an example embodiment, a trench FET has source regions arranged above insulated gates in trenches. A body region of opposite conductivity type is arranged between the trenches and a body region is arranged above the body region. Source contact metallisation contacts the source and body contact region. In this way a small cell pitch can be achieved.

Abstract: High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying the substrate, comprising a gate dielectric layer and a gate electrode formed thereon. A channel well and a second well are formed in portions of the first well. A source region is formed in a portion of the channel well. A drain region is formed in a portion of the second well, wherein the gate dielectric layer comprises a relatively thinner portion at one end of the gate stack adjacent to the source region and a relatively thicker portion at one end of the gate stack adjacent to and directly contacts the drain region.

Abstract: The invention relates to a semiconductor circuit arrangement having at least one first and a second field effect transistor (T1, T2), where the field effect transistors respectively have at least two active regions (AA11 to AA22) with, respectively, a source region, a drain region and an intermediate channel region, the surface of the channel regions having a gate (G11 to G22) formed on it, insulated by a gate dielectric, for the purpose of actuating the channel regions. At least one active region (AA22) of the second field effect transistor (T2) is arranged between the at least two active regions (AA11, AA12) of the first field effect transistor (T1), which results in a reduced mismatch between the two transistors, caused by temperature and local distances.

Abstract: A power transistor includes a semiconductor layer an electrode layer. The semiconductor layer having a source zone, a drain zone spaced apart from the source zone in a lateral direction, a drift zone adjacent to the drain zone, and a body zone. The body zone is interposed between the drift zone and the source zone. The electrode layer is dielectrically insulated from the semiconductor layer, and includes a gate electrode divided into at least two sections and a field plate. The field plate is arranged at a first height level relative to the semiconductor layer. A first gate electrode section is arranged at least partially at a second height level, which is lower than the first height level relative to the semiconductor layer. A second gate electrode section, which is laterally displaced from the first gate electrode section, is disposed at a first intermediate level arranged between the first and second height levels.