Abstract: It is an object to provide a thin-type full-color display device with the long lifetime, inexpensively, in which desired emission luminance and desired color purity can be obtained at a low voltage. In a light-emitting device capable of full-color display, among a plurality of light-emitting elements emitting different emission colors (for example, colors of red (R), green (G), and blue (B)), at least one of the light-emitting elements of an emission color is a light-emitting element including an organic compound (an organic EL element), and the other light-emitting element of an emission color is a light-emitting element using an inorganic material as a light-emitting layer or a fluorescent layer (an inorganic EL element). It is to be noted that the organic EL element and the inorganic EL element are formed over the same substrate.

Abstract: Provided are a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminium nitride crystal or an aluminum oxynitride crystal.

Abstract: In a conventional semiconductor light-emitting device having a semiconductor light-emitting element-mounted body and an optical lens which are located adjacent each other, interfacial peeling sometimes occurs at the contact interfaces between components when the device is subjected to outside temperature changes. This may lead to the deterioration of optical characteristics and the reduction in reliability of the device. In accordance with an aspect of the disclosed subject matter, a semiconductor light-emitting element-mounted body can be integrated with the optical lens via a soft resin spacer. Hence, the soft resin spacer can serve as a thermal stress relaxation layer located between the semiconductor light-emitting element-mounted body and the optical lens, which are integrated together. The thermal stress relaxation layer can possibly prevent peeling, caused by thermal stresses due to outside temperature changes, from occurring at the interfaces between the components.

Abstract: A semiconductor light-emitting device includes a semiconductor light-emitting element and a lead-out electrode. The semiconductor light-emitting element has a light-emitting surface of polygonal shape and an electrode formed on the light-emitting surface. The lead-out electrode is connected to the electrode. In the semiconductor light-emitting device, the electrode is formed along at least two sides of the light-emitting surface. In addition, the lead-out electrode is formed on the electrode, and includes an opening portion which opens toward an upper side of the light-emitting surface.

Abstract: The present invention discloses a side structure of a bare LED and a backlight module thereof, wherein the backlight module is preferably a light source of a display device such as an LCD device. The backlight module includes a flat plate covered with a thermally conductive dielectric material, a plurality of the side structures of the bare LEDs placed on the flat plate and in contact with the thermally conductive dielectric material, and a plurality of reflection parts also placed on the flat plate, each side structure of each bare LED includes a bare LED and two electrically conductive materials coupled to two bonding pads of the side structure of the bare LED respectively, and positioned on the flat plate therefor.

Abstract: To provide a light-emitting material made of an inorganic compound, which exhibits higher luminance than the conventional material, due to its crystal structure. The light-emitting material includes a host material and an impurity element which serves as a luminescence center. The main crystal structure of the light-emitting material is hexagonal. The host material is a compound of a Group 2 element and a Group 16 element, or a compound of a Group 12 element and a Group 16 element. The impurity element includes at least one of manganese (Mn), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), and praseodymium (Pr).

Abstract: Provided are a nitride semiconductor light-emitting device and a method for manufacturing the same, capable of improving light emitting efficiency by forming a reflection layer on a lateral side of an LED chip. Am embodiment provides a nitride semiconductor light-emitting device includes a light-emitting device chip and a reflection layer. The reflection layer is formed on a lateral side of the light-emitting device chip.

Abstract: Structure and method of structure in which a contact, e.g., low resistance; ohmic; resulting in Schottky isolation, is coupled to a doped region that is buried in a substrate. In a bipolar transistor having a collector region formed below an upper surface of a substrate, a trench is formed through a portion of the collector region, and the sidewall(s) and/or bottom of the trench are doped, e.g., by ion implantation or dopant. The trench is filled with a conductor, e.g., a refractory metal such as tungsten.

Abstract: In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.

Abstract: In order to lay out a power amplifier heterojunction bipolar transistor capable of large power output in a small area, the subject invention provides a heterojunction bipolar transistor constituted of a plurality of transistor components arranged on a sub-collector layer, collector layers of said transistor components being separated one another, said transistor components being arranged in a line in a longitudinal direction of an emitter. The subject invention also provides a multi-finger type heterojunction bipolar transistor using the heterojunction bipolar transistor as a unit transistor.

Abstract: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD).

Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V).

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

Abstract: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

Abstract: According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

Abstract: An image pickup apparatus of the present invention includes a plurality of photoelectric conversion elements disposed on a semiconductor substrate, a multi-layer wiring structure including a plurality of interlayer insulation films disposed above the semiconductor substrate, and a passiation layer disposed above the multi-layer wiring structure. A first insulation layer is disposed below the under surface of the passiation layer; a second insulation layer is disposed above the top surface of the passiation layer; and the refractive indices of the passiation layer and the first insulation layer differ from each other, and the refractive indices of the passiation layer and the second insulation layer differ from each other. Moreover, planarization processing is performed to at least one layer of the interlayer insulation films and the first insulation layer.

Abstract: A semiconductor device comprises a floating gate which is formed on a semiconductor substrate of a first conductive type interposing a first gate insulation layer therebetween, a second charge retaining area which is formed on the semiconductor substrate interposing a second insulation layer, a control gate which is formed on the floating gate interposing a second gate insulation layer therebetween, a second gate electrode which extends in the first direction and which is formed on the second charge retaining region interposing the second gate insulation layer therebetween, and a semiconductor layer which extends in a second direction and which is formed on the semiconductor substrate so as to intersect the first and the second gate electrode are provided; wherein an n-type conductive region of a second conductive type is formed on the semiconductor layer. Consequently, it achieves high-integration of a semiconductor device.

Abstract: An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state. Then the impurities are activated, and the amorphized portion is recrystallized, by low temperature solid-phase epitaxial regrowth. With the processing temperature required for the low temperature solid-phase epitaxial regrowth being within a range of 450° C.-650° C., thermal diffusion of the impurities into the semiconductor film is suppressed, thereby maintaining the initial steep step-profile.

Abstract: [Means for Solving] A semiconductor device 10 comprises a P type base region 13 formed in an N? type base region 11, and N+ type emitter regions 14 formed plurally in the P type base region 13 so as to be spaced form each other. The N+ type emitter regions 14 are formed such that the rate of the area occupied by the N+ type emitter region 14 in the P type base region 13 at the center part of the semiconductor device 10 is smaller than the rate of the area occupied by the N+ type emitter region 14 in the P type base region 13 at the peripheral part of the semiconductor device 10.

Abstract: According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate.

Abstract: The present invention discloses an architecture of a NMOS transistor with a compressive strained Si—Ge channel fabricated on a silicon (110) substrate, which comprises: a p-silicon (110) substrate, two n+ ion-implanted regions functioning as the source and the drain respectively, a compressive strained Si—Ge channel layer, and a gate structure. The compressive strained Si—Ge channel layer is grown on the p-silicon (110) substrate to reduce the electron conductivity effective mass in the [1_l -10] crystallographic direction and to promote the electron mobility in the [1-10] crystallographic direction. Thus, the present invention can improve the electron mobility of a NMOS transistor via the channels fabricated on the silicon (110) substrate. Further, the NMOS transistor of the present invention can combine with a high-speed PMOS transistor on a silicon (110) substrate to form a high-performance CMOS transistor on the same silicon (110) substrate.

Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.

Abstract: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.

Abstract: A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.

Abstract: A memory device is provided. The memory device including memory cells having at least three stacked electrodes spaced apart pairwise by dielectric material so that the pairs of electrodes form respective capacitor layers. The capacitors are connected electrically in parallel to each other. The dielectric material is optionally ferroelectric material, in which case the capacitors are ferrocapacitors.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

Abstract: A method for forming a capacitor insulation film includes the step of depositing a monoatomic film made of a metal by supplying a metal source including the metal and no oxygen, and depositing a metal oxide film including the metal by using a CVD technique. The method provides the metal oxide film having higher film properties with a higher throughput.

Abstract: A semiconductor device prevents diffusion of electric charges retained in silicon nitride films of a MOSFET during a writing operation and has a favorable charge retention property. The silicon nitride films, each of which functions as a memory functional body, are formed at a thickness of 100 ? at a maximum. Each of the silicon nitride film dose not exist on each side surfaces of a gate electrode but exists only on each silicon oxide films between the gate electrode and a substrate, so that each of the silicon nitride films is small in volume.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.

Abstract: A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

Abstract: A non-volatile semiconductor memory which can suppress a leak current, improve dielectric strength and ensure large capacitance between a control gate and a floating gate and a manufacturing process thereof. A silicon nitride film is formed on the floating gate electrode layer of a memory cell and has a thickness of 5 nm or more. A high dielectric constant thin film is formed on the silicon nitride film. A control gate electrode layer is formed over the high dielectric constant thin film.

Abstract: A nonvolatile memory device includes a semiconductor pin including a first semiconductor pattern, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern, disposed between the first semiconductor pattern and the second semiconductor pattern, connecting the first semiconductor pattern and the second semiconductor pattern, a charge storage layer on the second semiconductor pattern with a tunneling insulation layer interposed therebetween, and a gate electrode on the charge storage layer with a blocking insulation layer interposed therebetween, wherein a width of the second semiconductor pattern is greater than a width of the third semiconductor pattern.

Abstract: Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices on the first areas and second type devices on the second areas, wherein the first type devices are parallel or perpendicular to the second type devices. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).

Abstract: A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions includes one or more body contact diffusion regions formed in the source regions where each body contact diffusion region has a length that extends to the edges of the two adjacent polysilicon lines, and one or more body pickup contacts where each body pickup contact is formed over a respective body contact diffusion region. In one embodiment, the body contact diffusion regions are formed in a fabrication process using ion implantation of dopants of a first type through a body diffusion mask. Each body contact diffusion region defined by an exposed area in the body diffusion mask has a drawn area that overlaps the respective two adjacent polysilicon lines.

Abstract: A semiconductor device includes: a semiconductor base material; an insulating layer selectively formed on the semiconductor base material; a first semiconductor layer made of single-crystal and formed on the semiconductor base material that is exposed below the insulating layer, the first semiconductor layer having an opening that exposes the semiconductor base material; a second semiconductor layer made of a single-crystal whose wet-etching selectivity is smaller than a wet-etching selectivity of the first semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having the opening that exposes the semiconductor base material; a polycrystalline layer made of the same composition as the second semiconductor layer, the polycrystalline layer being formed on the insulating layer; a support film formed on a whole upper face of the semiconductor base material and filling the opening; a mask pattern formed on the support film so as to continuously cover at least a part of

Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.

Abstract: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.

Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate; side wall spacers on side surfaces of the gate electrode; a source portion and a drain portion in the semiconductor substrate, the source portion and the drain portion being provided laterally to the side wall spacers; an on-source silicide film on the source portion; an on-drain silicide film on the drain portion; source contacts over the source portion; and at least a pair of drain contacts which are provided over the drain portion and which are aligned in the gate width direction of the gate electrode. Part of the drain portion between the pair of drain contacts includes a high resistance region at least in an area between the side wall spacer and edges of the drain contacts facing the gate electrode such that the on-drain silicide film is not provided in the high resistance region.

Abstract: Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Abstract: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

Abstract: A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the semiconductor die, the L-shaped area having first and second inner sides that are respectively disposed adjacent first and second sides of the control circuit. At least one of the first and second output transistors is coupled to the control circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.