Abstract: A thermal isolation structure for use in passively regulating the temperature of a microdevice is disclosed. The thermal isolation structure can include a substrate wafer and a cap wafer defining an interior cavity, and a number of double-ended or single-ended thermal bimorphs coupled to the substrate wafer and thermally actuatable between an initial position and a deformed position. The thermal bimorphs can be configured to deform and make contact with the cap wafer at different temperatures, creating various thermal shorts depending on the temperature of the substrate wafer. When attached to a microdevice such as a MEMS device, the thermal isolation structure can be configured to maintain the attached device at a constant temperature or within a particular temperature range.

Abstract: A pressure sensor includes a gold-silicon eutectic crystal layer interposed between the contact layer and the silicon substrate. Because the contact layer and the silicon substrate are electrically connected to each other by using a gold-silicon eutectic reaction at the time of bonding the silicon substrate and the glass substrate, a contact resistance between the contact layer and the silicon substrate can be stabilized, and a Q value of the sensor can be stabilized. In addition, since the contact layer and the silicon substrate are bonded to each other by the gold-silicon eutectic reaction, the bonding strength is sufficient.

Abstract: A mechanical quantity measuring apparatus is provided which can make highly precise measurements and is not easily affected by noise even when it is supplied an electricity through electromagnetic induction or microwaves. At least a strain sensor and an amplifier, an analog/digital converter, a rectification/detection/modulation-demodulation circuit, and a communication control circuit are formed in one and the same silicon substrate. Or, the silicon substrate is also formed at its surface with a dummy resistor which has its longitudinal direction set in a particular crystal orientation and which, together with the strain sensor, forms a Wheatstone bridge. With this arrangement, even when a current flowing through the sensor is reduced, measured data is prevented from being buried in noise, allowing the sensor to operate on a small power and to measure a mechanical quantity with high precision even when it is supplied electricity through electromagnetic induction or microwaves.

Abstract: The invention relates to a method for storing information on a storage device (100) by depositing electromagnetic material (104) in a pattern on a sensor surface (106) of the storage device, the pattern representing the information to be stored. The storage device (100) comprises an array of sensor elements (101) that are sensitive to electromagnetic material (104) within a near field working distance (105). The read-out is done by a resistance measurement which relies on a magneto resistance phenomenon detected in a multilayer stack of the sensor elements (101). The storage device (100), comprising the deposited pattern of electromagnetic material (104), is a Read Only Memory device. The deposition of the pattern is, for example, possible by scanning a depositing unit (403), e.g. a printer head, in a line-by-line motion across the sensor surface (106), resulting in a Printed Magnetic ROM.

Abstract: A photoelectric conversion device including a photoelectric conversion part including a pair of electrodes and a photoelectric conversion layer provided between the pair of electrodes, wherein the photoelectric conversion part further includes a first charge blocking layer for reducing an injection of a charge into the photoelectric conversion layer from one of the pair of electrodes when a voltage is applied between the pair of electrodes, the first charge blocking layer being provided between the one of the pair of electrodes and the photoelectric conversion layer; and the first charge blocking layer has a relative dielectric constant larger than a relative dielectric constant of the photoelectric conversion layer.

Abstract: A photodiode having an increased proportion of light-sensitive area to light-insensitive area includes a semiconductor having a backside surface and a light-sensitive frontside surface. The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic layer separating the first and second active layers. A plurality of isolation trenches are arranged to divide the photodiode into a plurality of cells. Each cell has a total frontside area including a cell active frontside area sensitive to light and a cell inactive frontside area not sensitive to light. The cell active frontside area forms at least 95 percent of the cell total frontside area. A method of forming the photodiode is also disclosed.

Abstract: Techniques for producing a flexible structure attached to a device. One embodiment includes the steps of providing a first substrate, providing a second substrate with a releasably attached flexible structure, providing a bonding layer on at least one of the first substrate and the flexible structure, adjoining the first and second substrate such that the flexible structure is attached at the first substrate by means of the bonding layer, and detaching the second substrate in such a way that the flexible structure remains on the first substrate.

Abstract: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10. Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20. Wiring substrate 20 has formed therein a groove portion 26a that surrounds a region opposing thinned portion 14 and groove portions 26b that extend to an exposed surface of wiring substrate 20 from groove portion 26a. Insulating resin 32 fills a gap between outer edge 15 of thinned portion 14 and wiring substrate 20 to reinforce the bonding strengths of conductive bumps 30.

Abstract: A manufacturing method for a semiconductor device formed in a device region composed of a plurality of semiconductor layers on a substrate, the method including a trench forming step of forming a trench on the substrate around the device region and a semiconductor growth step of growing the semiconductor layer in the device region.

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

Abstract: A semiconductor device capable of preventing an interlayer dielectric film from deterioration resulting from a liquid such as a chemical solution penetrating into the interlayer dielectric film and recovering the interlayer dielectric film from deterioration with a prescribed gas is obtained. This semiconductor device comprises a first insulating film formed on a substrate and a first gas-liquid separation film, formed on at least a part of the surface of the first insulating film, composed of a material hardly permeable by a liquid and easily permeable by a gas.

Abstract: Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed between the first terminal and the anti-fuse layer. The diffusion layer inhibits diffusion of conductive material from the first terminal to the anti-fuse layer when the anti-fuse structure is unprogrammed, but permits diffusion of the conductive material when a programming voltage is applied between the first and second terminals during operation. Advantageously, the first terminal may be composed of metal and the anti-fuse layer may be composed of a semiconductor.

Abstract: A thin film capacitor device of the present invention has a thin film capacitor having two electrodes and a dielectric layer provided therebetween and external terminals electrically connected to the electrodes. In addition, the thin film capacitor device also has resistor layers which are provided between the external terminals and the electrodes and adjacent thereto, and which are formed of a material have a higher resistivity than that of the adjacent electrodes.

Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.

Abstract: A light-detecting device, comprising: a semiconductor substrate 101 that is composed of silicon as a base material, and contains carbon at a predetermined concentration; and an epitaxial layer 102 that is formed on the semiconductor substrate 101 and composed of silicon as a base material, the epitaxial layer 102 including a light-detecting unit (mainly 104) a predetermined distance away from the semiconductor substrate 101, wherein the semiconductor substrate 101 is formed using a crystal growth method from melt obtained by melting a material containing silicon and a material containing carbon so that carbon is contained in the semiconductor substrate 101 at the predetermined concentration.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract: A method for the production of gallium nitride compound semiconductor chips from a wafer having gallium nitride compound semiconductor layers (2, 3) laminated on the principal surface of a substrate (1) comprises a step of forming first grooves (11) linearly in a desired chip shape by etching on the gallium nitride compound semiconductor layers (2, 3) sides of the wafer, a step of forming second grooves (22) having a nearly equal or smaller line width (W2) than a line width (W1) of the first grooves on the substrate (1) side of the wafer at positions not conforming to the central lines of the first grooves, and a step of dividing the wafer along the first and second grooves. It consequently allows the wafer to be accurately cut in an extremely high yield, with the result that the number of chips taken out of one wafer will be increased and the productivity will be enhanced.

Abstract: An insulating material comprising a multiplicity of highly porous particles embedded within a matrix material, the pores within the particles being substantially evacuated.

Abstract: A MEMS microphone with a stacked PCB package is described. The MEMS package has at least one MEMS acoustic sensor device located on a PCB stack. A metal cap structure surrounds the at least one MEMS acoustic sensor device wherein an edge surface of the metal cap structure is attached and electrically connected to the PCB stack. In a first embodiment, a back chamber is formed underlying the at least one MEMS acoustic sensor device and within the PCB stack wherein an opening underlying the at least one MEMS acoustic sensor device accesses the back chamber. An opening in the metal cap structure not aligned with the at least one MEMS acoustic sensor device allows external fluid, acoustic energy or pressure to enter the at least one MEMS acoustic sensor device. In a second embodiment, a back chamber is formed in the space under the metal cap and over the first PCB.

Abstract: A semiconductor package structure is disclosed. The structure includes a lead frame, a semiconductor chip, a plurality of metallic conducting wires, an encapsulation, a barrier layer and a pure tin layer, herein the lead frame has at least one die pad, a plurality of inner leads and outer leads. The semiconductor chip is disposed on the die pad. The metallic conducting wires electrically connect the semiconductor chip and the inner leads. The encapsulation packages of the semiconductor chip, the die pad, the metallic conducting wires and the inner leads. The barrier layer covers each of the outer leads to prevent an inter-metallic compound produced by the outer leads and pure tin. The pure tin layer covers the barrier layer to increase the solder wettability for the outer leads. Besides, a method for manufacturing the semiconductor package structure is disclosed.

Abstract: The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.

Abstract: Electronic component (1; 20) has at least one stack (2; 21, 23) with at least two semiconductor chips (8, 9; 32, 33; 42, 43). Each semiconductor chip (8, 9; 32, 33; 42, 43) includes an active surface including integrated circuits (11; 35) and chip contact pads (10; 34) at least one being a ground cell (13; 37) and a passive surface. The electronic component (1; 20) further includes at least one intermediate spacer (14; 38; 44) with a thermally conductive and electrically conductive material. The intermediate spacer block (14; 38; 44) is positioned between the active surface of a semiconductor chip (9; 33; 43) and the passive surface of an adjacent semiconductor chip (8; 32; 42) in the stack (2; 21, 23). The intermediate spacer (14; 38; 44) and the ground cells (13; 37) of the semiconductor chips (9; 33; 43) are electrically connected and have a common ground.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: A contact tail for an electronic component useful for attachment of components using conductive adhesive, which may be lead (Pb)-free. The contact tail is stamped, providing a relatively low manufacturing cost and high precision. The contact tail has a distal portion with a large surface area per unit length. The distal portion shapes conductive adhesive into a joint, holding the adhesive adjacent the lead for a more secure joint. Additionally, the distal portion holds adhesive to the contact tail before a joint is formed, facilitating the use of an adhesive transfer process to dispense adhesive. To further aid in the transfer of adhesive, the contact tail may be formed with concave portions, which increase the volume of adhesive adhering to the contact tail. By adhering an increased but controlled amount of adhesive to the contact tail, arrays of contact tails may be simply and reliably attached to printed circuit boards and other substrates.

Abstract: A signal routing technique for a multilayered printed circuit board is provided. The multilayered printed circuit board comprises a top layer, a bottom layer and at least one internal layer. Signals for a first subset of a plurality of higher speed buses are routed in stripline on the first internal layer. Signals for a second subset of said plurality of higher speed buses in microstrip on the top layer.

Abstract: The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.

Abstract: The power semiconductor module (1) has a heat-conducting base plate (11) on which at least three substrates (2, 3, 4, 5, 6, 7) are placed, each substrate supporting at least one power semiconductor component (8, 9) that gives off heat generated during operation. In order to optimize a power semiconductor module of this type with regard to mechanical load and heat dissipation, the substrates (2, 3, 4, 5, 6, 7) are placed on the base plate (11) while being arranged in a single row (12), and pressing devices (15, 16), which are situated close to the substrate, are provided on both longitudinal sides (11a, 11b) of the base plate (11) while being arranged parallel to the row (12). The base plate can be pressed against a cooling surface by the pressing devices.

Abstract: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a first surface. The process may then include dispensing and curing an underfill material in the cavity, and attaching a lid to the first surface of the substrate.

Abstract: A semiconductor structure (100) includes a first substrate (110) having a first semiconductor device (112) formed therein, a second substrate (120) having a second device (122) formed therein and vertically-integrated above the first substrate (110), and a thermal isolation gap (130) disposed between the first device (112) and the second device (122). The thermal isolation gap (130) may be formed, for example, using an etched dielectric layer formed on first substrate (110), using an etched cavity in the second substrate (120), or by including a bonding layer (140) that has a gap or void incorporated therein.

Abstract: A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protruding outside the package, and an isolation spacer filling a clearance distance between the package and a heat sink attached to the package.

Abstract: A multichip device, which achieves a normal operation and a testing operation without the needs for terminals dedicated for the testing and/or an interposer substrate, is provided. The peripheral chip also includes a switching unit for providing a switching between a normal mode that provides a first connection condition and a testing mode that provides a second coupling connection condition. The switching unit, in turn, provides connections of at least some of a plurality of outside terminals to the functional circuits, respectively, in the normal mode, and connects at least some of a plurality of outside terminals to the inside terminals in the testing mode. Thus, the normal operation and the testing operation can be carried out without the needs for the external terminals and/or the interposer substrate, which are employed for the purpose of only the testing.

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.

Abstract: A semiconductor structure having a novel cap layer on a low-k dielectric layer and a method for forming the same are provided. The cap layer preferably includes a material selected from the group consisting essentially of CNx, SiCN, SiCO, SiC, and combinations thereof. The semiconductor structure further includes a via in the low-k dielectric layer, and a metal line in the low-k dielectric layer and on the via. An etch stop layer is preferably formed on the cap layer.

Abstract: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.

Abstract: An embodiment of a pseudo nonvolatile memory device incorporating a high capacity micro battery includes a DRAM chip having bonding pads. The DRAM chip may be attached to a frame. The frame may have external connecting terminals corresponding to the bonding pads. Wires are provided for electrically connecting the bonding pads to corresponding external connecting terminals. The bonding pads and the wires may be covered with an encapsulant. A micro battery is provided over the DRAM chip. The micro battery may supply power to the DRAM chip.

Abstract: Noble metal barrier layers are disclosed. In one aspect, an apparatus may include a substrate, a dielectric layer over the substrate, and an interconnect structure within the dielectric layer. The interconnect structure may have a bulk metal and a barrier layer. The barrier layer may be disposed between the bulk metal and the dielectric layer. The barrier layer may include one or more metals selected from iridium, platinum, palladium, rhodium, osmium, gold, silver, rhenium, ruthenium, tungsten, and nickel.

Abstract: A pad part of a semiconductor device includes a semiconductor substrate having a pad forming region; a plurality of dot type stack patterns with a dielectric layer and a conductive layer for option capacitors, formed in the pad forming region and arranged at regular intervals; a first interlayer dielectric formed on the semiconductor substrate to cover the stack patterns; first metal lines formed on the first interlayer dielectric to be connected to the stack patterns arranged in diagonal directions; a second interlayer dielectric formed on the first interlayer dielectric to cover the first metal lines; second metal lines formed on the second interlayer dielectric to be brought into contact with the first metal lines; a pad formed on the second interlayer dielectric; and option metal lines formed on the second interlayer dielectric to connect the second metal lines and the pad to each other.

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract: One aspect is a composite board including semiconductor chips in semiconductor device positions and a plastic housing composition partly embedding the semiconductor chips. A mould is provided for surrounding the semiconductor chips with plastic housing composition, the mould having a lower part and an upper part and a moldings cavity and the molding cavity having an upper contact area, which forms an interface with the top side of the plastic housing composition to be applied. The upper contact area is covered with a parting layer having essentially the same surface constitution and the same thermal conductivity as an adhesive film forming an interface with the underside of the plastic housing composition, with the result that a warpage of the composite board of less than 1% is obtained.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are laminated alternately, and first and second terminal electrodes arranged on the multilayer body. The first terminal electrode is electrically connected to the first inner electrodes. The first terminal electrode includes one or a plurality of resistance layers having a resistivity greater than that of the first inner electrode. The one or a plurality of resistance layers cover end portions of lead portions of the first inner electrodes exposed at the side face. Each resistance layer has a width wider than the lead portion of the first inner electrode but narrower than the width of the side face formed with the first terminal electrode.

Abstract: Device with a damascene interconnect for integrated circuits with improved reliability and improved electromigration properties. The device including a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.

Abstract: Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.

Abstract: Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole.

Abstract: A layer improves adhesion between interfaces of different components in semiconductor devices. The interface of a first component includes surfaces of a circuit carrier and the interface of a second component includes contact surfaces of a plastic package molding compound. The adhesion-improving layer includes a mixture of polymeric chain molecules and carbon nanotubes.

Abstract: To prevent wires from contacting an upper device when that upper device is stacked on a device that is bonded to electrodes of a board by wire bonding, a stacked semiconductor device includes a first device bonded to a package board, wires connecting electrodes of the first device to electrodes of the package board, and a second device stacked on the first device through an adhesive member. The adhesive member has a double-layered structure composed of a first die attach film and a second die attach film softer than the first die attach film. The first die attach film prevents the wires from penetrating.

Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

Abstract: An embodiment of the invention is directed to an encapsulated semiconductor device package. The package includes a semiconductor substrate, at least one semiconductor device wherein a portion of the device is on an exposed surface of the substrate and a non-patterned layer of nanocrystalline diamond covering the portion of the device on the exposed surface of the substrate. The layer of nanocrystalline diamond covering the portion of the device is intended to provide a hermetic seal that is more reliable and efficient than traditional materials and methods used for encapsulating semiconductor devices. The layer of nanocrystalline diamond is also intended as a means to make an integrated circuit tamper-proof by virtue of the layer opacity and material hardness of the nanocrystalline diamond film.

Abstract: The invention relates to an apparatus for the treatment of gaseous effluents, such as those originating from the production of semi-conductors involving contact with a liquid. The inventive apparatus consists of: a gas/liquid contact chamber which can receive a liquid in the lower part thereof and which is topped with a gas cover, said chamber comprising means for introducing a gas to be treated and means for releasing residual gases following treatment involving contact with the liquid; turbine-type gas/liquid contacting means comprising one or more stages which ensure improved contact between the gas and the liquid, the upper part of said means being equipped with an opening for drawing the gas situated in the gas cover above the liquid; and, preferably, means for measuring the pH of the liquid.