Abstract: A display device includes: a light source; a light guide plate including a light emitting surface that emits light incident from the light source; a light source board including the light source arranged thereon, the light source board arranged in close proximity to a side surface of the light guide plate; a rear frame arranged to support the light guide plate and including a protruding portion formed on a side surface of the rear frame; a middle frame arranged to support the light guide plate and the rear frame and including a notch portion where the protruding portion of the rear frame penetrate; and a display panel whose horizontal position is regulated by the protruding portion of the rear frame penetrating the notch portion of the middle frame.

Abstract: A bulb assembly includes a shell, a holder, and a bulb, wherein the bulb and the holder are received in the shell, wherein the bulb has two conductive wires passing through the holder and being folded upward outsides. The shell is provided with a central plate extending to the bottom of the holder and separating two conductive wires from each other. Hence, there are two connecting types for electrical wires with conductive pins to insert into shell and contact with various position of the conductive wires that facilitates the utilization of the products.

Abstract: A boost converter comprising an optional RFI-filter, a boost inductor (LB), two switch transistors connected in series (t2, T3) and at least one diode (D6, D7). The boost inductor is connected in series with the switch transistors directly to the AC mains voltage for producing a boosted AC voltage. The boosted AC voltage is rectified by a voltage doubling circuit, or alternatively with a full bridge rectifier. A control circuit controls the switch transistors. By arranging the boost inductor in the AC part, the inductor can be made considerably smaller. Moreover, several diodes can be excluded, resulting in a high efficiency, especially at low mains voltages below 3 times the output DC voltage. The boost converter is suitable for a mains AC voltage of 80 to 140 V for a supply of 410 V DC.

Abstract: An inventive inverter has a semiconductor switch circuit connected to the primary winding of a transformer. The semiconductor switch circuit is respectively controlled by PWM to supply a constant current to the load connected to a secondary winding of the transformer. The inverter is capable of deliberately regulating its ac power output to the load and lowering the lower limit of the output power through control of the intermittent operation, in which an error signal for carrying out the PWM control is reduced to zero during each off-duty period. In addition, the error signal for the PWM control is slowly decreased or increased in each shift from an off-duty period to on-duty period, and vise versa, by charging or discharging the capacitor in a feedback circuit, thereby allowing slow start or slow end of the respective on-off operations for the constant current control through the PWM.

Abstract: A DC-DC converter with a direct driven synchronous rectifier is disclosed, comprising: a DC-AC converter receiving a DC voltage; a transformer having one primary winding coupled to the DC-AC converter and at least two secondary windings; a synchronous rectifier having two transistors; and an output filter coupled to the synchronous rectifier, wherein the two transistors of the synchronous rectifier are driven by the two secondary windings of the transformer, respectively.

Abstract: An improved power converter that produces reduced-levels of common-mode voltages, or even entirely eliminates such voltages, is disclosed herein, along with a method of reducing common-mode voltages. In at least some embodiments, the improved power converter is equipped with common-mode filter inductors and a link coupling input and output ports of the power converter with one another to communicate a ground point associated with the input ports of the converter (and the source) to the load. Further, in at least some embodiments, the method includes providing common mode filter inductors as part of the converter, where the inductors are connected at least indirectly to at least one of a rectifier and an inverter of the converter, and communicating a grounded neutral from input ports of the converter to output ports of the converter by way of at least one additional linkage.

Abstract: A charge-pump voltage step-up circuit that produces a desired output voltage by stepping up an input voltage with an output capacitor combined with a plurality of stages of voltage step-up units has a voltage step-up factor switcher controlling how many stages of the voltage step-up units are operated according to a specified voltage step-up factor and a discharge controller discharging electric charge out of the charge accumulation capacitors and out of the output capacitor before the voltage step-up factor is changed. With this configuration, the voltage step-up factor can be changed without producing a reverse current from the output terminal.

Abstract: A switching power supply apparatus generates a first output voltage with a reversed polarity of an input voltage and a second input voltage of double the input voltage with the reversed polarity, and then outputs them from the first output terminal and the second output terminal. A driver circuit includes a control unit and a first switch to a sixth switch. The driver circuit repeats three charging periods in a time-division manner. The three charging periods are a first charging period during which a flying capacitor is charged with the input voltage, a second charging period in which a low-potential-side terminal of the flying capacitor is connected to a ground terminal and a first output capacitor is charged with a voltage appearing at the other end of the flying capacitor, and a third charging period in which a high-potential-side of the flying capacitor is connected with the first output terminal and a second output capacitor is charged with a voltage appearing at the other end of the flying capacitor.

Abstract: An AC-DC converter and a power supply are described.

Abstract: A power supply control apparatus and method are provided. The apparatus includes a controller outputting a first pulse width modulation (PWM) signal for supplying an electric power and a second PWM signal to be compared to the first PWM signal, a first PWM signal input unit converting the second PWM signal to a direct current (DC) signal, a second PWM signal input unit receiving the converted second PWM signal, a comparator comparing the first PWM signal and the converted second PWM signal, a switching unit generating a waveform having a voltage according to the comparison result of the comparator, a transformer transforming the voltage of the generated pulse waveform according to the switching result of the switching unit and a rectifier and voltage divider for rectifying and voltage-dividing the transforming result of the transformer, wherein the controller adjusts the second PWM signal by receiving the rectifying and voltage-dividing result of the rectifier & voltage divider.

Abstract: A power converting apparatus includes a power input part to which power is input; a power converting part converting the power input through the power input part; a converting current detecting part detecting a converting current of the power converted in the power converting part; a converting voltage detecting part detecting a converting voltage of the power converted in the power converting part; and a controlling part controlling the power converting part so that a value of power calculated by multiplication of the converting current detected in the converting current detecting part by the converting voltage detected in the converting voltage detecting part falls within a predetermined range of a preset reference value.

Abstract: An interleaved soft switching bridge power converter comprises switching poles operated in an interleaved manner so as to substantially reduce turn-on switching losses and diode reverse-recovery losses in the switching pole elements. Switching poles are arranged into bridge circuits that are operated so as to provide a desired voltage, current and/or power waveform to a load. By reducing switching turn on and diode reverse recovery losses, soft switching power converters of the invention may operate efficiently at higher switching frequencies. Soft switching power converters of the invention are well suited to high power and high voltage applications such as plasma processing, active rectifiers, distributed generation, motor drive inverters and class D power amplifiers.

Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.

Abstract: An integrated semiconductor memory has memory cells, with at least one pair of bit lines which comprises a first bit line and a second bit line, and with at least one sense amplifier which has the first bit line and the second bit line connected to it. The bit lines respectively have a first conductor track structure and a second conductor track structure, where the memory cells are respectively connected to the second conductor track structure, and where the first conductor track structure is respectively interposed between the sense amplifier and the second conductor track structure of the respective bit line and is arranged at a greater distance from the substrate area than the respective second conductor track structure.

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract: A read-only memory (ROM) is disclosed that uses the presence or absence of linear passive electrical elements, such as resistors or capacitors, to encode zeros and ones, permitting a large-area ROM to be fabricated, possibly on a flexible substrate. The ROM includes a substrate, a plurality of row conductors insulated from each other and at least partially layered on a portion of the substrate; a plurality of column conductors insulated from each other and from the row conductors and at least partially layered above or below a portion of the plurality of row conductors, a plurality of amplifiers electrically connected to the column conductors, and at least one linear passive element attached between the row conductors and the column conductors.

Abstract: A ferroelectric memory device includes a memory cell, read circuit, temperature sensing circuit, and read controller. The memory cell includes a ferroelectric capacitor. The read circuit is configured to read data from the memory cell. The temperature sensing circuit is configured to sense the ambient temperature of the memory cell. The read controller is configured to receive a temperature sensing signal from the temperature sensing circuit, and inhibit a data read operation by the read circuit when the temperature sensed by the temperature sensing circuit is higher than a preset temperature.

Abstract: Memory device and method for operating a memory device is disclosed. In one embodiment, the memory device has at least one memory cell including an active material, a current supply line, and a first switching device for switching a first current from the current supply line through the active material. The memory cell additionally comprises at least one further switching device for switching a further current from the current supply line through the active material.

Abstract: The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.

Abstract: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Abstract: A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save power. The gate and first terminals of the two capacitors preferably share the same conductive line such as a polysilicon segment. A second transistor and a second set of capacitors store the complementary state of the logic state so that complementary signals are provided for detecting the stored logic state. After the time for power down has ended, the state of the semiconductor storage device made up of the two transistors and four capacitors is sensed, and the detected logic state is loaded back into the latching type circuit.

Abstract: A first gate of a multi-gate transistor within a pass gate can be provided with a bias voltage to alter the bias point of the multi-gate transistor. The bias point can be controlled differently during different phases of memory cell operation and the bias point can provide operational improvements during each phase of memory cell operation. In a specific configuration the multi-gate semiconductor device has a first current electrode connected to a first node of a bit cell, a second current electrode connected to a bit line, and a second gate electrode connected to a read/write line, wherein the control module can alter the bias point of the multi-gate semiconductor differently during different phases of memory cell operation. In one embodiment a FinFET can be connected in a parallel configuration with the multi-gate transistor.

Abstract: An SRAM device is disclosed, which comprises a plurality of rows of SRAM cells and a line-buffer SRAM cell. Each row of SRAM cells is controlled by a word line. The line-buffer SRAM cell is coupled to the rows of SRAM cells and controlled by a read enable line. The signal on the read enable line is activated after the signal on the word line is activated, and part of the activated signal on the read enable line overlaps with the activated signal on the word line. The power provided to the line-buffer SRAM cell is selectively cut off. Alternatively, the power provided to the line-buffer SRAM cell is cut off when the signal on the read enable line is deactivated.

Abstract: This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.

Abstract: An embodiment of the invention relates to a device for memorisation of a memory bit, provided with a bistable circuit with complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract: According to an aspect of the invention, there is provided, a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor formed at a high potential power supply side and a first N-channel MOS transistor formed at a low potential power supply side, a second inverter being composed of a second P-channel MOS transistor formed at the high potential power supply side and a second N-channel transistor formed at the low potential power supply side, an input of the second inverter connecting with an output of the first inverter, an output of the second inverter connecting with an input of the first inverter, a data-retaining portion having a third N-channel MOS transistor and a fourth N-channel MOS transistor, the third N-channel MOS transistor having a source connecting with the output of the first inverter, a drain connecting with a first bit line, a gate connecting with a word line and the fourth N-channel MOS transistor having a source connecting with the output of

Abstract: A magnetic random access memory according to an embodiment of the present invention comprises first and second write lines which cross each other, and a magnetoresistive element whose center point is not overlapped onto a cross portion of the first and second write lines, wherein a center line of the magnetoresistive element in a direction of easy magnetization and center lines of the first and second write lines form a triangle.

Abstract: A magnetic memory includes a diode as an access device instead of MOS transistor and a magnetoresistive storage serves as a storage element, wherein the diode has four terminals, the first terminal is connected to a read word line, the second terminal serves as a storage node, the third terminal is floating, the fourth terminal is connected to a bit line, and wherein the magnetoresistive storage includes MTJ (magnetic tunnel junction) stack, the first electrode of the stack is connected to the storage node, the second electrode of the stack is connected to a free magnetic layer which serves as a resistor line, those electrodes are isolated by insulation layer, and the stack is coupled to a pinned magnetic layer which serves as a write word line. The diode also serves as a current amplifier with controlling the storage node through the storage element when the resistor line is asserted to measure the resistance of the storage element during read.

Abstract: In an example, a determination circuit 5 determines whether an input waveform is a first waveform (=0) or a second waveform (=1). When magnetization switching is caused during writing, the second waveform (=1) having a large voltage change is outputted, and thus the determination circuit 5 determines that the output waveform is the second waveform, using threshold determination or the like. In another example, when an initial voltage V1 agrees with a voltage V2 stored by intentionally writing “0”, “0” is outputted; when V1 disagrees with V2, “1” is outputted. In the disagreement case, the written data is rewritten into the original data “1.

Abstract: A magnetic switching element according to an example of the present invention includes a magnetic element, first and second electrodes which put the magnetic element therebetween, a current control section which is connected to the first and second electrodes, the current control section controlling a magnetization direction of a magnetization free section in such a manner that a current is made to flow between the magnetization free section and the magnetization fixed section, a movable conductive tube having a fixed end and a free end, and a third electrode connected to the fixed end of the conductive tube. A switching operation is performed in such a manner that a spatial position of the conductive tube is caused to change depending on the magnetization direction of the magnetization free section.

Abstract: A device is disclosed having a first Field Effect Transistor having a channel region controlled by a gate, a second Field Effect Transistor having a first channel region substantially controlled by a first gate, and a second channel region substantially controlled by a second gate. The gate of the first Field Effect Transistor and the first gate of the second Field Effect Transistor are coupled to a memory write line. The second gate of the second Field Effect Transistor receives a control signal from a memory bit cell.

Abstract: A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

Abstract: A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.

Abstract: A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.

Abstract: A data recording system of a semiconductor integrated circuit device having a memory area is disclosed. The semiconductor integrated circuit device is equipped with a memory area that includes a binary area and a multi-level area. The semiconductor integrated circuit device records, in the binary area, data transmitted from a host device as binary data. Further, when no access is provided from the host device, the semiconductor integrated circuit device copies, to the multi-level area, the data recorded in the binary area as multi-level data.

Abstract: An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector memory for storing the sectors and word lines corresponding to each sector.

Abstract: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

Abstract: A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

Abstract: The method for programming/erasing a non volatile memory cell device includes at least one electric stress step to apply, to at least one active oxide layer of at least one memory cell of the device, a stress electric field able to remove at least a part of charges trapped in the active oxide layer. The method may be used for devices with floating gate type memory cells. The electric stress step may include the application, to one or more terminals of at least one memory cell, of potentials able to produce an electric field on a corresponding active oxide layer.

Abstract: DRAM includes a small capacitor as a storage device, a write MOS transistor as a write device, and a diode as a read device; the diode includes four terminals, the first terminal serves as a read word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; the diode can be composed of the parasitic bipolar transistor of the write MOS transistor with attaching one more terminal; the diode and the write MOS transistor can be formed from thin-film layer, thus multiple memory cells are stacked; the heavy routing lines are driven by the bipolar drivers which are part of the invention; the bipolar drivers and the control MOS transistors of the peripheral circuit can be formed from the thin-film transistor; hence the whole chip can be stacked over the wafer, such as silicon, quartz and others; additionally it applications are extended to a multi port memory and a content addressable memory.

Abstract: An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.

Abstract: In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.

Abstract: A non-volatile memory device includes a polarity of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target memory cell in the array, as well as the drain and/or source nodes of unselected memory cells in the array. The multiple pre-charge paths decrease the current through the array cells and also decrease the pre-charge and set up times for the array.

Abstract: A method for resetting threshold voltage of a non-volatile memory is provided. The method is suitable for a non-volatile memory having a plurality of memory cells. Each memory cell includes a gate and a charge trapping layer. The method includes erasing the non-volatile memory by Fowler-Nordheim (FN) tunneling effect until erasure saturation. The non-volatile memory has a uniform saturation threshold voltage.

Abstract: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract: The present invention provides a SONOS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and erasing operation characteristics. In the erasing method, first electrons are erased by one of Hot Hole Injection (e.g., gate-to-drain Hot Hole Injection) or tunneling in a first step, and second electrons that are not erased in the first step are erased by the other of tunneling (e.g., gate-to-body tunneling) or HHI in a second step. Preferably, a time gap intervenes between the first and second steps.

Abstract: A multi-probe for writing data to and/or reading data from a recording medium. The multi-probe includes a plurality of probes. All of the probes are working probes for writing the data to and/or reading the data from the recording medium.

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Abstract: In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.

Abstract: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.