Abstract: In order to suppress the effect due to electrons (holes) generated by incident light that cannot be prevented from entering only by means of light shielding, rather than the drain region 34 of a transistor, with respect to a majority carrier, a region 36 whose voltage is set to a value lower than the reference value of product of the voltage of a drain region and Q (unit electric charge) is provided, or a potential barrier is provided around the drain region. In such a configuration, by controlling the voltage of the periphery of the drain region 34 connected to a reflection electrode 30 to be in a floating state, photo carriers generated in the semiconductor substrate are caused to be hardly guided in the drain region 34.

Abstract: An excellent light emitting element capable of improving problems caused by a material having high light-reflectivity and susceptible to electromigration, especially Al used for the electrode. FIG. 2A depicts semiconductor light emitting element having a first and second electrodes 20 and 30 disposed at a same surface side respectively on a first and second conductive type semiconductor layer 11 and 13. In the electrode disposing surface, the first electrode 20 comprises a first base part 23 and a first extended part 24 extending from the first base part, and a plurality of separated external connecting parts 31 of the second electrode 30 arranged side by side in extending direction of the first extended part.

Abstract: A novel semiconductor device includes a plurality of light emitting diodes, a plurality of transistors, a source pad, and a plurality of wires. The plurality of transistors drive the plurality of light emitting diodes. The source pad is connected to sources of the plurality of transistors and supplies an electric current to each of the plurality of transistors. The plurality of wires connect the source pad and the sources of the plurality of transistors. The plurality of wires also provide substantially equal resistance to the electric current passing therethrough.

Abstract: Provided are embodiments of a light emitting device and fabrication methods thereof. The light emitting device can include a buffer layer provided between a substrate and a semiconductor layer incorporating a high fusion point metal. In a fabrication method of the light emitting device, the buffer layer incorporating a high fusion point metal can be formed on a substrate, and a semiconductor layer can be formed on the buffer layer.

Abstract: A compound nitride semiconductor substrate includes a substrate having a first side and a second side. A first layer overlies the first side of the substrate and a second layer overlies the second side of the substrate. The first layer includes a first group-III element and nitrogen. The second layer includes a second group-III element and nitrogen.

Abstract: It is an object of the present invention to provide a simple and reliable method for forming a rough structure having inclined side surfaces in a light emitting device, and to provide a group III nitride semiconductor light emitting device that is obtained by the method and is excellent in light extraction efficiency. The inventive group III nitride semiconductor light emitting device comprising group III nitride semiconductor formed on a substrate comprises a first layer of Ge doped group III nitride semiconductor having pits on the surface thereof, and a second layer adjoining on the first layer and having a refractive index different from that of the first layer.

Abstract: A group III nitride semiconductor light emitting element, comprising having a light emitting layer with a multiquantum well structure formed of a group III nitride semiconductor. The light emitting layer has plural well layers, and the plural well layers are formed to coincide in emission wavelength with each other.

Abstract: A semiconductor light-emitting device comprises a multilayer structure and a glass substrate. The multilayer structure includes a plurality of laminated compound semiconductor layers and generates light. The multilayer structure has a light exit face for emitting the generated light, whereas the glass substrate optically transparent to the light is bonded to the light exit face by a film made of silicon oxide.

Abstract: Light emission from a light package, such as from an LED light package, is enhanced by a system and method for adjusting the refractive index at the surface of the encapsulating material surrounding the light source. The surface refractive index is changed to better match the index within the encapsulating material with the index of the media surrounding the encapsulating material. In one embodiment, the index is adjusted by roughing the surface of the encapsulating material. In another embodiment, a separate layer is created having a corrective index of refraction. The separate layer can comprise photonic crystals, if desired. In some embodiments the adjusting will achieve a graded index of refraction.

Abstract: This invention relates to a semiconductor light-emitting device including a semiconductor light-emitting chip and a transparent carrier. The semiconductor light-emitting chip includes an active layer and transparent substrate. The active layer emits light under a bias. At least a portion of the light emitted from the active layer enters into the transparent carrier through the transparent substrate. The semiconductor light-emitting chip is coupled to the transparent carrier through the transparent substrate. The area of the transparent carrier is larger than that of the active layer.

Abstract: Methods of fabricating a light-emitting device are provided. A light-emitting device can be formed from bonding a lens including a plug and a cap to an LED package including a socket configured to receive the plug. The lens can be fabricated using an injection mold formed from a well secured to the LED package and injecting a material into the injection mold to cure into a shape of the lens. The lens can also be fabricated using a blank about the shape of the lens and machining the blank to produce the plug and the cap of the lens. The lens can be bonded to the LED package using a convex bead of adhesive deposited on the surface of the LED package and spreading the adhesive between the lens and the LED package.

Abstract: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and has a plurality of openings corresponding to the conductive regions, respectively. A conductive member fills a respective opening, and is electrically connected a respective conductive regions to an exterior circuit.

Abstract: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and has a plurality of openings corresponding to the conductive regions, respectively. A conductive member fills a respective opening, and is electrically connected a respective conductive regions to an exterior circuit.

Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.

Abstract: A light emitting diode has a base made of heat conductive material, a wire plate made of an insulation material and secured to an upper surface of the base. Conductive patterns are secured to the wire plate, and a light emitting diode element is secured to the base at an exposed mounting area. The light emitting diode element is electrically connected to the conductive patterns.

Abstract: An LED package and a fabrication method therefor. The LED package includes first and second lead frames made of heat and electric conductors, each of the lead frames comprising a planar base and extensions extending in opposed directions and upward directions from the base. The package also includes a package body made of a resin and configured to surround the extensions of the first and second lead frames to fix the first and second lead frames while exposing underside surfaces of the first and second lead frames. The LED package further includes a light emitting diode chip disposed on an upper surface of the base of the first lead frame and electrically connected to the bases of the first and second lead frames, and a transparent encapsulant for encapsulating the light emitting diode chip.

Abstract: A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a metal substrate directly bonded to a metal plate that is substantially exposed for low thermal resistance by positioning it on the bottom of the light-emitting diode structure. This metal plate can then be soldered to a printed circuit board (PCB) that includes a heat sink. For some embodiments of the invention, the metal plate is thermally and electrically conductively connected through several heat conduction layers to a large heat sink that may be included in the structure.

Abstract: A substrate with transparent conductive film which is suitable for laser patterning and can be produced with high productivity, is provided. A substrate with transparent conductive film, which comprises a glass substrate and a transparent conductive film composed mainly of indium oxide, formed thereon, wherein the average domain diameter at the surface of the transparent conductive film is at most 150 nm. Such transparent conductive film is formed by sputtering at a substrate temperature of at most 250° C. during the film deposition.

Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.

Abstract: A field effect transistor has a shifted gate such that the gate-source distance depends on the ratio of the threshold voltage to the drain voltage. In one embodiment, a switch may include two FETs: one FET in a series configuration and one FET in a shunt configuration. Providing a switch having at least one FET with a shifted gate allows increasing switching speed and decreasing insertion loss.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than the other gate. Such a FET allows tailoring the electric field in the channel region of the FET so that it is substantially uniform. The FET exhibits desirable performance characteristics, including having a constant transconductance.

Abstract: Methods and apparatus are provided. In one embodiment, a memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.

Abstract: A gate electrode of a MOS transistor connected with a word line and a bit line in an SRAM has a projection extending in a direction away from a contact electrically connecting a drain region of the MOS transistor and the bit line. A contact electrically connecting the gate electrode and the word line is provided in the projection of the gate electrode.

Abstract: A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.

Abstract: A method of manufacturing image sensor devices, in which a dielectric protecting layer is formed on a photo-receiving region before a gate of a MOS is formed. Therefore, during the subsequent processes for forming the MOS component, damage to the surface of the photo-receiving region caused by plasma or etching can be avoided, and the dark current is improved. An image sensor device manufactured by the method is also disclosed and characterized in that a part of the gate stacks over the dielectric protecting layer and the surface of the photo-receiving region is smooth to obtain good performance.

Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.

Abstract: A solid-state image sensing apparatus has a signal storage portion of a second conductivity type provided within a semiconductor substrate or a well each of a first conductivity type to store a signal charge obtained through a photoelectric conversion, a surface shield layer of the first conductivity type provided in a surface portion of the semiconductor substrate or the well which is located above the signal storage portion, a gate electrode provided over the semiconductor substrate or the well in adjacent relation to at least one end of the signal storage portion, and a drain region of the second conductivity type provided in a surface portion of the semiconductor substrate or the well which is on the side opposite to the surface shield layer when viewed from the gate electrode.

Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.

Abstract: A solid-state imaging device is provided and includes: a semiconductor substrate; a plurality of photoelectric conversion films stacked above the semiconductor layer and absorbing different wavelength regions of light; and a transmission-blocking film at least one between the plurality of photoelectric conversion films, the transmission-blocking film blocking a transmission of a particular region of light, the particular region of light having a wavelength in a region to be absorbed in a photoelectric conversion film located above and nearest to the transmission-blocking film.

Abstract: Back-illuminated photo-transistor arrays for computed tomography and other imaging applications. Embodiments are disclosed that use bipolar transistors and JFETs, either with a single photo-sensor and transistor per pixel, or multiple photo-sensors and transistors per pixel.

Abstract: A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.

Abstract: A thin-film capacitor (2) in which a lower electrode (6), a dielectric thin-film (8), and an upper electrode (10) are formed in order on a substrate (4). The dielectric thin-film (8) is made of a composition for thin-film capacitance devices. The composition includes a bismuth layer-structured compound whose c-axis is oriented vertically to the substrate and which is expressed by a formula: (Bi2O2)2+(Am?1BmO3m+1)2?, or Bi2Am?1BmO3m+3 wherein “m” is an even number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta Sb, V, Mo and W. The temperature characteristics of the dielectric constant are excellent. Even if the dielectric thin-film is made more thinner, the dielectric constant is relatively high, and the loss is small. The leak characteristics are excellent, the break-down voltage is improved and the surface smoothness is excellent.

Abstract: a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads. The center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts.

Abstract: Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract: The present invention provides methods and apparatuses for a non-volatile semiconductor memory device. A non-volatile semiconductor memory device having multiple layers to provide a source, a drain, and a floating gate, comprising a plurality of metal layers to provide interconnects to the non-volatile memory wherein at least two of the plurality of metal areas on one or more layers are configured to provide a capacitor having a capacitance that is capacitively coupled to the floating gate.

Abstract: Disclosed is a phase change memory device comprising: a semiconductor substrate formed with a first insulating interlayer having a contact hole; a lower electrode formed within the contact hole of the first insulating interlayer; an insulating layer pattern formed on the lower electrode in such a manner so as to be sized smaller than the lower electrode, thereby exposing an edge portion of the lower electrode; a phase change layer formed in such a manner so as to cover the insulating layer pattern and come in contact with the exposed edge portion of the lower electrode; and an upper electrode formed on the phase change layer.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.

Abstract: An SOI substrate is comprised of a support substrate, a buried insulating layer and a semiconductor layer. A 1poly-type memory cell has a pair of source/drain regions, a floating gate electrode layer, and a control gate impurity diffusion region. An isolation insulating layer extends from a surface of the semiconductor layer to reach the buried insulating layer while surrounding the periphery of the control gate impurity diffusion region thereby to separate a region in which the source/drain regions are formed and the control gate impurity diffusion region from each other. Therefore, a nonvolatile semiconductor can be obtained which can prevent a parasitic bipolar operation and is suitable for higher integration.

Abstract: A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode provided above the charge storage layer, a second insulating film provided between the control gate electrode and the charge storage layer, the second insulating film between adjacent charge storage layers including a first region having permittivity lower than that of the second insulating film on a top surface of the charge storage layer in a cross-section view of a channel width direction of the nonvolatile memory cell, and the first region having composition differing from that of the second insulating film on the top surface of the charge storage layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

Abstract: First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

Abstract: A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming operations to this memory structure, a voltage is applied to the source or a back bias is applied to the substrate of the transistor to greatly reduce the current requirement of a single-gate EEPROM device. When performing erase operations, the drain voltage is raised, and a small voltage is added to the gate to increase the F-N tunneling current, thereby accomplishing the effect of fast erase.

Abstract: A power semiconductor package that includes at least two semiconductor devices electrically coupled to one another through a common metallic web.

Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of terminal trench 62.

Abstract: A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.