Abstract: An organic light emitting device which has an anode, i.e. a lower electrode, made of a single metal layer in a top emission structure, and a method of fabricating the same are provided. The organic light emitting device is constructed with a substrate, an anode disposed on the substrate and including a metal, a metal fluoride layer disposed on the anode, an organic layer disposed on the metal fluoride layer and including at least an organic emission layer, and a cathode disposed on the organic layer.

Abstract: Provided is a method of forming a fine pattern having a pattern dimension of 1 ?m or less, repeatedly with reproducibility. The method of forming the fine pattern includes: forming an azobenzene-functionalized polymer film on an etched layer; irradiating the azobenzene-functionalized polymer film using an interference laser beam to form a patterned azobenzene-functionalized polymer film having fine-patterned surface relief gratings by a photophysical mass transporting of the azobenzene-functionalized polymer; etching the etched layer using the azobenzene-functionalized polymer film having the surface relief grating patterns as an etching mask; and removing the patterned azobenzene-functionalized polymer film.

Abstract: A serial magnetic mass storage device and associated data storage method of the kind in which data is encoded in single magnetic domains in nanowires. In the invention, the nanowires are provided with a large number of notches along their length to form domain wall pinning sites. Moreover, the notches are addressed in groups (A, B, C) by heating electrodes. By alternately heating the notches hosting head-to-head and tail-to-tail domain walls in synchrony with alignment and anti-alignment of an operating field (H) along the nanowire the magnetic domains are moved along the nanowire by alternate movement of the head-to-head and tail-to-tail domain walls in caterpillar or worm-like motion in which the domains are incrementally lengthened and shortened by one inter-notch distance as they move along the nanowires under the joint coordinated action of the heating and alternating operating field.

Abstract: A light emitting composition includes a light-emitting lumophore-functionalized nanoparticle, such as an organic-inorganic light-emitting lumophore-functionalized nanoparticle. A light emitting device includes an anode, a cathode, and a layer containing such a light-emitting composition. In an embodiment, the light emitting device can emit white light.

Abstract: An organic semiconductor crystalline film and weak oriented epitaxy growth preparation method thereof. The organic semiconductor crystalline film is a n-type semiconductor or a p-type semiconductor, and organic semiconductor crystal molecules in the organic semiconductor crystalline film are oriented in a stand-up manner on the ordered substrate, and have an oriented relationship with the ordered substrate. The organic semiconductor crystalline film prepared by the present invention is useful for organic transistor and organic phototransistor devices. The method of the present invention can control the high carrier mobility direction of organic semiconductor crystals to have ordered orientation in the film, enhance contacts between crystals, improve mechanical strength and micro-machining property of the film, and give a high carrier mobility. The carrier mobility of weak oriented epitaxially grown film of the present invention is 0.

Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relief the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

Abstract: A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region and connected to at least one pad of an integrated circuit chip and the wafer substrate to establish electrical connection during electrostatic discharge and prevent ESD damage. The pad and substrate are isolated during tested of the integrated circuit chips in the wafer. Preferably, the external region is removed when the integrated circuit chips are diced from the wafer.

Abstract: A semiconductor device having a microstructure and a method of manufacturing a microstructure are provided, suppressing any change of characteristics in a wafer state caused in an assembly step. Specifically, a wafer where a plurality of microstructure chips are formed and a dummy wafer are attached to each other using an adhesive layer. As to an MEMS device, a cut dummy wafer is used as a mount for a chip and the dummy wafer and a housing member are attached to each other. Thus, the dummy wafer absorbs any stress or the like applied from below when the housing member is used for packaging.

Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.

Abstract: A thin film transistor array panel includes a substrate with a plurality of gate lines and data lines crossing each other, wherein the gate lines and the data lines define pixel groups each including a plurality of pixels, and a plurality of thin film transistors are connected to the gate lines and the data lines and include an organic semiconductor, wherein the thin film transistors from adjacent pixels of different pixel groups are disposed proximate to one another.

Abstract: A liquid crystal display device includes a first substrate and a second substrate facing each other having a pixel region; a color filter layer on the first substrate corresponding to the pixel region; a planarization layer on the color filter layer having a groove; a common electrode on the planarization layer; a pixel electrode on the second substrate; and a liquid crystal layer between the common electrode and the pixel electrode.

Abstract: A liquid crystal display device includes: a liquid crystal panel; a horizontal sync signal having a horizontal period; a gate driver that supplies a plurality of gate signals sequentially to a plurality of gate lines, wherein a first gate line provides a gate signal with a gate pulsewidth equal to the horizontal period +? and a second gate line provides a gate signal with a gate pulsewidth equal to the horizontal period +? so that gates signals on the first and second gate lines overlay by 2? and wherein the first and second gate lines are adjacent to one another; and a data driver that supplies pixel data signals to a plurality of data lines on the liquid crystal panel during every period of the horizontal sync signals.

Abstract: The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel.

Abstract: A thin film transistor array substrate structure. The array substrate structure includes a thin film transistor array substrate, an organic material layer formed thereon, and a plurality of black matrices and color filter patterns disposed on the organic material layer. The invention also provides a method of fabricating the thin film transistor array substrate.

Abstract: A thin film transistor includes a semiconductor pattern disposed on a substrate and a semiconductor pattern portion with a conductive or nonconductive characteristic, and a anti-diffusion portion on a side of the semiconductor pattern portion to prevent metal ions from being diffused along the semiconductor pattern portion. A first insulating layer covers the semiconductor pattern and has a first contact hole exposing a first region of the semiconductor pattern portion and a second contact hole exposing a second region of the semiconductor pattern portion. A gate electrode is disposed on the first insulating layer. A second insulating layer covers the gate electrode and has a third contact hole exposing the first region and a fourth contact hole exposing the second region. A source electrode is formed on the second insulating layer and connected to the first region, and a drain electrode is formed on the second insulating layer and connected to the second region.

Abstract: A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

Abstract: A liquid crystal display panel capable of preventing flicker and improving reflectance include a thin film transistor substrate having a gate line, a data line, a thin film transistor connected to the gage and data lines, and a reflective electrode connected to the thin film transistor and covering at least part of the gate line, a color filter substrate having a color filter and a common electrode forming an electric field with the reflective electrode. Liquid crystals are disposed between the thin film transistor substrate and the color filter substrate. The reflective electrode shields the liquid crystals from a gate signal.

Abstract: A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and drain electrodes on the active layer, spaced apart from each other and each having inner sides that face each other, wherein the source electrode is connected to the data line, ohmic contact layers between the active layer and each of the source and drain electrodes, a shielding pattern over the active layer and having outer sides, wherein at least one of the outer sides faces at least one of the inner sides of the source and drain electrodes, and a pixel electrode in the pixel region and connected to the drain electrode.

Abstract: A poly-silicon thin film transistor array substrate includes a gate line and a gate electrode over a substrate, a semiconductor layer having source/drain regions doped with impurity ions, a data line crossing the gate line, and source/drain electrodes connected to the source/drain regions, and a pixel electrode connected to the drain electrode, wherein the semiconductor layer is poly-silicon except for a amorphous silicon region below the gate line.

Abstract: The present invention provides a method for manufacturing a display device having a TFT that can be operated at high speed while using a small number of photomasks and improving the utilization efficiency of materials, where the threshold value is difficult to be varied. In the invention, a catalytic element is applied to an amorphous semiconductor film and the amorphous semiconductor film is heated to form a crystalline semiconductor film. After removing the catalytic element from the crystalline semiconductor film, a top-gate type thin film transistor with a planar structure is manufactured. Moreover, by using the droplet discharging method where an element of a display device is formed selectively, the process can be simplified, and loss of materials can be reduced.

Abstract: A large number of pixels PXL are arranged in a matrix fashion in a display region DSP on an insulating substrate. Disposed around the display region DSP are a drain-side pixel-driving circuit including a drain shift register DSR, a digital-to-analog converter circuit DAC, a drain level shifter DLS, a buffer BF and sampling switches SSW; and a gate-side pixel-driving circuit including a gate shift register GSR and a gate level shifter GLS, and various kinds of circuits. Current mobility of thin film transistors constituting a circuit region SX requiring high-speed operation of these pixel-driving circuits is improved by optimizing a combination of plural layouts, arrangements and configurations for the respective circuits to meet the specifications special for the respective circuits.

Abstract: An electron emitter according to the present invention includes: an area in which a surface of the substrate is exposed or an area in which the inner surface of the substrate is exposed; the SiC substrate with the (0001) surface as a principal surface; the electron emission layer has carbon formed on the substrate surface C; and the electron formed on the area. In addition, the electrode may be formed on the substrate Si surface. Furthermore, the electron emission layer may be formed on a part of the substrate surface C. The electrode may be formed on the area, of the substrate C surface, on which the electron emission layer is not formed.

Abstract: A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a highly doped second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4).

Abstract: Provided is a monocrystalline silicon carbide ingot containing a dopant element, wherein a maximum concentration of the dopant element is less than 5×1017 atoms/cm3 and the maximum concentration is 50 times or less than that of a minimum concentration of the dopant element. Also provided is a monocrystalline silicon carbide wafer made by cutting and polishing the monocrystalline silicon carbide ingot, wherein a electric resistivity at room temperature of the wafer is 5×103 ?cm or more. Further provided is a method for manufacturing the monocrystalline silicon carbide including growing the monocrystalline silicon carbide on a seed crystal from a sublimation material by a sublimation method. The sublimation material includes a solid material containing a dopant element, and the specific surface of the solid material containing the dopant element is 0.5 m2/g or less.

Abstract: A semiconductor light emitting element array includes a substrate made of SiC and having a first surface and a second surface opposite to the first surface. The array also includes a plurality of semiconductor light emitting elements supported by the first surface of the substrate. Each of the light emitting elements includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The second surface of the substrate serves as a light emitting surface, from which light produced by the light emitting elements is emitted out.

Abstract: A silicon carbide semiconductor device is provided with a semiconductor substrate (20) of silicon carbide of a first conductivity type, a hetero semiconductor region (60) forming a hetero-junction with the semiconductor substrate (20), an insulated gate including a gate electrode (40) and a gate insulator layer (30) formed on the semiconductor substrate (20) and adjoining to the hetero semiconductor region (60), a source electrode (80) electrically connected to the hetero semiconductor region (60) and a drain electrode (90) electrically connected to the semiconductor substrate (20).

Abstract: A wavelength converting material including a wavelength converting activator and a scatter is provided. The wavelength converting activator is suitable for being activated by a light with a wavelength ?1, so as to emit a light with a wavelength ?2. The scatter is disposed on the wavelength converting activator. The scatter is suitable for scattering a first light and a second light irradiated to a surface thereof. As a result of that the scatters on the wavelength converting activators increases the gap of two wavelength converting activators adjacent to each other, the wavelength converting activators could be sufficiently activated for emitting a light with wavelength ?2 while the wavelength converting materials are irradiated by the light with ?1. Therefore, the brightness of a light emitting diode with the wavelength converting material is enhanced.

Abstract: Primary electrodes process and installation for manufacturing of LED multi-layer metals comprised of having epitaxial wafer cleaned up and placed in the manufacturing installation to undergo multi-metal electrodes process; installation include a loader, a magnetic device, a carrier, a magnetic mask, and multiple-layer metal sources for epitaxial wafer loaded by the carrier to form multiple metal electrodes through deposition of contact window adapted to the magnetic mask using the metal coating deposition method.

Abstract: A semiconductor optical wave guide device is described in which a buried oxide layer (BOX) is capable of guiding light. Optical signals may be transmitted from one part of the semiconductor device to another, or with a point external to the semiconductor device, via the wave guide. In one example, an optical wave guide is provided including a core insulating layer encompassed by a clad insulating layer. The semiconductor device may contain an etched hole for guiding light to and from the core insulating layer from a transmitter or to a receiver.

Abstract: Both ends of the lead arrangement project outward from side surfaces of a package to form outer lead regions. Each of the outer lead regions includes a pair of outer lead projections and lead terminal smaller projections that are located between the outer lead projections. The outer lead projections and lead terminal smaller projections project outward. Adjustment is made to the projection amount of end surfaces of the lead smaller projections lying in a plane perpendicular to a longitudinal direction of the lead arrangement, whereby the end surfaces projecting less than end surfaces of the outer lead projections. Thus, cut surfaces of lead connection portions with edged corners are not exposed. This arrangement prevents that the cut surfaces damage other devices.

Abstract: A semiconductor device manufacturing method can produce semiconductor light emitting/detecting devices that have high connective strength and high luminous energy by increasing contact areas of electrodes thereof and decreasing enclosed areas of electrodes thereof. A wafer is provided with a semiconductor substrate and a semiconductor epitaxial layer. A plurality of substrate concave portions and epitaxial layer concave portions are formed on the semiconductor substrate and the semiconductor epitaxial layer, respectively. Substrate electrodes and epitaxial layer electrodes are formed in the substrate concave portions and the epitaxial layer concave portions. A substrate surface electrode and an epitaxial layer surface electrode can be formed on the semiconductor substrate and the substrate electrodes and the semiconductor epitaxial layer and the epitaxial layer electrodes, respectively.

Abstract: A semiconductor light emitting device having a multiple pattern structure greatly increases light extraction efficiency. The semiconductor light emitting device includes a substrate and a semiconductor layer, an active layer, and an electrode layer formed on the substrate, a first pattern defining a first corrugated structure between the substrate and the semiconductor layer, and a second pattern defining a second corrugated structure on the first corrugated structure of the first pattern.

Abstract: An inclined surface having an inclination angle ? is formed in an edge portion which forms an opening portion of an inter-layer insulating film, thereby reducing a stress by the inclined surface.

Abstract: Embodiments of a light emitting device and a method for fabricating the same are provided. The light emitting device comprises a cavity and one or more light emitting elements. The cavity is formed to a depth of 450 ?m or less, and the light emitting elements are installed in the cavity. A fabricating method includes forming a package body having a cavity with a depth of 250 ?m to 450 ?m and at least one lead frame disposed at the bottom surface of the cavity, mounting at least one light emitting element on the lead frame, and molding a molding member in the cavity.

Abstract: A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.

Abstract: A full color LED display, comprised a plurality of full color luminant units, is characteristic of: each of the full color luminant units comprises four LEDs distributed in a cross type; each of the LEDs has a polygon top; each space between any two adjacent LEDs of the LEDs is smaller than or equal to 1.2 millimeters; and each space between any two adjacent full color luminant units of the full color luminant units is smaller than or equal to 8 millimeters. The full color luminant unit comprises two red LED, one green LED and one blue LED while the LEDs are full-length LEDs. Moreover, a LED panel's virtual pixel technology is applied for the full color LED display so that the full color LED display has higher image density, better signal mixing, and higher resolution thereof.

Abstract: A light emitting device is provided which has a reflector having a reflection surface made of porous alumina having an apparent density of 2.5 to 3.3 g/cm3, and an LED disposed on the reflection surface or near the reflection surface. There are provided: a light emitting device equipped with an LED chip and a reflector having a high reflectivity relative to near infrared to ultraviolet rays irradiated from an LED chip and fluorescent material; and the reflector.

Abstract: A light emitting device includes a package having a recessed portion defined by a bottom surface and a side surface and a light emitting element mounted on the bottom surface of the recessed portion, in which the package has fibrous fillers, and at least some of the fillers are projected outwards through the side surface and coated with a reflection film made of metal.

Abstract: A mounting substrate includes a peripheral portion and a central portion. Solid state light emitting elements are provided on the mounting substrate. A housing is configured to thermally couple to the peripheral portion of the mounting substrate, so as to provide a first thermal conduction path for at least some heat generated by the solid state light emitting elements. A thermal conduction member is configured to thermally couple the central portion of the mounting substrate to the housing, so as to provide a second thermal conduction path that is different from the first thermal conduction path, for at least some heat generated by the solid state light emitting elements. Related assembling methods are also described.

Abstract: An LED chip of the present invention has a structure in which an n-type semiconductor layer and a p-type semiconductor layer are successively formed on the lower face of an element substrate, with the p-type semiconductor layer being formed on an area except for an area for an n-electrode. A first n-electrode is formed on the area for the n-electrode and a first p-electrode is formed on the p-type semiconductor layer. A first insulating layer having openings and is formed on the first n-electrode and the first p-electrode, and a second n-electrode and a second p-electrode having virtually the same size are formed on the first insulating layer. With this arrangement, the electrode on the n-type semiconductor layer can be made larger, thereby a mounting process of LED chips onto a circuit board can be executed by using solder at low costs.

Abstract: A light emitting diode is disclosed. The diode includes a package support and a semiconductor chip on the package support, with the chip including an active region that emits light in the visible portion of the spectrum. Metal contacts are in electrical communication with the chip on the package. A substantially transparent encapsulant covers the chip in the package. A phosphor in the encapsulant emits a frequency in the visible spectrum different from the frequency emitted by the chip and in response to the wavelength emitted by the chip. A display element is also disclosed that combines the light emitting diode and a planar display element. The combination includes a substantially planar display element with the light emitting diode positioned on the perimeter of the display element and with the package support directing the output of the diode substantially parallel to the plane of the display element.

Abstract: The disclosed subject matter relates to a light emitting semiconductor apparatus with reduced color unevenness and suppressed topical deterioration over time with regard to an amount and chromaticity of the illuminating light. The light emitting semiconductor apparatus of the disclosed subject matter can include three separate bonding pads. Among those, the centrally located bonding pad is die bonded to two types of light emitting devices which have an identical material and structure and almost equal sizes, but are different in orientation and direction characteristic of PN-electrodes. The bonding pad located in an outermost location is die-bonded to the light emitting device. In this case, the direction characteristic of a central light emitting device exhibits a substantial reverse conical form while the direction characteristic of the light emitting device exhibits a substantial conical form.

Abstract: A vertical light-emitting diode (VLED) structure with a eutectic layer is described. The eutectic layer improves the heat conductivity of the device, thereby leading to increased brightness and higher luminous efficiency. The eutectic bonds of this layer also improve the reliability of the VLED structure since they have a lower coefficient of thermal expansion (CTE). A metal protective layer may be included to prevent diffusion of the eutectic layer thereby increasing the reliability and lifetime of the VLED structure. A reflective layer and/or a patterned surface may be added to this structure to further enhance the emitted light and increase the luminous efficiency.

Abstract: A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such a semiconductor light emitting device may be formed by growing an n-type region, growing a p-type region, and growing a light emitting layer disposed between the n-type region and the p-type region. The difference in temperature between the growth temperature of a part of the n-type region and the growth temperature of a part of the p-type region is at least 140° C.

Abstract: A semiconductor apparatus includes an electrostatic protective device having PN junction with N-type Si and P-type SiGe. The electrostatic protective device is directly connected with a terminal to receive static electricity and with a terminal to discharge static electricity.

Abstract: An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire.

Abstract: A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.

Abstract: A display substrate having a high aperture ratio includes gate and source metallic patterns, first and second gate insulating layers, and a pixel electrode. The gate metallic pattern includes a gate line, a gate electrode and a first storage electrode. The first gate insulating layer covers at least one of the gate electrode and the first storage electrode. The second gate insulating layer is patterned to expose the first gate insulating layer on the first storage electrode. The source metallic pattern includes a second storage electrode contacting a source line and the first gate insulating layer on the first storage electrode. The pixel electrode is electrically connected to a switching element. Therefore, the display substrate having the high aperture ratio may be obtained to enhance luminance of a display image.

Abstract: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 ?; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 ?.