Patents Issued in November 15, 2007
  • Publication number: 20070262449
    Abstract: The present invention concerns a methods and compositions for preparing a multi layer composite device, such as a semiconductor device. Said method comprises (A) forming a dielectric layer on the surface of a composite material by bringing said surface into contact: a) either with a solution, comprising the diazonium salt of aniline, a diazonium salt bearing at least one functional group or an amine compound of formula H2N-A-X-Z as defined in claim 1: b) or with a first solution containing an aryl diazonium salt and successively a second solution containing a compound bearing at least one functional group and bearing at least one functional group capable of reacting with the aryl radical grafted on the surface of the composite material thanks to the aryl diazonium salt; (B) forming an overlayer on said surface of said composite material obtained in step (A), said overlayer consisting of a Si-containing dielectric Cu-Etch Stop Layer and/or copper diffusion barrier.
    Type: Application
    Filed: March 5, 2007
    Publication date: November 15, 2007
    Applicant: ALCHIMER
    Inventors: Isabelle Bispo, Nathalie Thieriet, Paolo Mangiagalli
  • Publication number: 20070262450
    Abstract: A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N?1 electrically conductive regions to touch the electrically conductive layer.
    Type: Application
    Filed: April 21, 2006
    Publication date: November 15, 2007
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
  • Publication number: 20070262451
    Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Inventors: Willy Rachmady, Brian McIntyre, Michael Harper, Subhash Joshi
  • Publication number: 20070262452
    Abstract: In an electronic component built-in substrate of the present invention, an electronic component is mounted on a mounted body having a first wiring layer, the electronic component is embedded in an insulating layer, a conductive ball is arranged to pass through the insulating layer and connected electrically to the first wiring layer, a second wiring layer connected electrically to the conductive ball is formed on the insulating layer, and the first wiring layer and the second wiring layer are interlayer-connected via the conductive ball.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 15, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.,
    Inventor: Kiyoshi Oi
  • Publication number: 20070262453
    Abstract: In a semiconductor device, a plurality of triple-stacked structures all having the same structure are provided. Each of the triple-stacked structures includes one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 15, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takeshi Toda
  • Publication number: 20070262454
    Abstract: An area with a low via pattern density is extracted from a semiconductor integrated circuit that includes the first wirings and the second wirings disposed on the upper layer of the first wirings, based on wiring layout information. Then, dummy via patterns connected either to the first wirings or the second wirings are disposed in the peripheral area of the via patterns within the selected area. With this, the dummy via can be disposed even in an area where the wirings are congested.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 15, 2007
    Inventor: Hidenori Shibata
  • Publication number: 20070262455
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 15, 2007
    Inventor: Mou-Shiung Lin
  • Publication number: 20070262456
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 15, 2007
    Inventor: Mou-Shiung Lin
  • Publication number: 20070262457
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 15, 2007
    Inventor: Mou-Shiung Lin
  • Publication number: 20070262458
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 15, 2007
    Inventor: Mou-Shiung Lin
  • Publication number: 20070262459
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 15, 2007
    Inventor: Mou-Shiung Lin
  • Publication number: 20070262460
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 15, 2007
    Inventor: Mou-Shiung Lin
  • Publication number: 20070262461
    Abstract: A semiconductor device includes a substrate; a wiring formed on the substrate; a base portion disposed at an end portion of the wiring; and an electrode formed on the base portion. The base portion has a size smaller than that of the electrode, so that the base portion is not shifted out of the electrode.
    Type: Application
    Filed: December 14, 2006
    Publication date: November 15, 2007
    Inventor: Takashi Oosumi
  • Publication number: 20070262462
    Abstract: A wiring board used for manufacturing a resin-molding type semiconductor device includes a plurality of element regions each having a mount region on which a semiconductor element is mounted and an electrode wire, and a peripheral region surrounding the plurality of element regions and having engagement parts such as through holes engaged with a resin with which the plurality of element regions and the peripheral region are sealed.
    Type: Application
    Filed: April 11, 2007
    Publication date: November 15, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiaki Shimizu, Toshiyuki Fukuda
  • Publication number: 20070262463
    Abstract: The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately 10% to 50%, and preferably about 30%, of the total height of each solder ball within its associated interconnection. Such a design compensates for under-sized or misshapen solder balls on the die under test and thereby prevents a possible false failure indication for the die under test. This design also distributes the forces on the solder ball caused by biasing the die under test to its temporary package to the periphery of the solder ball and thus reduces the likelihood of damage to the solder ball or the semiconductor substrate.
    Type: Application
    Filed: October 24, 2006
    Publication date: November 15, 2007
    Inventor: Salman Akram
  • Publication number: 20070262464
    Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 15, 2007
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Charles Watkins, Kyle Kirby, Alan Wood, Salman Akram, Warren Farnworth
  • Publication number: 20070262465
    Abstract: An MCM-type semiconductor device allowing high-speed operation and reduction in power consumption, and is also capable of preventing reliability and yield rate of MCM from degrading. The reduction in power consumption and increase in operation speed are attained by connecting signal lines between in-chip circuits (30), (32) in an electrically direct manner. On the signal line, a protection circuit (406) for electrostatic damage protection is provided. In device fabrication, connection using interconnections (12) between the in-chip circuits (30), (32) is carried out while keeping a protection circuit (406) connected to the signal lines (internal draw-out lines (12a), internal interconnections (14)), by which circuit components can be protected from static electricity even if electric charge accumulated on the semiconductor chips (20), (22) should flow into the signal lines, because the protection circuit (406) can absorb the charge.
    Type: Application
    Filed: August 11, 2004
    Publication date: November 15, 2007
    Inventor: Shin Iwabuchi
  • Publication number: 20070262466
    Abstract: A semiconductor device of the present invention includes a first semiconductor chip, a second semiconductor chip, and an adhesive layer, sandwiched between the first and second semiconductor chips, which adheres to the first semiconductor chip 2, the first and second semiconductor chips being laminated so that part of the second semiconductor chip protrudes outwards from an outer edge of the first semiconductor chip, the adhesive layer adhering to the first semiconductor chip so as to avoid an outer edge of the first semiconductor chip from which outer edge portion the part of the second semiconductor chip protrudes outwards. This makes it possible to provide a semiconductor device having a highly reliable (durable) laminated structure in which semiconductor chips are laminated.
    Type: Application
    Filed: April 10, 2007
    Publication date: November 15, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Yasuki Fukui
  • Publication number: 20070262467
    Abstract: A semiconductor device having a semiconductor chip stack on a rewiring plate is disclosed. In one embodiment, the device includes an external contact area having a plurality of external contact area regions which are physically separate from one another is arranged on the underside. The individual external contact area regions are assigned to the individual semiconductor chips in the semiconductor chip stack. The external contact regions of an individual external contact area have a common external contact which electrically connects the external contact area regions.
    Type: Application
    Filed: February 3, 2005
    Publication date: November 15, 2007
    Inventors: Christian Birzer, Jens Pohl
  • Publication number: 20070262468
    Abstract: A semiconductor device includes a first semiconductor chip having a first pad, a bonding member having a second pad facing the first pad, and a refractory metal layer which is formed by electroless plating in direct contact with the first pad and the second pad.
    Type: Application
    Filed: July 10, 2006
    Publication date: November 15, 2007
    Inventors: Hayato Nasu, Takamasa Usui
  • Publication number: 20070262469
    Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.
    Type: Application
    Filed: July 22, 2007
    Publication date: November 15, 2007
    Inventors: VICTOR 'KHNG, Lee Chai
  • Publication number: 20070262470
    Abstract: The present invention provides a module with a built-in semiconductor that can suppress a reduction in yield caused by a crack or failure of a semiconductor device in the process of mounting a thin semiconductor device on a wiring board and a method for manufacturing the module. In the module with a built-in semiconductor, a semiconductor device (107) is contained in an interlayer connection member (105) located between a first wiring board (101) and a second wiring board (103). The back side of the semiconductor device (107) is die-bonded to the first wiring board (101) via an adhesive (108), and the semiconductor device (107) is connected electrically to the second wiring pattern (104) via a protruding electrode (109).
    Type: Application
    Filed: September 20, 2005
    Publication date: November 15, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Ichiryu, Yoshihisa Yamashita, Seiichi Nakatani
  • Publication number: 20070262471
    Abstract: A method of making a double-sided antenna for high frequency devices is discussed. The method includes forming metal patterns on both sides of a substrate having pre-formed connection holes. Preferably, the metal patterns are formed using a printing ink having a precursor and a solvent. In one embodiment, the metal patterns include coils which are formed on both sides of the substrate. In one embodiment, shunt bars are used to speed up the process of making the metal patterns. The shunt bars are punched out at the end of the process to electrically isolate the metal patterns.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 15, 2007
    Inventor: James Montague Cleeves
  • Publication number: 20070262472
    Abstract: A high withstand voltage semiconductor chip mounted on a package or a board is covered with a sealing resin, and the resin is cured while a high voltage is applied between at least one of electrode terminals connected from a chip electrode or the chip via wiring of wires or the like and another electrode that necessitates a dielectric withstand voltage between the electrode and the electrode terminal during the curing. The sealing resin is provided by a synthetic high molecular compound structured in a manner that an organic silicon polymer C is constituted by alternately linearly linking an organic silicon polymer A having a crosslinking structure of siloxane with an organic silicon polymer B having a linear link structure of siloxane (Si—O—Si bond) by siloxane bond and the polymers are three-dimensionally linked together by covalent bond.
    Type: Application
    Filed: October 5, 2005
    Publication date: November 15, 2007
    Inventors: Shinichi Okada, Yoshitaka Sugawara, Katsunori Asano, Daisuke Takayama, Yoshikazu Shoji, Tadashi Janado, Takashi Sueyoshi, Ken-Ichiro Hiwatari
  • Publication number: 20070262473
    Abstract: An integrated circuit package system is provided including providing a carrier, mounting an integrated circuit die on the carrier, connecting the integrated circuit die with the carrier, and forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress.
    Type: Application
    Filed: April 13, 2007
    Publication date: November 15, 2007
    Inventors: Choong Bin Yim, Young Cheol Kim
  • Publication number: 20070262474
    Abstract: A semiconductor device is provided which is capable of suppressing decreased yields and increased costs, maintaining excellent optical characteristics, reducing secular changes in characteristics to ensure high erliability. After implanting a dopant into a polycrystalline silicon film and activating the implanted dopant and forming a source region, drain region, and channel region, a substrate is exposed to hydrogen gas plasma with a substrate temperature kept within a range between 350° C. and 420° C. and with treating time of 3 minutes to 60 minutes taken. This exposure suppresses a content of occluded water contained in silicon dioxide making up a primary protecting film, which prevents the diffusion of water being an impurity at operational temperatures of a thin film transistor and adverse characteristics on operational characteristics.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 15, 2007
    Inventors: Kunihiro Shiota, Jun Tanaka
  • Publication number: 20070262475
    Abstract: A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment feature such that the polysilicon layer reaches a first temperature. The polysilicon layer is then annealed with the substrate to raise the polysilicon layer to a second temperature higher than the first temperature. A photoimageable layer is then deposited over the polysilicon layer, after which an alignment signal including light from the alignment feature is received through the annealed polysilicon layer. Using the alignment signal passing through the annealed polysilicon layer from the alignment feature, an exposure system is aligned with the substrate with improved results.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 15, 2007
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Johnathan Faltermeier, James Norum
  • Publication number: 20070262476
    Abstract: A process for manufacturing an integrated circuit using shallow trench isolation (STI) includes a 2-step nitride removal process which, when combined with a nitride pull-back step provides, in a floating gate memory integrated circuit, a high coupling ratio and a reduction in thinning of the tunnel oxide layer in a floating gate memory integrated circuit.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Inventors: Yi Ding, Jason Taylor, Chiliang Chen
  • Publication number: 20070262477
    Abstract: An apparatus adapted to release individually into an atmosphere one of at least two volatile liquids, each liquid being in heat transfer contact with one face of a theromoelectric device, typically a Peltier device. The apparatus allows the emission of different liquids at different times.
    Type: Application
    Filed: May 4, 2005
    Publication date: November 15, 2007
    Applicant: GIVAUDAN SA
    Inventors: Colin Brown, Guy Naish
  • Publication number: 20070262478
    Abstract: An apparatus for generating aerosol comprises a capillary tube comprising at least one bend, fluid inlets, and an outlet along the bend. The capillary tube is heated to a temperature sufficient to volatilize fluid in the capillary tube, such that the volatilized fluid discharges from the outlet to form an aerosol.
    Type: Application
    Filed: January 30, 2007
    Publication date: November 15, 2007
    Applicant: Philip Morris USA Inc.
    Inventors: Shane Price, Evgeni Sychev, Marc Belcastro, Jeffrey Swepston
  • Publication number: 20070262479
    Abstract: A method for welding together two layers or workpieces within a multi-layer assembly in which laser light is directed through an outer layer of the assembly, allowing transmission of the laser light from its outer surface to at least within the vicinity of its inner surface substantially without any absorption of energy from the laser light. The laser light is directed towards a layer having an absorbent component, corresponding to a portion thereof, capable of absorbing laser light within a given wavelength range thereby creating a welded area between a surface of the layer having the absorbent component and a surface of a layer facing the layer having the absorbent component. The absorbent component can be provided either within the bulk of a layer or it can be provided as a separate surface layer on one or both surfaces of a layer.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 15, 2007
    Inventors: Kim Bager, Ingrid Fink, Thorkild Vorm
  • Publication number: 20070262480
    Abstract: An optical glass having high-refractivity and low-dispersion optical properties and having a low glass transition point so that a heat-treating furnace can be operated for a long period of time. The optical glass has a refractive index nd of at least 1.875, an Abbe's number vd of at least 39.5 and a glass transition point Tg of 700° C. or lower, and contains at least one of La2O3, Gd2O3, Y2O3 or Yb2O3 and at least one of ZrO2, Ta2O5 or Nb2O5, with a weight ratio of the total content of La2O3, Gd2O3, Y2O3 and Yb2O3 to the total content of SiO2 and B2O3 of from 3.2 to 5 and the weight ratio of the total content of ZrO2, Ta2O5 and Nb2O5 to the total content of SiO2 and B2O3 is from 1.1 to 1.5.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 15, 2007
    Applicant: HOYA CORPORATION
    Inventor: Kazuo Tachiwana
  • Publication number: 20070262481
    Abstract: It is an object of the present invention to provide a fine particle granulation method capable of granulating fine particles in an extremely easy operation without the need for carrier particles that cannot be reliably isolated and removed or binders that remain as impurities, and of improving the handling properties of these fine particles, and of obtaining fine particles that can be rapidly broken down into primary particles during use. To achieve this object, the fine particle granulation method comprises an agitation step in which fine particles are dispersed in a supercritical fluid, and a spraying step in which the supercritical fluid with the fine particles dispersed therein is subjected to rapid adiabatic expansion.
    Type: Application
    Filed: October 19, 2005
    Publication date: November 15, 2007
    Inventor: Satoru Watano
  • Publication number: 20070262482
    Abstract: The invention relates to processes for producing nanoparticles, especially pigment particles, comprising the following steps: i) bringing a base substance (1) into the gas phase, ii) generating particles by cooling or reacting the gaseous base substance (1), and iii) applying electrical charge to the particles during particle generation in step ii) in a nanoparticle generation apparatus. The invention further relates to apparatus for producing nanoparticles, having a feed line (28) for transporting the gas stream (29) into the apparatus, a particle generation and charging area for substantially simultaneous generation and charging of nanoparticles, and a takeoff line (30) for transporting the charged nanoparticles from the particle generation and charging area.
    Type: Application
    Filed: July 8, 2005
    Publication date: November 15, 2007
    Inventors: Jorg Halpap, Richard Van Gelder, Bernd Sachweh, Siegfried Welker, Norbert Wagner, Andreas Marquard, Gerhard Kasper
  • Publication number: 20070262483
    Abstract: A process for manufacturing a self-extinguishing cable including at least one transmissive element and at least one flame-retardant coating in a position radially external to the at least one transmissive element, wherein the at least one coating includes an expanded flame-retardant polymeric material having (a) at least one expandable polymer; (b) at least one expanding agent; (c) at least one flame-retardant inorganic filler, in an amount of 100 parts by weight of 250 parts by weight with respect to 100 parts by weight of the at least one expandable polymer.
    Type: Application
    Filed: December 24, 2003
    Publication date: November 15, 2007
    Inventors: Gianbattista Grasselli, Alberto Bareggi, Cristiana Scelza, Marco Frigerio, Paolo Veggetti, Sergio Belli
  • Publication number: 20070262484
    Abstract: A process for producing a multilayered unstretched film. The process is intended to minimize the amount of those thick parts of a film formed which are to be discarded, and to thereby attain a cost reduction. Thermoplastic resins (20A) and an extra thermoplastic resin (20B) different from the thermoplastic resins (20A) are separately melted by heating. Immediately before widening in respective manifolds, the extra thermoplastic resin is introduced to each edge part of each of the objective thermoplastic resins. The resins are fed to and widened in the manifolds so that the extra thermoplastic resin is disposed on the side of each edge of each objective thermoplastic resin. Subsequently, the melts are joined and ejected from the die lip of the T-die on a casting roll.
    Type: Application
    Filed: February 25, 2005
    Publication date: November 15, 2007
    Applicant: Tokyo Kohan Co., Ltd.
    Inventors: Tadashi Fujii, Takuji Nakamura, Hiroshi Inazawa, Yasuhiro Matsubara
  • Publication number: 20070262485
    Abstract: An insulation material having insulative properties of a synthetic down, while have a fir-tree structure more similar to natural down, and being in a blown form. The blowable insulation material is composed of plural units each having a number of filaments that are fused at one end of the unit and are open at an opposite end.
    Type: Application
    Filed: July 18, 2007
    Publication date: November 15, 2007
    Inventors: Trent Davis, Victor Laskorski
  • Publication number: 20070262486
    Abstract: A cover assembly for an internal combustion engine application and method of construction therefore provides one construction for a valve cover assembly, and another construction for an end cover assembly for a crankcase. The cover assemblies include at least one rigid metal carrier having a plurality of bolt openings and a plurality of load limiters located about said openings. A material is overmolded on the carrier and about the load limiters, with the material forming an exposed sealing surface for direct engagement with a seal gasket.
    Type: Application
    Filed: February 9, 2007
    Publication date: November 15, 2007
    Inventors: Robert Waters, David Hurlbert
  • Publication number: 20070262487
    Abstract: A frame is injection molded onto a group of panels to form a container. The panels extend at least partially around, and at least partially define, a cavity of the container.
    Type: Application
    Filed: March 8, 2007
    Publication date: November 15, 2007
    Inventors: Brian O'Hagan, Peter Blaas, Scott Middleton, Kevin Hjort, Bruce Barnard
  • Publication number: 20070262488
    Abstract: The present invention relates to a method for joining two vastly dissimilar materials. One embodiment provides a method for joining two materials. The method comprises generating a relative motion between a first material and a second material while pressing the first material against the second material, wherein the first material is non-metallic and the second material is metal, and holding the first material against the second material without relative motion to form a mechanical joint between the first and second materials.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Inventor: Hung Chen
  • Publication number: 20070262489
    Abstract: Apparatus for producing injection-molded parts, particularly PET preforms, includes a twin-screw extruder or multi-screw extruder for preparing and/or plasticizing material, preferably in granular form, which is transferred to a transfer reservoir. A piston unit further processes the material. The extruder has a plurality of processing zones, whereby at least two process zones are configured as degassing zones.
    Type: Application
    Filed: February 27, 2007
    Publication date: November 15, 2007
    Applicants: Berstorff GmbH, Krauss-Maffei-Kunststofftechnik GmbH
    Inventors: Gunther Fischbach, Jens Liebhold, Markus Berndt, Rainer Zimmet, Matthias Sieverding
  • Publication number: 20070262490
    Abstract: A PET resin container having an oxygen-capturing function and an improved level of oxygen barrier property is provided, with these performances being achieved by applying radiation to the container after the molding operation.
    Type: Application
    Filed: June 26, 2007
    Publication date: November 15, 2007
    Applicant: YOSHINO KOGYOSHO CO., LTD.
    Inventors: Naoyuki Kojima, Taro Enjoji, Hirohisa Yamazaki, Toshio Imai, Shuichi Koshio
  • Publication number: 20070262491
    Abstract: A method to inhibit the attack by organic acid such as acetic acid, of a thermoplastic polymer coated on a metal container body and/or end. The method includes flash heat treating the whole respective polymer coated metal parts of the container intended to come into contact with the organic acid such that the polymer on the parts is heated to above its melting temperature to make the container suitable for packaging organic acid-containing contents.
    Type: Application
    Filed: December 23, 2004
    Publication date: November 15, 2007
    Applicant: CORUS STAAL BV
    Inventors: Adrianus Den Hartog, Hendrik Breur
  • Publication number: 20070262492
    Abstract: Method for finishing a machined and cut acrylic piece to eliminate porosity of the cut and machined surfaces includes exposing all sides of the piece, then inserting the exposed piece into a heated oven, keeping the piece in the oven while the oven is maintained at a set temperature or within a set temperature range, and then removing the piece from the oven after the predetermined period of time. After this beating cycle, the machined and cut surfaces are non-stressed and therefore the acrylic piece is resistant to forming striations even when the cut and machined surfaces are exposed to oil and chemicals which cause striations in machined and cut surfaces of non-treated acrylic pieces. The predetermined period of time for heating the piece depends on a thickness of the piece and on whether the temperature in the oven environment is measured and controlled.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Applicant: RETAIL SOLUTIONS CENTER, INC.
    Inventor: Stephen Leo
  • Publication number: 20070262493
    Abstract: A method for forming a fine embossed pattern on a surface of a fastener member, wherein a mold core is formed with a mold cavity having a fastener member shape, and a layer of adhesive paper is adhered to an area of the mold cavity desired to be fashioned with an embossed decorative design, then laser engraving machining technology is used to engrave out a specific pattern on the mold cavity. Adhesive paper out of the pattern is removed, and mold texturing (electrodischarge machining) is implemented. Finally, the residual adhesive paper is torn away to reveal a non-textured fine pattern in the mold cavity, and plastic ejection molding is implemented to manufacture a fastener member having a fine embossed pattern, thereby increasing aesthetic appeal of the fastener member.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Inventor: Shih-Sheng Yang
  • Publication number: 20070262494
    Abstract: A method and an apparatus to form a sheet of polymeric material have first and second mold halves which clamp together on a polymeric sheet. A vacuum mechanism draws the sheet into an interior space. The vacuum mechanism has a plurality of controllable vacuum ports positioned about the interior space to direct the vacuum at specific portions of the sheet. Also, the sensing mechanism determines the draw depth of the sheet.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Inventor: Edwin Oakey
  • Publication number: 20070262495
    Abstract: A device and method is provided for the inline storage of water during pressurized use. The device provides a one-way valve associated with an incoming attachment point of a water tank assuring that water does not flow back through the incoming attachment point. The tank is constructed with two hemispherical caps at the ends connected by a tubular body providing structure when pressurized. The incoming attachment point is connected with the tank near the top preventing backpressure. An outgoing attachment point is connected with the tank as well.
    Type: Application
    Filed: April 9, 2007
    Publication date: November 15, 2007
    Inventor: Roger Bitner
  • Publication number: 20070262496
    Abstract: Acetalized polyvinyl alcohols having a high residual polyvinyl acetate content are suitable as use as dispersing agents in the production of ceramic green films.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 15, 2007
    Inventors: Michael FRANK, Robert Fuss
  • Publication number: 20070262497
    Abstract: A method for manufacturing a honeycomb structured body including molding ceramic raw material to form a pillar-shaped honeycomb molded body having a multiplicity of cells disposed in parallel with one another in the longitudinal direction with a cell wall therebetween, and filling in either one of the end portions of each of the cells with a plug material paste, and firing the honeycomb molded body to manufacture a honeycomb structured body comprising a honeycomb fired body, wherein after having filled in either one of the end portions of each of the cells of the honeycomb molded body with the plug material paste, a plug material paste drying process to dry the plug material paste is conducted by blowing hot air to an end face of the honeycomb molded body using a hot air drying apparatus.
    Type: Application
    Filed: April 2, 2007
    Publication date: November 15, 2007
    Applicant: IBIDEN CO., LTD.
    Inventors: Norihiko Yamamura, Syuhei Hayakawa, Yoshiteru Ohira
  • Publication number: 20070262498
    Abstract: A manufacturing method of a honeycomb structured body including a honeycomb fired body of the present invention comprises: fabricating a pillar-shaped honeycomb molded body having a large number of cells longitudinally placed in parallel with one another with a cell wall there between by molding a ceramic raw material, and firing of the honeycomb molded body, wherein the manufacturing method further includes removing of extraneous matters adhered to a surface of the honeycomb fired body after the honeycomb molded body has been fired.
    Type: Application
    Filed: February 9, 2007
    Publication date: November 15, 2007
    Inventors: Takamitsu Saijo, Kenichiro Kasai, Koji Higuchi