Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced or eliminated oxide layer beneath the high-k gate dielectric layer. A spacer adjacent a gate stack may act as an oxygen barrier to prevent the oxide from forming.

Abstract: A MEMS includes a first fixed end, a second fixed end, a first electrode, and an actuator element. The first electrode interposes between the first fixed end and the second fixed end. The first electrode is movable by the actuator element. A shape from the first electrode to the first fixed end and a shape from the first electrode to the second fixed end are asymmetrical.

Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.

Abstract: Embodiments of the invention provide an inductor integrated on a microelectronic die. The inductor may include upper and lower layers of magnetic material above and below an electrically conductive coil. There may be a magnetic via between the upper and lower layers of magnetic material. The magnetic via may comprise a material with a higher saturation flux density than the material of which the upper and lower layers of magnetic material are comprised.

Abstract: An object of the prevent invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc.

Abstract: An electron detector (30) for detection of electrons comprises a semiconductor wafer (11) having a central portion (12) with a thickness of at most 150 ?m, preferably at most 100 ?m, formed by etching an area of a thicker wafer. On opposite sides of the central portion (12) there are n-type and p-type contacts (16, 31). In operation, a reverse bias is applied across the contacts (16, 31) and electrons incident on the layer (15) of intrinsic semiconductor material between the contacts (16, 31) generate electron-hole pairs which accelerate towards the contacts (16, 31) where they may detected as a signal. Conductive terminals (24, 32) contact the contacts (16, 31) and are connected to a signal processing circuit in IC chips (28, 37) mounted to the semiconductor wafer (11) outside the active area of the detector (30). The contacts (16, 31) are shaped as arrays of strips extending orthogonally on the two sides of the intrinsic layer (15) to provide two-dimensional spatial resolution.

Abstract: A photo detector having an electrically conductive thin film and a light-receiving unit. A coupling periodic structure is provided on a surface of the film and converts incidence light to surface plasmon. The coupling periodic structure has an opening that penetrates the obverse and reverse surfaces of the thin film. The light-receiving unit is provided at one end of the opening in the surface that is opposite to the surface on which the coupling periodic structure is provided. The opening is shaped like a slit and is broader than half (½) the wavelength of the surface plasmon in a direction that intersects at right angles with a polarization direction of the incidence light and is narrower than half (½) the wavelength of the surface plasmon in a direction parallel to the polarization direction.

Abstract: A method of manufacturing a semiconductor device, the semiconductor device comprising: a semiconductor substrate; a pixel portion including an in-layer lens; and a peripheral circuit portion including a metal wiring portion, the pixel portion and the peripheral circuit portion being on the semiconductor substrate, the method comprising: forming an insulating film in the pixel portion and the peripheral circuit portion, so as to cover the metal wiring portion; providing, on the insulating film, a lens material layer for forming the in-layer lens; forming a resist layer for etching the lens material layer; curing the resist layer; and forming a first region and a second region in the resist layer, wherein a portion of the resist layer in the first region is thicker than that of the resist layer in the second region, the first region being in the peripheral circuit portion and the second region being in the pixel portion.

Abstract: Methods for making optically blind reference pixels and systems employing the same. The reference pixels may be configured to be identical to, or substantially identical to, the active detector elements of a focal plane array assembly. The reference pixels may be configured to use the same relatively longer thermal isolation legs as the active detector pixels of the focal plane, thus eliminating joule heating differences. An optically blocking structure may be placed in close proximity directly over the reference pixels.

Abstract: A thermistor device having a high-speed response to temperature and a large ON/OFF ratio at the operating temperature. The thermistor device comprises a first layer of a first material having a positive temperature coefficient of resistance and a second layer of a second material having a semiconductivity and formed directly on the first layer. As the first material changes from conductive to a semiconductive or an insulative at or near the transition temperature TM-I, the interface between the first and second layer changes to a pn junction.

Abstract: A lead frame includes: a die pad for holding a semiconductor chip; a radiator plate extending outward from one side face of the die pad and another side face thereof opposite the one side; a plurality of inner leads arranged opposite respective sides of the die pad other than the sides from which the radiator plate extends so as to interpose the die pad; and a plurality of outer leads formed outside the plurality of inner leads and connected to the inner leads. At least one of the plurality of inner leads serves as a ground lead connected to the die pad. In the radiator plate, an island bonding area of which potential is equal to that of the die pad is formed, a first slit is formed around three sides of the island bonding area, and the other side is connected to the radiator plate through a joint part.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and filling the trench, a first semiconductor region of a second conductivity type provided between the trenches, a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region, a mesa of the semiconductor layer provided between the trenches of a Schottky barrier diode region adjacent to a transistor region including the first semiconductor region and the second semiconductor region, a control electrode connected to the conductive material filling the trench of the transistor region and a main electrode provided in contact with a surface of the first semiconductor region, the second semiconductor region, a surface of the mesa and a part of the condu

Abstract: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to the base substrate layer, filling the trench and contact hole with undoped intrinsic polysilicon and then performing a doping process in respect of the polysilicon material filling the contact hole so as to form in situ a highly doped contact post while the material filling the isolation trench remains non-conductive. The isolation trench and contact post are formed substantially simultaneously so as to avoid undue interference with the device fabrication process.

Abstract: A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

Abstract: An E-fuse and a method for fabricating an E-fuse are provided integrating polysilicon resistor masks. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Abstract: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline film or a laminate of these films formed on a polycrystalline film.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

Abstract: A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.

Abstract: By performing plasma etching on the second surface of a semiconductor wafer on the first surface of which an insulating film is placed in dividing regions and on the second surface of which a mask for defining the dividing regions are placed, the second surface being located opposite from the first surface, the insulating film is exposed from an etching bottom portion by removing portions that correspond to the dividing regions. Subsequently, by continuously performing the plasma etching in the state in which the exposed insulating film is surface charged with electric charge due to ions in the plasma, corner portions put in contact with the insulating film are removed in the device-formation-regions. Consequently, individualized semiconductor chips having a high transverse rupture strength are manufactured.

Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.

Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.

Abstract: A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and conductive material at both the active surface and the thinned back side. A metal layer having a glass transition temperature greater than that of the solder may be plated to form a dam structure covering one or both ends of the TWI. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

Abstract: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.

Abstract: A semiconductor housing having a coupling coating is disclosed. In one embodiment, the semiconductor housing includes a leadframe for equipping with a semiconductor chip and for enveloping with a polymer material, to which a polymer layer has been applied. The polymer layer has end groups which possess particularly good adhesion to the polymer material or the surface of the flat conductor.

Abstract: A semiconductor device includes a semiconductor element; a board where the semiconductor element is mounted; a heat radiation member thermally connected to the semiconductor element and fixed to the board; and a plurality of outside connection terminals provided on a surface opposite to a surface where the heat radiation member is provided of the board; wherein a fixing position where the heat radiation member is fixed to the board is substantially positioned on an inscribing circle; and the center of the inscribing circle is a center position of the board and the inscribing circle inscribes the heat radiation member.

Abstract: A method for providing improved gettering in a vacuum encapsulated device is described The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of the getter material, thereby increasing the volume of gas that the getter material can absorb. This may improve the vacuum maintained within the vacuum cavity over the lifetime of the vacuum encapsulated device.

Abstract: A stacked module employs flexible circuitry to connect CSP integrated circuits. A flexible circuit with obverse and reverse sides is disposed between two CSPs oriented face-to-face with the flex circuit between to form a precursor assembly. One or more flaps or extension parts of the flex circuitry extend from the perimeter of the facing CSPs. Contacts to connect the CSPs to an operating environment are disposed along the one or more flex circuitry flaps or extensions. In a preferred embodiment, the CSP and flex circuit precursor assembly is disposed in a frame and the one or more flex circuitry flaps or extensions that extend out from beyond the perimeter of the CSP devices are disposed on the form or frame. The module contacts disposed on the flex circuitry extension(s) are positioned along the bottom edge of the form or frame for deployment of the stacked module in an operating environment.

Abstract: An electric component includes a substrate having a first surface and a second surface opposite to the first surface; a first conductive layer formed on the first surface; a second conductive layer formed on the second surface; an electrode formed on the first conductive layer; a resin portion formed on the first conductive layer such that a part of the electrode is exposed; and an external terminal electrically connected to the part of the electrode.

Abstract: The semiconductor device which can be contributed to the miniaturization of a module substrate is offered regarding the point of the interconnection between the electrode pads which may be directly connected on a function. The first semiconductor chip and the second semiconductor chip which did the stack are mounted on the module substrate concerned deflecting a centre position mutually between module substrates to right and left. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is shorter, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip corresponding to mutual are directly connected with a wire.

Abstract: The invention relates to a semiconductor device comprising semiconductor device components embedded in plastic housing composition. The semiconductor device components partly contain copper or have copper-containing coatings and/or coating structures. The copper-containing regions of the semiconductor device components have an adhesion promoting layer with copper(II)oxide whiskers on the surfaces that are in contact with the plastic housing composition.

Abstract: A semiconductor component including: a substrate, at least one semiconductor chip arranged on the substrate and at least one passive device likewise arranged on the substrate. The passive device is mounted with its underside on the substrate. The semiconductor component further includes an interspace disposed between the underside of the passive device and the substrate. The interspace is filled with an underfilling material. In order to avoid the solder pumping effect, the upper side and the lateral sides of the passive device are also embedded in a plastic compound.

Abstract: An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes lie along the cut line between adjacent packages so that, upon singulation, the filled through holes are cut and a portion of the filled through-holes are exposed at the side edges of the singulated packages. These exposed portions of the filled through-holes form vertical surface mount technology (SMT) pads. After the semiconductor packages are singulated and the SMT pads are defined in the side edges, SMT is used to solder the SMT pads of a first semiconductor package to the respective SMT pads of a second semiconductor package to structurally and electrically couple the two packages together side-by-side.

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies.

Abstract: The semiconductor device of the invention has a motherboard 3, a lower package 2 mounted on the motherboard 3, and an upper package 1 mounted on the lower package 2 via intermediate terminals 11. Edge portions, in a marginal area of the lower package 2, with which the intermediate terminals 11 overlap are in contact with the motherboard 3.

Abstract: In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is coupled to the package via the first pin and the second pin. The substrate includes a plurality of power domains and a power control unit. The second pin of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first pin of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

Abstract: An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

Abstract: A sealing structure having a sealing space provided by bonding a substrate and an intermediate member with a first bonding part and by bonding the intermediate member and a cap with a second bonding part. The intermediate member has a higher thermal conductivity than the substrate and the cap.

Abstract: A heat sink structure for embedding chips and a method for fabricating the same are proposed. An external metal layer is formed on the surface of a chip with pads and a wafer backside heat conductive layer is formed on the inactive surface of the chip. At least one chip is embedded into one cavity of a circuit board. The circuit board integrated with at lease one chip is formed with a circuit layer and a heat dissipating layer. The circuit layer is connected to the external metal layer and the heat dissipating layer is connected to the wafer backside heat conductive layer of at least one chip, so as to electrically connect to the chip embedded into the circuit board. Thus, the chip is electrically connected to outer circuit and the heat generated during operation of the chip is conducted to exit.

Abstract: A packaged electronic component includes a body, a plurality of magnetic elements and a silicon material, wherein the magnetic elements are disposed in the body, and the silicon material covers the surfaces of the magnetic elements. At least one side of the body has a hole to dissipate heat, and provides additional space to contain expanded silicon material after heating.

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract: A semiconductor device, a chip structure thereof, and a method for fabricating the same are proposed. The method involves cutting a wafer with an array of chips twice so as to separate the chips and to form a chip structure. The first cutting is wider than the second cutting, and both are performed on an inactive surface of each of the chips. The chip structure includes a protruding portion formed on the inactive surface. The chip structure is electrically connected to a substrate by conductive bumps in a flip-chip manner and mounted with a heat sink. A decrease in contact area between the chip and the heat sink reduces warpage caused to the semiconductor device by thermal stress, thus preventing delamination of the heat sink and cracking of the conductive bumps, and reducing the expense and time spent on finding suitable underfill materials.

Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.

Abstract: A method for manufacturing a stacked bump structure including the following steps is provided. First, a substrate having multiple bonding pads disposed on a surface thereof is provided. Next, a first bump and a second bump are respectively formed on any two adjacent bonding pads of the substrate. Then, a third bump is formed between the first bump and the second bump by wire bonding technology, so as to make the two adjacent bonding pads electrically connected to each other through the third bump.

Abstract: A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.

Abstract: A semiconductor device capable of suppressing diffusion of noise signals is provided. The semiconductor device has a BGA (Ball Grid Array) structure in which a plurality of electrode terminals to do input and/or output of signals from and to the outside is arranged in a matrix form. The semiconductor device includes a noise source electrode terminal to do input and/or output of signals, and low-impedance electrode terminals. The noise source electrode terminal does input and/or output of signals acting as a source of noises. The low-impedance electrode terminal are arranged so as to be adjacent to the noise source electrode terminal in a vertical or horizontal direction. The low-impedance electrode terminal is arranged so as to be adjacent to the noise source electrode terminal in a slanting direction.