Abstract: A fuse structure includes an insulating structure, a fuse pattern, an insulating pattern and an insulating layer. The insulating structure has a fuse region and a wire region proximate the fuse region. The fuse pattern is on the fuse region. The insulating pattern has a first portion and a second portion. The first portion is located on the fuse region and covers a sidewall of the fuse pattern. The second portion is located on the wire region. The insulating layer is on the insulating pattern and the fuse pattern and has a height selected to limit spread of fractures of the fuse pattern generated by cutting of the fuse pattern.

Abstract: In one embodiment, a well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.

Abstract: In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.

Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality modified region 71 is formed at a position where the distance between the front face 3 of the substrate 4 and the end part of the quality modified region 71 on the front face side is 5 ?m to 15 ?m. When the quality modified region 71 is formed at such a position, a laminate part 16 (constituted by interlayer insulating films 17a, 17b here) formed on the front face 3 of the substrate 4 is also cut along a line to cut with a high precision together with the substrate 4.

Abstract: Herein disclosed a semiconductor device in which a semiconductor chip is mounted over a substrate, the device including a plurality of through-interconnects configured to be formed inside each of through-holes that penetrate the substrate and be led from the semiconductor chip to a face of the substrate on an opposite side of the semiconductor chip.

Abstract: A multi-chip stacked package is revealed, primarily comprising a spacer pad and a plurality of leads of a lead frame, a first chip, a second chip, and an encapsulant. A plurality of first electrodes are formed on the active surface of the first chip below the spacer pad and are electrically connected to one surfaces of the leads. A plurality of second electrodes are formed on the active surface of the second chip above the spacer pad and are electrically connected to the same surfaces of the leads. The encapsulant encapsulates the spacer pad, parts of the leads, the first chip, and the second chip where the active surface of the first chip is attached to the bottom surface of the spacer pad and the back surface of the second chip to the top surface of the spacer pad. Moreover, the spacer pad does not cover the first electrodes of the first chip for wire-bonding to achieve multi-chip stacking with a reduced overall package thickness.

Abstract: In a liquid crystal driver package (1a) of one embodiment of the present invention, a film base member (2) is connected to a liquid crystal driver (3) through an interposer substrate (4a). Film base member connecting terminals (13) of the interposer substrate (4a) are connected to terminals of on-film wires (5 and 6) of the film base member (2) with an anisotropic conductive adhesive. An insulating film (7) is formed at an edge section of the interposer substrate (4a) and a periphery section of the edge section. This arrangement prevents the on-film wires (5 and 6) from coming into direct contact with the interposer substrate (4a). Therefore, it becomes possible to provide an IC chip (liquid crystal driver) package in which short circuit does not occur between the on-film wires adjacent to each other.

Abstract: A semiconductor device (10) comprises a die (11) provided between a first leadframe (12) and a second leadframe (13), such that a first surface of the die (11) is connected to the first leadframe (12) and a second surface of the die (11) is connected to a second leadframe (13). Mold compound (15) includes side recesses (16) into which end portions (18) of leadframe (12) can be fit.

Abstract: A high power shunt switch comprises a leadframe including a paddle for supporting a shunt element, and a plurality of bond pads located around a periphery of the paddle, wherein at least a first subset of the bond pads are aligned in a substantially straight-line configuration. A shunt element is fixedly attached to the paddle and wire bonded to a top surface of one the bond pads. An encapsulant is disposed on the paddle, the shunt element, the plurality of bond pads, and the wire bond, thereby forming an encapsulated package structure. The package structure is positioned and attached to a transmission line such that the bottom surfaces of each of the at least first subset of bond pads are in simultaneous contact with the transmission line. The package structure and the transmission line are fixedly attached to a suitable substrate.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.

Abstract: In a semiconductor apparatus, a semiconductor element is mounted on a wiring substrate. Wiring patterns and protrusions are formed on a surface of a substrate with the wiring patterns extending on tops of the protrusions. The surface of the substrate on which the wiring patterns are formed are covered with an insulating layer. Surfaces of connection parts of the wiring patterns formed on the tops of the protrusions are formed with the surfaces of the connection parts exposed to a surface of the insulating layer on a level with the surface of the insulating layer or in a position lower than the surface of the insulating layer. The connection parts are formed as pads for connection formed in alignment with connection electrodes of the semiconductor element. The semiconductor element is mounted by making electrical connection to the connection parts by flip chip bonding.

Abstract: A light emitting diode (LED) module includes a circuit substrate and a plurality of LED dies. The circuit substrate sequentially includes a metal layer, a first dielectric layer and an interconnection layer. The first dielectric layer has a plurality of openings. The LED dies are respectively disposed in the openings and electrically connected with the interconnection layer.

Abstract: A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

Abstract: A method for hermetically sealing a package includes applying a light or energy active resist to a fill port to act as a temporary hermetic seal, patterning the resist, and applying a solder to the fill port, wherein the solder is configured to serve as a hermetic seal.

Abstract: The heat dissipation characteristics of a semiconductor device having a flip-chip mounted semiconductor chip are improved at low costs. The semiconductor device includes: a substrate; the semiconductor chip which is flip-chip mounted on the substrate with the front surface of the chip facing downward; a sealing resin layer which is molded around the semiconductor chip; a phase change portion which is provided on the rear surface of the semiconductor chip so as to be capable of being thermally connected to a heat dissipation member such as a heat sink or a heat pipe. The phase change portion is melted by the operating heat of the semiconductor chip. Therefore, the intimate characteristics between the semiconductor chip and the heat dissipation member are improved, and the heat dissipation characteristics of the semiconductor chip are improved.

Abstract: A wire bond free power module assembly consists of a plurality of individual thin packages each consisting of two DBC wafers which sandwich one or more semiconductor die. The die electrodes and terminals extend through one insulation covered end of the wafer sandwich and the outer sides of the sandwiches are the outer copper plates of the DBC wafers which are in good thermal communication with the semiconductor die but are electrically insulated therefrom. The plural packages may be connected in parallel by lead frames on the terminals and the packages are stacked with a space between them to expose both sides of all packages to a cooling medium, either the fingers of a conductive comb or a fluid heat exchange medium.

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.

Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.

Abstract: A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

Abstract: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position.

Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. -The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.

Abstract: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.

Abstract: Chip and wire and flip chip compatible die stack capacitors (“stack caps”), die stack assemblies and die stack assembly methods are disclosed. Each stack cap includes a plurality of multilayer sections. Each multilayer section is fabricated separately, and the sections are then bonded or integrated together. As illustrative examples, stack cap formats with peripheral ring wire bond terminals or interfacial attach pad terminals along with their associated die stack assemblies and assembly methods are disclosed. Each stack cap is attached directly to the IC die that it bypasses. The respective peripheral power, ground and signal bond pads of each bonded stack cap and die pair and the host substrate are connected with bond wires.

Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

Abstract: An on-die termination method to support a multi-chip package routing topology is described. The on die termination method may increase the surface area on the substrate such that larger size die or more memory may be mounted thereto. The on-die termination method may include a semiconductor package that features on die termination bumps coupled to a semiconductor die's bus terminals, which couples the semiconductor die to an on-die termination pin coupled in the motherboard. An alternative on-die termination method includes a semiconductor die, within the multi-chip CPU package, designated as an end agent from which a single on die termination bump is coupled to an on-die termination pin.

Abstract: In a printed circuit board, a semiconductor including plural power supply terminals and a semiconductor chip is mounted onto a mounting surface of a printed wiring board, and a bypass capacitor for reducting a power ground noise is provided. Another bypass capacitor, which is connected to the bypass capacitor only within an IC chip is provided to inhibit the power ground noise from causing not only a variation in timing of the IC chip and a malfunction thereof but also a malfunction of another IC chip and the generation of an EMI noise in a case where the power ground noise propagates to a power supply side.

Abstract: A surface mounting structure and a packaging method thereof comprises a chip, a first conducting wire and a second conducting wire. The two conducting wires instead of lead frame architecture of the prior art is that the lead frame and a bridge jumper connected with N junction and P junction instead of the two conducting wires. The two conducting wires are drawn out from a bottom of a package, and are pressed and bent to original surface of the surface mounting pins so as to increase space utilization rate. Thereby it is to improve a complicated lead frame architecture of the prior art, increase use space and simplify system design.

Abstract: An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The semiconductor layers define cavities therebetween in which circuit components are fabricated. A sealing ring seals the semiconductor layers together so as to hermetically seal the circuit components within the cavities.

Abstract: The deterioration of dielectric breakdown strength arising from an opening of a metal plate is prevented and the reliability as a circuit board is enhanced. A circuit board is provided with a metal plate, having openings, as core material. The opening is provided in a manner that the size of the opening gradually increases from a lower surface side toward an upper surface side of the metal plate. On both surface sides of the metal plate there are provided wiring patterns, respectively, via insulating layers. The insulating layer provided on an upper region of the opening and the corresponding wiring pattern are provided such that they have a recess on the upper surface of them. To electrically connect each wiring pattern, the circuit board further includes a conductor which penetrates the metal plate via the opening and which connects the wiring patterns with each other. An LSI chip is directly coupled to the upper surface side of the metal plate via a solder ball.

Abstract: A light emitting diode (LED) module includes a metal circuit substrate and a plurality of LED dies. The metal circuit substrate sequentially includes a metal board, a first dielectric layer and an interconnection layer. The first dielectric layer has a plurality of openings. The LED dies are respectively disposed in the openings and electrically connected with the interconnection layer.

Abstract: In a semiconductor device 100, a light emitting element 120 has been mounted on an upper plane of a semiconductor substrate 102. In an impurity diffusion region of the semiconductor substrate 102, a P conducting type of a layer 104, and an N layer 106 have been formed, while an N conducting type impurity is implanted to the P layer 104, and then the implanted impurity is diffused to constitute the N layer 106. A zener diode 108 made of a semiconductor device has been formed by the P layer 104 and the N layer 106.

Abstract: An integrated heat sink comprises a plurality of heat sink portions. The integrated heat sink provides efficient transfer of heat from a non-planar surface. In an example configuration two heat sinks are integrated to provide a thermal solution for dual bare die silicon circuits on a common substrate. One of the heat sinks in the integrated heat sink is compressively coupled to an integrated circuit via an integral spring assembly. The spring assembly pushes one of the heat sinks against one of the integrated circuits while allowing the other heat sink to remain positioned against the other integrated circuit. The integrated heat sink compensates for variations in circuit height. The integrated heat sink obviates the need for independent heat sinks for transferring heat from a non-planar surface.

Abstract: A system and method of cooling a CCD camera may employ a composite material housing design that allows the cold side of a TEC to be mounted relatively close to the CCD and the hot side of the TEC to be isolated from the housing cavity in which the CCD resides. An efficient heat transfer path may facilitate cooling the CCD to a predetermined or selected operating temperature and isolate the CCD from the heat loads generated by operation the TEC.

Abstract: A stacking structure of chip package disclosed herein includes a lead frame having a plurality of supporting fingers and a plurality of leads; a first chip arranged on one side of the lead frame by utilizing a first connecting element so as to partially cover these supporting fingers, wherein the supporting fingers stretch from the edge of the first chip toward the first chip to provide a support; a second chip arranged on the opposite side of the lead frame at the corresponding position of the first chip by utilizing a second connecting element to partially covering the supporting fingers, wherein the first chip, the second chip and the partially-covered supporting fingers are cooperated to define an open mold-flowing trench; an electrical-connecting element to electrically connect the first chip, the second chip and the leads; and a molding compound utilized to cover the first chip, the second chip, the electrical-connecting element and some of the lead frame, wherein the molding compound flows through the

Abstract: In some embodiments, a system includes a circuit board, a first chip, and a second chip stacked on the first chip. The first chip is coupled between the circuit board and the second chip, and the first chip includes circuitry to repeats commands the first chip receives to the second chip. Other embodiments are described.

Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.

Abstract: An example of a high-frequency semiconductor device includes two unit semiconductor devices. Each of the two unit semiconductor devices has a ground substrate, a high-frequency semiconductor element, an input-side matching circuit, an output-side matching circuit, a side wall member, an input terminal, and an output terminal. The ground substrate has heat-radiating property. The high-frequency semiconductor element is provided on the ground substrate. The input-side matching circuit is connected to the high-frequency semiconductor element. The output-side matching circuit is connected to the high-frequency semiconductor element. The side wall member surrounds at least the high-frequency semiconductor element. The input terminal is connected to the input-side matching circuit. The output terminal is connected to the output-side matching circuit. The two unit semiconductor devices are coupled to each other at upper edges of the side wall members.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.

Abstract: A chip module assembly includes a CO2 getter exposed through a gas-permeable membrane to a chip cavity of a chip module. One or more chips is/are enclosed within the cavity. The CO2 getter comprises a liquid composition including 1,8-diaza-bicyclo-[5,4,0]-undec-7-ene (DBU) in a solvent that includes an alcohol, preferably, 1-hexanol. In one embodiment, a sheet of gas-permeable membrane is heat-welded to form a pillow-shaped bag in which the liquid composition is sealed. The pillow-shaped bag containing the liquid composition is preferably disposed in a recess of a heat sink and exposed to the cavity through a passage between the recess and the cavity. The CO2 getter can remove a relatively large amount of carbon dioxide from the cavity, and thus effectively prevents solder joint corrosion. For example, based on the formula weights and densities of the DBU and 1-hexanol, 200 g of the liquid composition can remove over 34 g of carbon dioxide.

Abstract: A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.

Abstract: A chip structure including a chip, at least an arrangement of side pads and multiple bumps is provided. The chip has an active surface, and the arrangement of side pads is disposed on the active surface and close to a side of the active surface. The arrangement of side pads includes multiple pads arranged along the extending direction of the side, and the bumps are disposed on the pads. Each bump has a first portion and a second portion, wherein the second portion is connected to the first portion along an axis perpendicular to the extending direction of the side. In addition, the width of the first portion in the extending direction of the side is larger than that of the second portion in the extending direction of the side. The second portion of the bump is located between the first portions of two bumps adjacent to the bump.

Abstract: A semiconductor package having a good joint to an external board, providing easy measurement control of the electrical characteristics of a semiconductor chip, and ensuring a sufficient number of input and output terminals, and a method of mounting the same are provided. The semiconductor package comprises a plurality of connection terminals aligned individually, and a plurality of conductive wires spaced from the connection terminals. The connection terminals and the wires are bonded to one side of a body, and an interconnection connecting at least one pair of the connection terminal and the wire is formed in the body.

Abstract: The first external electrode has a main body portion a part of which is buried in a side wall of a case and joining portions protruding from an end of the main body portion toward the inside of the case. Each joining portion of the first external electrode is formed to have a thickness smaller than that of the main body portion, and an end portion of each joining portion is directly joined onto a wiring pattern of the insulating substrate through ultrasonic joining. Therefore, a load and ultrasonic vibration necessary for joining the joining portion onto the wiring pattern can be suppressed, which makes it possible to directly join the first external electrode onto the wiring pattern of the insulating substrate without damaging an insulating member of the insulating substrate.

Abstract: Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external connection electrode, the electronic component including a recess or/and a projection configured to be provided under the barrier metal layer outside or/and inside the opening, the underlying metal layer being formed on the recess or/and the projection and having a surface shape that follows the recess or/and the projection.

Abstract: The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. One aspect of present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a circuit pattern including bonding pads on one side of a first insulation layer, laminating a second insulation layer onto one side of the first insulation layer, and exposing the bonding pads by removing a part of the first insulation layer and the second insulation layer corresponding to the location in which the bonding pads is formed.

Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.