Patents Issued in December 20, 2007
  • Publication number: 20070290246
    Abstract: To fabricate an active matrix type display device integrated with an image sensor at a low cost and without complicating process, an image sensor laminated with TFT and a light receiving unit is formed on a light receiving matrix, a display matrix is arranged with TFT and pixel electrodes on a matrix and formed with an electrode layer functioning as a black matrix, a lower electrode of the light receiving unit is formed by a starting film the same as that of the black matrix, a terminal for fixing potential of an upper electrode is formed by starting films the same as those of a signal line, the electrode layer or pixel electrodes and the terminals function also as shield electrodes for a side face of the light receiving unit since potential thereof is fixed.
    Type: Application
    Filed: August 14, 2007
    Publication date: December 20, 2007
    Inventors: Hongyong Zhang, Masayuki Sakakura, Yurika Satou
  • Publication number: 20070290247
    Abstract: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration in the gate insulation film formed by the plasma nitridation is 5 to 20% in atomic percentage. Even without subsequent annealing, it is possible to effectively prevent a boron penetration phenomenon in the DRAM and to reduce traps in the film causing deterioration in driving capability of the device.
    Type: Application
    Filed: October 27, 2005
    Publication date: December 20, 2007
    Inventors: Tatsuo Nishita, Shuuichi Ishizuka, Yutaka Fujino, Toshio Nakanishi, Yoshihiro Sato
  • Publication number: 20070290248
    Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 20, 2007
    Inventor: Rolf Weis
  • Publication number: 20070290249
    Abstract: An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.
    Type: Application
    Filed: August 24, 2007
    Publication date: December 20, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Martin Popp, Frank Jakubowski, Juergen Holz, Lars Heineck
  • Publication number: 20070290250
    Abstract: Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
    Type: Application
    Filed: August 28, 2007
    Publication date: December 20, 2007
    Inventors: William Clark, Edward Nowak
  • Publication number: 20070290251
    Abstract: A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Applicant: Macronix International Co., Ltd.
    Inventor: Chao-I Wu
  • Publication number: 20070290252
    Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.
    Type: Application
    Filed: May 7, 2007
    Publication date: December 20, 2007
    Inventors: Jeoung-Mo Koo, Hee-Seon Oh
  • Publication number: 20070290253
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.
    Type: Application
    Filed: June 20, 2007
    Publication date: December 20, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaru KITO, Nobutoshi Aoki, Masaru Kidoh, Ryota Katsumata, Masaki Kondo, Naoki Kusunoki, Toshiyuki Enda, Sanae Ito, Hiroyoshi Tanimoto, Hideaki Aochi, Akihiro Nitayama, Riichiro Shirota
  • Publication number: 20070290254
    Abstract: In order to link a defect inspection process before forming contact holes with an exposure process for forming the contact holes, a position (physical coordinates) of a defect on a wafer is stored, the defect having been detected in the defect inspection process before forming the contact holes, an exposure (dummy exposure) is performed under the condition that no contact hole is formed on the above-mentioned position. In this method, no contact hole is formed in the region having the defect therein, the cell is considered as a defective one, yet a word line (control gate) and a bit line are not short-circuited through the contact hole, and makes it possible to avoid the short-circuiting by only applying a redundancy to the bit line as conventionally employed.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 20, 2007
    Inventor: Reiji Makara
  • Publication number: 20070290255
    Abstract: A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.
    Type: Application
    Filed: August 23, 2007
    Publication date: December 20, 2007
    Inventors: Mark Helm, Roger Lindsay
  • Publication number: 20070290256
    Abstract: An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency. The memory cell can comprise a dual gate structure, such that the cell is a 2-bit cell.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Applicant: Macronix International Co., Ltd.
    Inventor: Ming-Chang Kuo
  • Publication number: 20070290257
    Abstract: A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween, wherein the shield electrode and the gate electrode are electrically connected together.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 20, 2007
    Inventors: Nathan Kraft, Christopher Boguslaw Kocon, Paul Thorup
  • Publication number: 20070290258
    Abstract: Field effect transistors include a substrate and a pillar that extends away from the substrate. The pillar includes a base adjacent the substrate, a top remote from the substrate, and a sidewall that extends between the base and the top. An insulated gate is provided on the sidewall. A first source/drain region is provided in the substrate beneath the pillar and adjacent the insulated gate. A second source/drain region that is heavily doped compared to the first source/drain region, is provided in the substrate beneath the pillar and remote from the insulated gate. The pillar may be an I-shaped pillar that is narrower between the base and the top compared to adjacent the base and the top, such that the sidewall includes a recessed portion between the base and the top.
    Type: Application
    Filed: September 11, 2006
    Publication date: December 20, 2007
    Inventors: Youngwoong Son, Jae-Man Yoon, Bong-soo Kim, Hyeoungwon Seo
  • Publication number: 20070290259
    Abstract: A process for manufacturing a semiconductor device consecutively includes forming a recess in the surface region of a silicon substrate, forming a gate insulation film on the surface of the recess, depositing a silicon electrode film including an oxygen-mixed layer extending parallel to the surface of the recess, injecting impurities into silicon the electrode film 17, and heat-treating the silicon electrode film to diffuse impurities.
    Type: Application
    Filed: June 19, 2007
    Publication date: December 20, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kanta SAINO
  • Publication number: 20070290260
    Abstract: A Trench MOSFET of an embodiment of the present invention includes: a semiconductor substrate including a substrate, an epitaxial layer, a body region, and a highly doped source region. The substrate, the epitaxial layer, the body region, and the highly doped source region are adjacently formed in this order. A trench region is formed in the semiconductor substrate in such a manner that the bottom of the trench region reaches the epitaxial layer. A gate insulator is formed on a bottom surface and a sidewall of the trench region. A gate electrode is provided within the trench region. The gate insulator includes an electric-field reducer thicker than a thickness of the gate insulator provided between the gate electrode and the body region. Thus, voltage-resistance improves in the vicinity of the bottom of the trench. This allows increase of breakdown voltage. Therefore, a Trench MOSFET with higher breakdown voltage is realized.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 20, 2007
    Inventor: Alberto Adan
  • Publication number: 20070290261
    Abstract: The present invention provides a self-driven LDMOS, which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal will be clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS will be turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention doesn't lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential doesn't vary in response to an increment of the drain-voltage potential.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 20, 2007
    Applicant: SYSTEM GENERAL CORP.
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang
  • Publication number: 20070290262
    Abstract: A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate is operatively coupled to the source region and is located offset from the drain region on a side of the source region opposite from the drain region. When the device is in an on state, current tends to flow deeper into the drift region to the offset gate, rather than near the device surface. The drift region preferably includes at least first and second stacked JFETs.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventor: Jun Cai
  • Publication number: 20070290263
    Abstract: It is made possible to obtain epitaxially grown layers with excellent crystallinity. A semiconductor device includes: a semiconductor layer having crystallinity; a first insulating film formed on the semiconductor layer and having a first opening to reach the semiconductor layer; a first epitaxially grown layer formed on the first insulating film so as to embed the first opening; a second insulating film formed on the first epitaxially grown layer and having a second opening to reach the first epitaxially grown layer; and a second epitaxially grown layer formed on the second insulating film so as to embed the second opening.
    Type: Application
    Filed: March 7, 2007
    Publication date: December 20, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiki KAMATA
  • Publication number: 20070290264
    Abstract: The invention aims at increasing an effect of a strain applying technique for enhancing transistor performance in a fully depleted silicon-on-insulator (FDSOI) type transistor having a thin buried oxide (BOX) film. In an FDSOI type transistor having a very thin SOI structure (6), a stress generating region is formed on a back face side (5) of a very thin BOX layer (4) in order to apply strains to portions in which channels are intended to be formed. Desired portions on a back face side of the BOX layer (4) are amorphized by performing ion implantation, and are then recrystallized by performing a heat treatment in a state where a stress applying film (3) is formed, thereby transferring stresses from the stress applying film (3) to the portions in which the channels are intended to be formed. Thus, the stress generating region is formed.
    Type: Application
    Filed: February 13, 2007
    Publication date: December 20, 2007
    Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Yusuke Morita
  • Publication number: 20070290265
    Abstract: An epitaxial device module monolithically integrated with a CMOS structure in a bulk or thick-film SOI substrate, comprising an active area on which epitaxial layers are formed by selective or non-selective epitaxial growth and a separate active area in which the CMOS structure is formed. A hard mask for epitaxy having an opening therein provides self-alignment for optional ion implants into the substrate. The ion-implanted region overlaps the active region underneath the epitaxial layer, a portion of the source/drain region of the CMOS structure and the isolation region separating the two active areas, thereby establishing a conductive path underneath the isolation region between the two active areas.
    Type: Application
    Filed: July 23, 2007
    Publication date: December 20, 2007
    Inventors: Carlos Augusto, Lynn Forester
  • Publication number: 20070290266
    Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.
    Type: Application
    Filed: June 26, 2007
    Publication date: December 20, 2007
    Inventors: Ming-Dou Ker, Che-Hao Chuang
  • Publication number: 20070290267
    Abstract: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 20, 2007
    Applicant: Fuji Electric Holdings Co., Ltd
    Inventors: Koh Yoshikawa, Setsuko Wakimoto, Hitoshi Kuribayashi
  • Publication number: 20070290268
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: August 9, 2007
    Publication date: December 20, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070290269
    Abstract: A device includes a substrate, a first gate, a second gate, and a third gate. The substrate has a first active region and a second active region. The first gate is configured in a first loop structure around the first active region. The second gate is configured in a second loop structure around the second active region, and the third gate is configured in a third loop structure around the first gate and the second gate.
    Type: Application
    Filed: August 17, 2007
    Publication date: December 20, 2007
    Inventors: Trudy Benjamin, James Axtell, Joseph Torgerson
  • Publication number: 20070290270
    Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
    Type: Application
    Filed: May 7, 2007
    Publication date: December 20, 2007
    Inventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
  • Publication number: 20070290271
    Abstract: The semiconductor device whose yield and reliability improved, and its manufacturing method are offered. A resist layer is formed so that the silicon nitride film and filling insulating film in region A may be covered. Then, in order to adjust the height position of the upper surface of a filling insulating film, a plasma etch back or fluoric acid is performed. Thereby, the filling insulating film on the silicon nitride film in region B is removed. Therefore, the problem that the residue of a filling insulating film remains on the silicon nitride film in region B is solved.
    Type: Application
    Filed: June 14, 2007
    Publication date: December 20, 2007
    Inventor: Yoshihiko Kusakabe
  • Publication number: 20070290272
    Abstract: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
    Type: Application
    Filed: August 29, 2007
    Publication date: December 20, 2007
    Inventors: Eric Coker, Douglas Coolbaugh, Ebenezer Eshun, Zhong-Xiang He, Matthew Moon, Anthony Stamper
  • Publication number: 20070290273
    Abstract: An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by ?FN tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.
    Type: Application
    Filed: October 30, 2006
    Publication date: December 20, 2007
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: HANG-TING LUE, ERH-KUN LAI, SZU-YU WANG
  • Publication number: 20070290274
    Abstract: A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction.
    Type: Application
    Filed: June 19, 2007
    Publication date: December 20, 2007
    Inventor: Toshitake YAEGASHI
  • Publication number: 20070290275
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: July 6, 2007
    Publication date: December 20, 2007
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20070290276
    Abstract: The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 20, 2007
    Applicant: SYSTEM GENERAL CORP.
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin
  • Publication number: 20070290277
    Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.
    Type: Application
    Filed: August 23, 2007
    Publication date: December 20, 2007
    Inventors: Sun-Jay Chang, Shien-Yang Wu
  • Publication number: 20070290278
    Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.
    Type: Application
    Filed: June 20, 2006
    Publication date: December 20, 2007
    Applicant: Agere Systems Incorporated
    Inventors: Taeho Kook, Tanya Nigam, Bonnie E. Weir
  • Publication number: 20070290279
    Abstract: A semiconductor device includes an interlayer insulating film, a first interconnect material, and a second interconnect material. The interlayer insulating film is formed on a semiconductor substrate including an effective chip. The first interconnect material is formed in an interconnect pattern in the interlayer insulating film. The interconnect pattern is made in a region above the effective chip. The second interconnect material is formed in a groove pattern in the interlayer insulating film. The groove pattern is made between the region above the effective chip and a region above an edge of the semiconductor substrate. The second interconnect material separates the interlayer insulating film into an inner circumferential portion which includes the region above the effective chip and an outer circumferential portion which does not include the region above the effective chip.
    Type: Application
    Filed: May 23, 2007
    Publication date: December 20, 2007
    Inventor: Kentaro Imamizu
  • Publication number: 20070290280
    Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.
    Type: Application
    Filed: August 27, 2007
    Publication date: December 20, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Shin KWON, Joon-Yong JOO, Kwang-Ok KOH, Sung-Bong KIM
  • Publication number: 20070290281
    Abstract: Disclosed is an activation device for use in initiating an event. This activation device includes an activation member with a body having a front surface and a rear surface. The illumination member is positioned substantially adjacent, spaced from or near to the rear surface of the body of the activation member. The illumination member projects physical waves toward the rear surface of the body of the activation member. A method of manufacturing an activation device is also disclosed.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 20, 2007
    Applicant: Bea, Inc.
    Inventors: Thomas P. Schluep, Michael F. Stadler, Zachary T. Casella
  • Publication number: 20070290282
    Abstract: An embodiment of a micro-mover in accordance with the present invention can include a movable plate hermetically sealed between a top cap wafer and a bottom cap wafer. A magnet disposed on one or both of the cap wafers. The movable plate can include current paths disposed within a magnetic field generated by the magnet, and coaxially with a surface of the movable plate. When current is applied to the current paths, the movable plate is urged some distance within a gap between the movable plate and a stationary portion disposed co-planar with the movable plate.
    Type: Application
    Filed: October 26, 2006
    Publication date: December 20, 2007
    Applicant: NANOCHIP, INC.
    Inventors: Nickolai Belov, Peter David Ascanio, Donald Edward Adams
  • Publication number: 20070290283
    Abstract: A solar cell and a manufacturing method thereof. A method of manufacturing a solar cell includes: forming an emitter layer on a first surface of a semiconductor substrate; forming an insulation layer on the emitter layer; applying a chemical compound including a dopant having a conductive type of the emitter layer on the insulation layer according to a pattern; forming a high concentration emitter portion by removing a portion of the insulation layer corresponding to a positioning of the chemical compound and diffusing the dopant toward the emitting layer; removing the chemical compound; and forming a first electrode electrically connected to the high concentration emitter portion.
    Type: Application
    Filed: December 28, 2006
    Publication date: December 20, 2007
    Inventors: Sang-Wook Park, Dae-Won Kim, Eun-Chel Cho
  • Publication number: 20070290284
    Abstract: A detector configuration determines the direction of illumination incident on a photosensitive device. Multiple mask layers include holes which form an interlayer optical path through which radiation reaches a photodetector. The interlayer optical path provides a selected nominal maximum signal angle and the detector senses when radiation is received at or near that angle. In one embodiment, three holes in three metallization layers provide an arbitrarily narrow interlayer optical path with improved angular detection relative to that provided by two holes. An illumination direction-sensing array may use multiple instances of the detector configuration. The detector configuration may provide enhanced utility and economy by being adapted to use only those fabrication steps used for fabricating other primary circuits on an IC.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 20, 2007
    Inventor: Jamie Lyn Shaffer
  • Publication number: 20070290285
    Abstract: A semiconductor device that contains photodiodes whose sensitivity and storage capacity can be increased, and a solid-state image pickup device formed by arranging the photodiodes in an array and its manufacturing method. A first semiconductor region 11 of a second conductivity type is formed on the principal surface of a semiconductor substrate 10 of a first conductivity type. A pixel separating region 14 of the first conductivity type is formed to penetrate through the first semiconductor region 11 to separate the regions of the adjacent photodiodes PD. A second semiconductor region 15 of the second conductivity type used to drain excess charge is formed in semiconductor substrate 10 at a position away from the junction surface between semiconductor substrate 10 and the first semiconductor region 11 and below the junction surface.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 20, 2007
    Applicant: TEXAS INSTRUMENTS, INCORPORATED
    Inventors: Hidetoshi Shimada, Karuya Mori
  • Publication number: 20070290286
    Abstract: A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate (1) in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and a second transistor, the first transistor having a first diffusion layer (2) as a source or a drain where a signal potential corresponding to a signal charge generated by the photodiode is transmitted and held, and the second transistor having a second diffusion layer as a source and a drain where the signal potential is not transmitted.
    Type: Application
    Filed: October 28, 2005
    Publication date: December 20, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mikiya Uchida, Ken Mimuro, Mototaka Ochi
  • Publication number: 20070290287
    Abstract: A photodetector, comprises a first section comprising at least one p-n junction that converts photon energy into a separate charge carrier and hole carrier; and another section of semiconductors of opposing conductivity type connected electrically in series and thermally in parallel in a heat dissipating and electric generating relationship to the cell to augment generation of electric energy of the first section.
    Type: Application
    Filed: July 23, 2007
    Publication date: December 20, 2007
    Inventor: Philip Freedman
  • Publication number: 20070290288
    Abstract: A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 20, 2007
    Inventors: Sheng Hsu, Jong-Jan Lee, Jer-Shen Maa, Douglas Tweet
  • Publication number: 20070290289
    Abstract: A diode conducts current between an anode terminal and a cathode terminal. The diode includes a parasitic transistor formed between one of the terminals and the substrate. The diode also includes a second transistor that competes with the parasitic transistor to direct current flow between the anode terminal and the cathode terminal.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 20, 2007
    Applicant: Polar Semiconductor, Inc.
    Inventors: Steven L. Kosier, David M. Elwood
  • Publication number: 20070290290
    Abstract: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 20, 2007
    Applicant: HIMAX TECHNOLOGIES, INC.
    Inventor: Tung-Yang Chen
  • Publication number: 20070290291
    Abstract: High voltage devices capable of preventing leakage current caused by inversion layer. In the high voltage device, a substrate comprises an active area formed therein, a source region and a drain region formed in the substrate, and a gate structure is formed on the active area to define a channel region in the substrate between the drain region and the source region, wherein the active area has at least one side extending along a direction perpendicular to the channel direction of the channel region, such that the gate structure without completely covering the extension.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiann-Tyng Tzeng, Li-Huan Zhu
  • Publication number: 20070290292
    Abstract: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.
    Type: Application
    Filed: July 19, 2007
    Publication date: December 20, 2007
    Inventors: Tai-Peng Lee, Barbara Haselden
  • Publication number: 20070290293
    Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
    Type: Application
    Filed: August 28, 2007
    Publication date: December 20, 2007
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jigish Trivedi, Robert Patraw, Kevin Beaman, John Smythe
  • Publication number: 20070290294
    Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.
    Type: Application
    Filed: August 28, 2007
    Publication date: December 20, 2007
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: John Smythe, William Budge
  • Publication number: 20070290295
    Abstract: At least one fuse pattern extending in a first direction is formed on a fuse region of a substrate. A preliminary first insulating pattern is formed on the fuse region to cover the fuse pattern. A conductive layer is formed on the preliminary first insulating pattern. The conductive layer and the preliminary first insulating pattern are etched to form at least one fence extending in a second direction substantially perpendicular to the first direction. Related fuse structures are also disclosed.
    Type: Application
    Filed: March 5, 2007
    Publication date: December 20, 2007
    Inventor: Won-Chul Lee