Abstract: The invention pertains to a method for manufacturing an electronic component with a semiconductor element (1) that is contacted and fixed on a substrate surface (2). The method is characterized in that the rear side of the semiconductor element and/or the substrate surface is coated with an adhesive structure consisting of a first component (3) that solidifies, particularly hardens or cures, and an electrically conductive second component (4) that does not solidify, wherein the semiconductor element is bonded to the substrate surface in a contacting fashion. The electronic component is characterized in that a structured adhesive layer arranged between the semiconductor element and the substrate surface comprises a solidifying first component (3) and an electrically conductive non-solidifying second component (4).

Abstract: The invention provides a semiconductive device that comprises interlevel dielectric layers that are located over devices. The interlevel dielectric layers have a dielectric constant (k) less than about 4.0. Interconnects are formed within or over the interlevel dielectric layers. The semiconductive device further comprises an aluminum oxide barrier located between at least one pair of the interlevel dielectric layers. The aluminum oxide barrier is substantially laterally co-extensive with the interlevel dielectric layers.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode.

Abstract: An electrode pad on a semiconductor substrate having a reduced capacitance of an electrode pad portion and allowing control of a characteristic impedance for a practical electrode pad size is provided.

Abstract: Via layout with via groups placed in an interlocked arrangement for suppressing the crack propagation along the domain boundary between the via groups. A structure has a metal via pattern located in a dielectric layer and having a first via group and a second via group adjacent to each other. The first via group has at least two first line vias extending in a first direction, and the second via group has at least two second line vias extending in a second direction. The first via group and the second via group are placed in an interlocked arrangement, and a domain boundary along the first direction or the second direction between the first via group and said second via group is not straight.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.

Abstract: A semiconductor device includes a memory chip having a memory cell array including a plurality of memory blocks, wherein the memory chip includes a plurality of test pads for testing operations of the memory blocks, and an interface chip including a penetrating electrode and a plurality of interface circuit blocks, wherein at least one of the interface circuit blocks is electrically connected to at least one of the memory blocks via the penetrating electrode, and wherein the interface chip includes a plurality of bonding pads for interfacing between the interface circuit blocks and an external device.

Abstract: A stacked die package for an electromechanical resonator system includes a chip that contains an electromechanical resonator bonded onto the control chip for the electromechanical resonator by a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package provides small package footprint and/or low package thickness, as well as low thermal resistance and a robust conductive path between the chip that contains the electromechanical resonator and the control chip.

Abstract: An electronic device includes a stack of electronic components and connecting elements. The component stack includes two components stacked one on top of another by their top sides. Contact areas are arranged on the top sides of the components, and the contact areas include external contact structures as connecting elements. The external contact structures on the contact areas include rib and/or trench structures oriented in such a way that the rib and/or trench structures of the contact areas of the components stacked one on top of another cross or intersect each other.

Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.

Abstract: A mold for forming a conductive bump, a method of fabricating the mold, and a method of forming a bump on a wafer using the mold are provided. The bump can be formed by employing various materials, the mold can be repeatedly used several times because the mold is not damaged, and due to a high precision, the pitch of the bumps is not limited. The mold for forming a conductive bump comprises a first substrate having a groove to form a bump; a second substrate for vacuum adsorption formed below the first substrate, and having a through-hole in communication with the groove; and a mask layer formed on the first substrate, and used to form the groove.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: Disclosed is a resin paste for die bonding comprising a butadiene homopolymer or copolymer (A) having a carboxylic acid terminal group, a thermosetting resin (B), a filler (C), and a printing solvent (D), wherein the elastic modulus of the resin paste following drying and curing is within a range from 1 to 300 MPa (25° C.). The solid fraction is preferably from 40 to 90% by weight, the thixotropic index is preferably from 1.5 to 8.0, and the viscosity (25° C.) is preferably from 5 to 1,000 Pa·s. Using this resin paste, a semiconductor device is produced by a method comprising (1) applying a predetermined quantity of the resin paste to a substrate, (2) drying the resin paste to effect B-staging of the resin, (3) mounting a semiconductor chip on the B-staged resin, and (4) conducting post-curing of the resin.

Abstract: A device configured to have a nanowire formed laterally between two electrodes includes a substrate and an insulator layer established on at least a portion of the substrate. An electrode of a first conductivity type and an electrode of a second conductivity type different than the first conductivity type are established at least on the insulator layer. The electrodes are electrically isolated from each other. The electrode of the first conductivity type has a vertical sidewall that faces a vertical sidewall of the electrode of the second conductivity type, whereby a gap is located between the two vertical sidewalls. Methods are also disclosed for forming the device.

Abstract: An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe.

Abstract: A semiconductor device having a wire loop and a method and apparatus for manufacturing the semiconductor device are provided. The semiconductor device includes a wiring board having an electrode pad, a semiconductor chip having a bonding pad and attached on a top surface of the wiring board while exposing the electrode pad, and a wire loop electrically connecting the bonding pad of the semiconductor chip to the electrode pad of the wiring board. The wire loop includes a contact ball bonded on the bonding pad and a wire extending from a side portion of the contact ball and bonded on the electrode pad of the wiring board.

Abstract: A bonding wire takes the form of a ribbon, and a bond includes such a bonding wire. The bonding wire includes at least two layers having different current carrying capacity.

Abstract: An electrical component includes a substrate that includes one or more terminal contacts for one or more electrical component structures on a surface of the substrate. The electrical component also includes a cover having a first surface and a second surface. The cover includes one or more terminal pads on the first surface, one or more terminal contacts on the second surface, and electrical throughplatings electrically connecting the terminal pads and the contacts. The cover is on the surface of the substrate. The electrical component also includes a conductive adhesive is in one or more cavities between the substrate and the cover.

Abstract: An active device array mother substrate suitable for being divided into a plurality of active device array substrates is provided. The active device array mother substrate includes a substrate, multiple sets of active device arrays, and a plurality of outer circuit pads. The substrate has a plurality of predetermined regions defining the positions of the active device array substrates respectively. Furthermore, the multiple sets of active device arrays are disposed in the predetermined regions respectively and the pads are also disposed in the predetermined regions. The pads and the active device arrays in the predetermined regions are electrically connected to each other. Particularly, the pads of at least two predetermined regions are electrically connected to each other.

Abstract: Methods, systems, and apparatuses for integrated circuit (IC) package vertical interconnection are described herein. In an aspect of the invention, an IC package includes an IC die with contact pads. The IC package also includes interconnect members which are coupled to the die at the contact pads. An encapsulating material encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. A second IC package is coupled to the first IC package through the plurality of interconnect members of the first IC package. In an example, solder balls attached to a bottom of the second IC package are coupled to the contact surfaces of the interconnect members to couple the first IC package and the second IC package.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane.

Abstract: Disclosed area compositions comprising: a polyimide resin with a water absorption of 2% or less and, optionally, one or more of an electrically insulated filler, a defoamer and a colorant and one or more organic solvents. The compositions are useful as encapsulants and have a consolidation temperature of 190° C. or less.

Abstract: The invention concerns a device for stirring a liquid (L) in a reactor and for injecting a gas in said liquid, comprising a self-aspirating turbine (5) for producing a gas-liquid dispersion, an axial flow rotor (4) with axial flow for collecting said dispersion, and means for directing the gas-liquid dispersion towards said axial flow rotor (4) with axial flow. The invention is characterized in that said means comprise deflecting means (8) integrated in the self-aspirating turbine (5). The invention is applicable to the biological treatment of industrial effluents.

Abstract: A sparger includes a conduit and a plurality of dispensing tubes extending therefrom. The dispensing tubes can be roll pins. The dispensing tubes can extend into the inner diameter of the conduit. A dissipater can be positioned to interrupt the flow of fluid exiting from the dispensing tubes.

Abstract: Systems and methods for reducing temperature variations induced by fluid handling equipment in process fluids by separating heat-producing portions of the control equipment from portions of the equipment which handle or are in close proximity to a fluid flow path. In one embodiment, the fluid handling components are contained in a first enclosure, while the heat-generating components are contained in a second enclosure. An air gap is maintained between the two enclosures to provide thermal isolation of the fluid handling components from the heat-generating components. In one embodiment, the air gap is maintained by connecting the two enclosures using insulating spacers. Interconnects between components in the two enclosures may be routed through an insulating tube that is sealed at each end to prevent heat transfer through the tube.

Abstract: A method for producing a lens mold suitable for manufacturing a field of micro-lenses is disclosed. The method includes the step of molding the lens mold from a sheaf of closely-packed balls held by a hexagonal mounting.

Abstract: In one aspect, the present invention relates to a method of making multi-phase particles that include nanoparticulates and matrix, which maintains the nanoparticulates in a dispersed state. A flowing gas dispersion is generated that includes droplets of a precursor medium dispersed in a gas phase. The precursor medium contains liquid vehicle and at least a first precursor to a first material and a second precursor to a second material. The multi-phase particles are formed from the gas dispersion by removing at least a portion of the liquid vehicle from the droplets of precursor medium. The nanoparticulates in the multi-phase particles include the first material and the matrix in the multi-phase particles includes the second material.

Abstract: The invention relates to a blank for a tooth replacement part comprising a first section having a shape of a section of a tooth or a tooth replacement part, and a second section comprising a material stock, which can be machined to a desired shape, e.g. by milling it off. The invention further relates to a method of producing a tooth replacement part, wherein a blank is machined by a removing process such as milling or laser machining to obtain a desired shape of a tooth replacement part, wherein only portions of the blank are machined while other portions remain unmachined because they already have the desired final shape. The invention also relates to a set comprising at least one above-defined blank and at least one counterpart, which is provided with a receptacle for holding the blank adapted at least partially to the first section and/or to the second section.

Abstract: A production light comprising a housing (1) with a synchronous driving mechanism with at least two rollers (2,4) where a film/band (6) of gels (8) is wound and taut between the rollers (2,4) so the aperture (10) of the production light is covered by the film/band (6), characterized in that the film/band (6) comprises of a plurality of separate sections of gels (8) where the gels (8) are attached to the film/band (6) by fastening means in such a way that each section of gel (8) is easily mounted or remounted onto the film/band (6).

Abstract: A lithography method includes the steps of: A) filling a mold having a patterned surface with a phase change composition at a temperature above the phase change temperature of the phase change composition; B) hardening the phase change composition to form a patterned feature; C) separating the mold and the patterned feature; optionally D) etching the patterned feature; optionally E) cleaning the mold; and optionally F) repeating steps A) to D) reusing the mold. The PCC may include an organofunctional silicone wax.

Abstract: The invention concerns the manufacture of containers, in particular bottles, from thermoplastic material blanks, in particular PET, whereby a mold is used including at least one capacitive sensor inserted in its wall defining the molding cavity, the front side of the capacitive sensor being flush with the molding surface of the molding cavity and being configured in the continuity of the surface.

Abstract: An apparatus and method for making a mold or mold face includes a container having at least one opening. The apparatus also includes a flexible membrane that is retained to the container that extends across the opening of the container. The apparatus for making a mold further includes support media that is disposed within the container along with a vacuum valve that is connected to the container.

Abstract: A laminate oleophilic reformative clay and a method of production for the same are described, and a material and method of production for ABS nano-metric composite material produced by the same are also described. The ABS nano-metric composite material is waterproof for a self-cleaning ability and has enhanced strength. The cost to produce the ABS nano-metric composite material is also reasonable. The ABS nano-metric composite material is made of ABS substrate formed from ABS material and laminate oleophilic reformative clay uniformly distributed in the ABS substrate.

Abstract: A hard disk drive inner part formed of a resin which exhibits well-balanced low outgassing properties, ultrasonic cleaning resistance, low ionic contamination properties, low particulate contamination properties, repeated removability, heat resistance, specific gravity, and water-absorbing properties. The hard disk drive inner part includes a resin composition which includes a polyphenylene ether resin (A).

Abstract: In one aspect, the invention provides a body comprising particles containing an insulating aerogel material intermingled with particles containing a phase change material, and a binder forming a matrix retaining the intermingled particles. In another aspect, the invention provides a method of forming an insulating body comprised by applying first and second streams onto a substrate; the first stream comprising a binder and the second stream comprising particles containing aerogel material; and simultaneously applying a phase change material onto the substrate.

Abstract: This invention relates to rigid porous carbon structures and to methods of making same. The rigid porous structures have a high surface area which are substantially free of micropores. Methods for improving the rigidity of the carbon structures include causing the nanofibers to form bonds or become glued with other nanofibers at the fiber intersections. The bonding can be induced by chemical modification of the surface of the nanofibers to promote bonding, by adding “gluing” agents and/or by pyrolyzing the nanofibers to cause fusion or bonding at the interconnect points.

Abstract: A method for forming a self-planarizing wiring layer for a semiconductor device includes forming a mat of filament material over a semiconductor substrate, and infusing the mat with a conductive material formed at a thickness substantially corresponding to the thickness of the mat of filament material. The mat is then patterned so as to expose regions where conductive wiring is not to be present, and the infused conductive material is removed from the exposed regions. The exposed regions of the mat are infused with an insulating material, formed at a thickness substantially corresponding to the thickness of the mat of filament material.

Abstract: An apparatus for trimming plastic from a plastic bottle forming a portion of a plastic one-bottle or multi-bottle blow molded log includes a drive member that moves the log along a path and a punch movable with respect to the drive member. The punch moves along the path with the log and engages the log to trim plastic from the log.