Abstract: A system and method for remotely monitoring load tap changes on utility-type equipment are disclosed. In one example embodiment, a sensor measures a voltage before a tap change and compares the measured voltage to a voltage after the tap change. From this information, the direction of the tap change and the distance traveled can be determined. The system and method can also include a timer to measure an elapsed time required to complete a particular tap change and use this time information to determine the distance traveled. The direction of the tap change can be determined from a sensor that triggers the timer. The system and method thereby enable efficient and cost-effective remote monitoring of load tap changes and positions.

Abstract: An improved power supply unit includes a DC power source having a positive terminal and a negative terminal, and a voltage regulating circuit that includes a plurality of elements coupled in series between the positive and negative terminals of the DC power source to regulate the power supply signals supplied thereto to effectively cancel ripple and noise in such power supply signals. In one embodiment, the series-coupled elements include at least one resistor and a transconductive element having a characteristic transconductance value of T. The at least one resistor provides a resistance substantially equal to 1/T. The transconductive element and the one resistor cooperate to suppress spurious voltage level variations produced by the DC power source. The transconductive element may be realized by a thermionic triode, field effect transistor or other suitable device.

Abstract: A switching regulator is disclosed that is able to prevent reverse direction current flow without using a dedicated diode even when a PMOS transistor is used as a switching transistor of a step-down switching regulator. A selection circuit is provided to control connection of the substrate gate of the switching transistor, and a control circuit controls the selection circuit to connect the substrate gate to the drain of the switching transistor when the voltage on an input terminal of the switching regulator is less than or equal to the voltage on the output terminal of the switching regulator, and connect the substrate gate to the source of the switching transistor when the voltage on the input terminal is greater than the voltage on the output terminal.

Abstract: A method for controlling the output of a switching power converter to account for high and low current loads is disclosed. A reference voltage is generated with a voltage reference generator representing a desired DC output voltage for the power converter. Then the DC voltage output of the power converter is sensed with a digital control system and generating switching control signals to control the operation thereof to minimize the difference between sensed DC voltage and the reference voltage. The current through the power converter is then determined and the operation of the voltage reference generator controlled to set the value of the reference voltage to a level that is a function of the sensed current so as to anticipate future current loading.

Abstract: An apparatus and method of control for converting DC (direct current) power from a solar photovoltaic source to AC (alternating current) power. A novel DC-to-AC power converter topology and a novel control method are disclosed. This combination of topology and control are very well suited for photovoltaic microinverter applications. Also, a novel variant of this control method is illustrated with a number of known photovoltaic DC-to-AC power converter topologies. The primary function of both control methods is to seek the maximum power point (MPP) of the photovoltaic source with novel, iterative, perturb and observe control algorithms. The control portion of this invention discloses two related control methods, both an improvement over prior art by having greatly improved stability, dynamic response and accuracy.

Abstract: Circuits for regulating a voltage or current to a load(s).

Abstract: A voltage verification unit and method for determining the absence of potentially dangerous potentials within a power supply enclosure without Mode 2 work is disclosed. With this device and method, a qualified worker, following a relatively simple protocol that involves a function test (hot, cold, hot) of the voltage verification unit before Lock Out/Tag Out and, and once the Lock Out/Tag Out is completed, testing or “trying” by simply reading a display on the voltage verification unit can be accomplished without exposure of the operator to the interior of the voltage supply enclosure. According to a preferred embodiment, the voltage verification unit includes test leads to allow diagnostics with other meters, without the necessity of accessing potentially dangerous bus bars or the like.

Abstract: A probe apparatus configured to measure a set of electrical characteristics in a plasma processing chamber, the plasma processing chamber including a set of plasma chamber surfaces configured to be exposed to a plasma is disclosed. The probe apparatus includes a collection disk structure configured to be exposed to the plasma, whereby the collection disk structure is coplanar with at least one of the set of plasma chamber surfaces. The probe apparatus also includes a conductive path configured to transmit the set of electrical characteristics from the collection disk structure to a set of transducers, wherein the set of electrical characteristics is generated by an ion flux of the plasma. The probe apparatus further includes an insulation barrier configured to substantially electrically separate the collection disk and the conductive path from the set of plasma chamber surfaces.

Abstract: A probe card is used in conducting a visual test for a target test object through simultaneous contact of the probe card with each and every electrode pad of the target test object. The probe card includes a plurality of probes composed of conductive wire strands and having elastically deformable contact parts so curved as to make contact with electrode pads of a target test object. The contact parts are oriented in one and the same direction and extend in a parallel relationship with one another. The probe card further includes a first insulating block for fixedly securing one end parts of the probes, a second insulating block for fixedly securing the other end parts of the probes and a mounting plate for holding the first and second insulating blocks in such a manner that the contact parts of the probes protrude outwardly.

Abstract: A magnetic sensor that prevents offset voltage from changing as time elapses. The magnetic sensor detects change in the direction of the magnetic field when the electric resistances of magnetic resistors change. The magnetic resistors of the magnetic sensor each include a heat treatment section formed by performing a pre-trimming heat treatment.

Abstract: There is described a sensor comprising an excitation winding, a signal generator operable to generate an excitation signal and arranged to apply the generated excitation signal to the excitation winding, a sensor winding electromagnetically coupled to the excitation winding and a signal processor operable to process a periodic electric signal generated in the sensor winding when the excitation signal is applied to the excitation winding by the signal generator to determine a value of a sensed parameter. The excitation signal comprises a periodic carrier signal having a first frequency modulated by a periodic modulation signal having a second frequency, the first frequency being greater than the second frequency. In this way, the sensor is well suited to using digital processing techniques both to generate the excitation signal and to process the signal induced in the sensor windings. In an embodiment, the sensor is used to detect the relative position of two members.

Abstract: An improved rotation angle detecting device that detects a rotation angle of a first member relative to a second member is proposed. The rotation angle detecting device includes a magnet unit fixed to the first member and a pair of magnetic sensors fixed to the second member to provide output signals whose phase is different from each other at 90 degrees in angle. The magnet unit includes a pair of disk plates that has the same magnetic poles at the same circumferential positions and is disposed at a prescribed axial distance and a shaft that is made of magnetic material to support the disk plates at the center thereof. The magnetic unit provides a uniform magnetic field in a space around the shaft between the pair of disk plates, and a pair of magnetic sensors is disposed in the space.

Abstract: A magnetic screening system including an arrangement of gradiometers each including at least three magnetometers, a gradiometer processor in communication with the magnetometers that scales outputs from the magnetometers with unequal weights and combines the scaled outputs to orient a direction of sensitivity of the respective gradiometer toward a volume of interest and at least one arrangement processor in communication with the arrangement of gradiometers that uses the gradiometers in a collective manner to detect a target object.

Abstract: A sensor has a substrate having a mechanically deformable region, a magnetostrictive spin-valve sensor element being arranged to detect a mechanical deformation of the mechanically deformable region. On the substrate, there is a device for generating a controllable magnetic field by which a performance of the sensor element is influenced.

Abstract: An embodiment of the invention relates to a device for performing NMR or ESR analysis. The device comprises a detection unit, a magnet, and a disk having a magnetic pattern. The detection unit comprises a sample holding space for holding a sample and a microcoil for detecting NMR or ESR signals generated within the sample. The magnet generates a static magnetic field within the sample. The disk and magnetic pattern, when rotating, generate an excitation magnetic field, which, together with the static magnetic field, creates an NMR or ESR within the sample. Other embodiments of the invention encompass methods for performing NMR or ESR analysis using the device and methods of making such devices.

Abstract: In a method and apparatus for magnetic resonance imaging based on a partially parallel acquisition (PPA) reconstruction technique, a number of partial k-space data sets are acquired with a number of component coils, the totality of the partial data sets forming a complete k-space data set, the respective coil sensitivity of each component coil is determined based on at least one part of the complete k-space data set, any partial k-space data set is transformed via a PPA reconstruction technique dependent on the determined coil sensitivities, and the transformed partial data sets are superimposed to obtain a low-artifact image data set.

Abstract: An MRI apparatus is provided. The MRI apparatus includes a main magnet (12) for generating a main magnetic field in an examination region, a plurality of gradient magnets (16) for generating magnetic field gradients in the main magnetic field, a radio frequency coil (22) for transmitting radio frequency signals into the examination region and exciting magnetic resonance in a subject disposed therein, and a radio frequency coil for receiving the magnetic resonance signals from the subject. The MRI apparatus also includes subject support (52) for supporting the subject, a position controller (60) for controlling the position of the subject support within the examination region, and a position encoder (53) for directly measuring the position of the subject support.

Abstract: A unilateral NMR sensor comprising a ferromagnetic yoke; a permanent magnet arranged on the yoke; a pole piece on the magnet; the pole piece including an air-pole piece interface surface whose shape corresponds to an equipotential contour of magnetic scalar potential.

Abstract: A Magnetic Resonance Imaging (MRI) system having a vacuum vessel positioned about an imaging volume, one or more high temperature superconducting coils positioned within the vacuum vessel, and a cryocooler coupled to the vacuum vessel to operate the superconducting coil at a temperature above 10 K. At least one gradient coil is positioned between an imaging volume and the superconducting coil without any thermal shielding interposed between the gradient coil and the superconducting coil. A method of forming an MRI system includes forming at least one winding of the main field generating coils with high temperature superconducting material, positioning the winding in a vessel for receiving cryogenic fluid, and positioning a gradient coil between the imaging volume and the winding without placing a thermal radiation shield between the gradient coil and the winding.

Abstract: A system, method, and computer-readable medium for magnetic resonance diffusion anisotropy image processing are provided.

Abstract: A cold mass for a superconducting magnet system in one example comprises a superconducting magnet, a cryogenic cooling circuit, and a magnet and cooling circuit support. The magnet and cooling circuit support comprises a substantially conductive coupler in a discrete path that serves to couple the superconducting magnet and the cryogenic cooling circuit.

Abstract: A method of processing an electromagnetic wavefield response in a seabed logging operation. The wavefield is resolved into upgoing and downgoing components. The downgoing component represents reflections from the sea surface while the upgoing component represents reflections and refractions from subterranean strata. The upgoing component is then subjected to analysis.

Abstract: Misalignment of the transmitter and receiver coils of an induction logging tool is determined by positioning the logging tool with a coil axially encompassing the transmitter coil and/or the receiver coil, and activating the transmitter at a plurality of rotational angles.

Abstract: Method and device for determining the formation factor of underground zones from drill cuttings. The device comprises a cell (1) associated with a device for measuring the electrical conductivity of the cell with the content thereof. The cell containing the drill cuttings is filled with a first electrolyte solution (A) of known conductivity (?A). After saturation of the drill cuttings by first solution (A), the global electrical conductivity (?*A) of the cell with the content thereof is determined. After discharging first solution (A), the cell containing the drill cuttings is filled with a second electrolyte solution (B) of known conductivity (?B), and the global electrical conductivity (?*B) of the cell containing the second solution and the cuttings saturated with the first solution is determined. The cuttings formation factor (FF) is deduced therefrom by combination of the measurements.

Abstract: A tracked vehicle has a power control apparatus for controlling charging and discharging of a plurality of storage devices. A voltage measuring device measures voltages of the respective storage devices, and a current measuring device measures currents flowing through the respective storage devices. A status detecting device detects the operating status of each storage device based on values measured by the voltage and current measuring devices; and a charging/discharging controlling device controls currents, voltages, or power according to the operating status of each storage device detected by the status detecting device, to charge or discharge the storage devices.

Abstract: A breakdown inspection apparatus for a wire includes a power supply applying a voltage to the wire and an electric field sensor detecting an electric field generated around the wire by the applied voltage so as for a user to determine according to variation of the electric field if there is an open defect in the wire.

Abstract: An improved prober for an electronic devices test system is provided. The prober is “configurable,” meaning that it can be adapted for different device layouts and substrate sizes. The prober generally includes a frame, at least one prober bar having a first end and a second end, a frame connection mechanism that allows for ready relocation of the prober bar to the frame at selected points along the frame, and a plurality of electrical contact pins along the prober bar for placing selected electronic devices in electrical communication with a system controller during testing. In one embodiment, the prober is be used to test devices such as thin film transistors on a glass substrate. Typically, the glass substrate is square, and the frame is also square. In this way, “x” and “y” axes are defined by the frame.

Abstract: An apparatus including a positioner control device, a measuring device and a control routine. The positioner control device is communicatively coupled to a chamber of a charged particle beam device (CPBD) and is configured to individually manipulate each of a plurality of probes within the CPBD chamber to establish contact between ones of the plurality of probes and corresponding ones of a plurality of contact points of a sample positioned in the CPBD chamber. The measuring device is communicatively coupled to the CPBD and the positioner control device and is configured to perform one of a measurement and a detection of a characteristic associated with one of the plurality of contact points. The control routine is configured to at least partially automate control of at least one of the CPBD, the positioner control device and the measuring device.

Abstract: A control unit of a wafer prober for implementing wafer examination, using a probe card including a multiple number of probes, executes a multiple number of measuring operations by bringing the probes of the probe card into contact with bonding pads formed on a wafer and by measuring the electric characteristics between predetermined pads of the bonding pads, each of the measuring operations being implemented after varying the relative position between the probe card and the wafer, in directions parallel to the face of the wafer. The control unit, upon execution of each of the measuring operations, implements the measuring operation after adjusting the relative position between the probe card and the wafer so that the contact position of each probe of the probes against each pad of the bonding pads is separated from all the positions at which the probes have already touched that pad of the bonding pads for a predetermined number of different times.

Abstract: A chip tester is mounted on a circuit board for testing validity of a chipset includes a base member that receives the chipset thereon and that has a plurality of testing contacts in electrical communication with the circuit board and, and a top cover that is mounted on the base member to confine the chipset therebetween and has a test opening for access to the chip set. When the chipset is confined between the top cover and the base member, electrical contacts of the chipset are in contact with the testing contacts in the base member.

Abstract: Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.

Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host.

Abstract: The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms a capacitive divider with the inherent capacitances of the automatic test equipment and the device under test (DUT). The voltage characteristics of the capacitive divider are used to drive voltage signals across the interface capacitor to test the DUT. In either direction (i.e. from the automatic test equipment to the DUT or vice versa), by altering the voltage output high amplitude of the driver and/or the voltage input high amplitude of the load, the DUT is validly tested through the interface capacitor. Thus, even if all I/O bumps have an oxide layer, the device may still be validly tested.

Abstract: A data acceleration device may include a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node which is electrically coupled with the first node, in response to an output signal from the pull-up driver, a first pull-down circuit for pull-down driving the second node, in response to an output signal from the pull-down driver, a delay circuit for delaying a signal from the second node by a preset time to output a delayed signal, a first switch for switching an operation of the first pull-up circuit in response to an output signal from the delay circuit, and a second switch for switching an operation of the first pull-down circuit in response to the output signal from the delay circuit. Also, there is presented a data transmission apparatus including the data acceleration device.

Abstract: A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

Abstract: In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of the inputs. The pulse generator is configured to generate a pair of control signals to the passgates, and is configured to generate pulses on the pair of control signals to open the passgates. Each of the latch elements is connected to a respective input and is configured to latch the signal on the respective input when passgates are open and to retain the signal on the respective input when the passgates are closed.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

Abstract: A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.

Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are synthesized to generate a composite clock having equal pulse intervals. Thus, even when the semiconductor integrated circuit is supplied with external clocks of lower frequencies, it is possible to operate the semiconductor integrated circuit at high speed. For example, the internal circuit can be operated and tested at high speed by using a low-cost LSI tester having a low clock frequency. This can reduce the testing cost of the semiconductor integrated circuit, allowing a reduction in chip cost.

Abstract: A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision without being affected by various fluctuations and variations, and a PLL circuit including the lock-detection circuit. The range corresponding to a phase difference between first and second output signals is determined to be a locked-state range, where the phase of each of the first and second output signals delays or advances with reference to that of an oscillation-output signal transmitted from a voltage-controlled-oscillation circuit.

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupled to said input signal and having a control input for delay adjustment, a first amplitude control device in series with the first variable delay device, providing at its output an amplitude controlled signal and having a control input for adjusting the output amplitude, a phase detector with linear characteristic having its two inputs connected to the output of the fixed-delay device and the output of the first amplitude control device, an error measurement device having its negative input connected to the output of the phase detector and its positive input connected to a control signal, an amplifier with low-pass characteristic having its input connected to the output of the error measurement device and its output to the control input of the firs

Abstract: An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steering FET controlled by an input signal drives a first output high via a circuit. That first output going high, after a delay, drives a second output high. When the input goes low, a second steering FET controlled by the input signal drives the second output low. That second output going low, after a delay, drives the first output low. No latching is provided in the present invention.

Abstract: A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for use by the signal treating unit. (c) A clock simulating unit occasionally coupled with at least one of the clock signal and the clock generator provides a simulated clock signal generally similar to the internal clock signal when either of the clock signal or the internal clock signal is interrupted. (d) A control unit coupled with the signal treating unit, at least one of the clock signal input locus and the internal clock generator for selectively coupling one of the internal clock signal and the simulated clock signal for use by the signal treating unit.

Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.

Abstract: A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.

Abstract: The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch transistor has a first terminal coupled to a first supply voltage (102), a second terminal coupled to an internal voltage rail (108), a gate coupled to an activation signal source (110), and a body coupled to a bias signal source (114). A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source when that transistor is shut off. A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on.

Abstract: In a method and apparatus for generating a power supply voltage, an integrated circuit including an adaptive power supply voltage circuit is provided where a target signal is generated representing an ideal or approximated ideal performance characteristic of a functional block operating with the power supply voltage. A generated functional block test signal is generated representing the performance characteristic of the functional block under these conditions. The adaptive power supply voltage circuit compares the target signal with the generated functional block test signal and adjusts the power supply voltage continuously until the target signal and generated functional block test signal are substantially equal. When the target signal and generated functional block test signal are substantially equal, the power supply voltage is locked for subsequent use. By optimizing the power supply voltage, minimal power dissipation is provided.