Abstract: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein a terminal pads is formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL and a second die is attached on the second dielectric layer. A surrounding material surrounds the second die. A third dielectric layer is formed over the second die and the surrounding material. A second re-distribution conductive layer (RDL) is formed on the third dielectric layer. A protection layer is formed over the second RDL.

Abstract: A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate.

Abstract: To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract: A stacked integrated circuit package-in-package system is provided including forming a substrate having a top surface and a bottom surface, mounting a first device over the top surface, stacking a second device over the first device in an offset configuration, connecting a first internal interconnect between the first device and the bottom surface, connecting a second internal interconnect between the second device and the bottom surface, and encapsulating the first device and the second device.

Abstract: A stacked integrated circuit package-in-package system is provided including forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.

Abstract: Provided are a stack package and a stack packaging method. The stack package includes: a first package; and a second package stacked on the first package, wherein external leads of the first package and the second package are directly connected to one another and inner leads thereof are arranged in different shapes so that the Chip Select signal of the second package are input through a No Select pin of the first package.

Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.

Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

Abstract: A semiconductor device includes a first semiconductor chip having first connecting pads arranged at first interval and a second semiconductor chip having second connecting pads arranged at second interval, the second interval being larger than the first interval, in which the first semiconductor chip includes the first connecting pads not connected to the second connecting pads and the first connecting pads not connected to the second connecting pads function as tilt adjustment pads adjusting tilt of bonding wires connecting the first connecting pads and the second connecting pads.

Abstract: An image sensor package comprises a substrate, a chip mounted over the substrate, A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the micro lens. A redistributed conductive layer is formed over the molding material to connect to a pad of the chip. Metal pads are formed on via structure as connecting points with PCB. A cover layer is formed over the substrate to isolate the metal pads.

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.

Abstract: A high power semiconductor package includes a substrate including a base metal layer, a base insulation layer formed on the base metal layer, and a plurality of conductive patterns formed on the base insulation layer. In one embodiment one or more high power semiconductor chips are mounted on the substrate, each including a plurality of bonding pads, one or more first package leads having end portions that are electrically connected to the corresponding conductive patterns, and a second lead having an end portion electrically which may be connected to either the base insulation layer or the base metal layer.

Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

Abstract: A semiconductor device of the present invention includes: a wiring board 4 in which a conductive wiring 6 is formed on an insulating substrate 5 having an opening 5a; a semiconductor element 2 that has a circuit forming region 2a and an electrode pad 3, and is mounted on the wiring board with the circuit forming region facing the opening, the electrode pad being connected electrically to the conductive wiring via a protruding electrode 3a; a sealing resin 7 that covers the connected portion between the electrode pad and the conductive wiring; a heat dissipating member 9 that is disposed so as to have a portion facing the opening; and a filling material 8 that has a heat conductivity higher than that of the sealing resin, and is filled into the opening, so as to be in contact with the circuit forming region of the semiconductor element and the heat dissipating member. Even when the wiring board has a small area, heat dissipation efficiency can be ensured, and low cost manufacture can be achieved.

Abstract: The semiconductor device is manufactured by forming a lower electrode layer 2 having a predetermined pattern on a semiconductor substrate 1 and forming an upper electrode layer 3 on a part of the top surface of the lower electrode layer 2, while holes 2X extending in the direction of thickness are formed on the top surface of the lower electrode layer 2 below the upper electrode layer 3, and the depth of holes 2X is smaller than the thickness of the lower electrode layer 2.

Abstract: Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250° C. and above. According to a first embodiment, the UBM structure comprises layers of Ni—P, Pd—P, and gold, wherein the Ni—P and Pd—P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni—P and gold, wherein the Ni—P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd—P, Ni—P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure.

Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

Abstract: Disclosed is a method of manufacturing a hybrid structure of multi-layer substrates. The method comprises steps of: separating a border district of at least one metal layer connecting with a border district of the corresponding dielectric layer from adjacent metal layers and adjacent dielectric layers for each multi-layer substrate and connecting a separated border of a metal layer of one multi-layer substrate with a separated border district of a metal layer of another multi-layer substrate to form a connection section. The hybrid structure comprises at least a first multi-layer substrate and a second multi-layer substrate. At least one first metal layer is connected with at least one second metal layer to form a connection section.

Abstract: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.

Abstract: A method for manufacturing a semiconductor device includes the steps of providing an element forming layer on a first surface of a semiconductor substrate, and providing an external connection terminal on a second surface of the semiconductor substrate opposite to the first surface so that the external connection terminal is electrically connected to the element forming layer through a via hole. The via hole is formed through the steps of forming a buried conductor layer on the first surface so as to electrically insulate the buried conductor layer from the semiconductor substrate, forming a communication hole on the second surface so as to communicate it with the buried conductor layer, and electrically connecting the buried conductor layer and the communication hole.

Abstract: In a semiconductor device provided by preventing connection failure caused by misalignment of a semiconductor element having fine and narrow-pitched bumps, a guide for preventing the misalignment is formed by an insulating resin layer around a connection electrode. The insulating resin layer has a thickness defined in relation to an angle ? formed by a side wall of the opening and alignment accuracy ? for the bump. Specifically, the thickness of the insulating resin layer may be ? tan ? or more.

Abstract: A semiconductor device in accordance with the present invention is a mounted body of a semiconductor chip with a plurality of electrode pads arranged in a plurality of stages and a tape wiring board, the average pitch of the electrode pads on the entire semiconductor chip can be reduced, while ensuring stable connectivity, by leading together to the outside of the semiconductor chip two or more wirings of the tape wiring board connected to the electrode pads on the inner side between the electrode pads arranged in a row on the outer periphery of the semiconductor chip.

Abstract: A wafer level package comprises a wafer having a plurality of dice formed thereon; a thinner metal cover with a cavity formed therein attached on the wafer by an adhesive material to improve thermal conductivity of the package. A protection film is formed on back side of the metal cover and filled into the cavity, thereby facilitating for laser marking and obtaining a better sawing quality of the package.

Abstract: Provided is a method of bonding a wire of a semiconductor package, by which a loop height may be reduced and/or a bonding reliability may be enhanced. In the method, a ball bump may be formed on a bonding pad on a semiconductor chip using a capillary through which a wire may be supplied. The wire may then be cut from the ball bump using the capillary. Subsequently, the capillary may be moved to an interconnection corresponding to the bonding pad of the semiconductor chip to perform stitch bonding of the wire supplied through the capillary on the interconnection. The capillary may again be moved to the ball bump formed on the bonding pad to bond the wire on the ball bump.

Abstract: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the surface of the semiconductor substrate from metal of the at least one metal-containing precursor. The invention also includes semiconductor constructions having metal-containing layers which include one or more of copper, cobalt, gold and nickel in combination with one or more of palladium, platinum, iridium, rhodium and ruthenium.

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.

Abstract: A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main electrode (4) towards a predetermined value. The main electrode (4) furthermore comprises a diffusion preventing dopant element (5) for preventing diffusion of the work function modulating element (6) towards and/or into the dielectric (3). Methods for forming such a semiconductor device are also described.

Abstract: A method of forming a metal line pattern for a semiconductor device is provided. The method includes forming a preliminary structure on a semiconductor substrate, having a lower barrier metal layer, a metal layer, and an upper barrier and/or passivation layer having a first thickness; removing a top surface of the passivation layer so that the passivation layer has a second thickness; forming a sub-passivation layer on the passivation layer; forming an adhesion promoter and a photoresist pattern on the sub-passivation layer; and forming a metal line pattern by etching the preliminary structure using the photoresist pattern as an etching mask.

Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.

Abstract: In general, in one aspect, the disclosure describes an apparatus having on die circuitry coupled to at least one input port to receive a signal. A resistor is coupled to the on die circuitry and an off die power supply When a signal of sufficient amplitude is received by the on die circuitry the on die circuitry enables current to flow through the resister and reduces the voltage applied to the on die circuitry via the resister.

Abstract: A method for manufacturing a semiconductor device, the method including: the first step of forming an insulating film over a substrate of which surface side has a first conductive layer, and forming a recess in the insulating film by dry etching; the second step of carrying out plasma treatment for the insulating film with use of a gas that contains carbon or silicon; and the third step of forming a second conductive layer buried in the recess for which the plasma treatment has been carried out.

Abstract: A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (150C), by forming an opening (220) through a top side contact pad (150C) and the semiconductor substrate (110). Conductive material (520, 540, 1110, 1130) is formed in the opening and in contact with the top side pad. The conductive material also provides a backside contact pad (1310). Other embodiments are also provided.

Abstract: There is disclosed an interconnect assembly. In an embodiment, the interconnect assembly includes conductive contact bumps extending from a bumped flex circuit assembly, and conductive contact pads attached to a rigid printed circuit assembly, having a contact surface having a hole and an abutment zone adjacent to the hole, wherein the contact surface is sized to allow contact, prior to disposition within the hole, by the distal end of one of the bumps, and wherein the abutment zone is sized to allow contact of the lateral periphery, and prevent contact of the distal end, of the bump disposed within the hole. A method of forming an interconnect is disclosed. In one embodiment the method includes wiping lateral portions of conductive contact bumps against conductive contact pads, and abutting lateral portions of the bumps against the pads without contacting distal ends of the bumps. Other embodiments are also disclosed.

Abstract: Methods of forming electrical interconnects include forming a first electrically insulating layer on a semiconductor substrate and then forming an opening in the first electrically insulating layer. A step is performed to line a sidewall of the opening with a nitrified first metal layer having a non-uniform nitrogen concentration therein. An electrically conductive pattern is formed in the opening. A second metal nitride layer is provided between the electrically conductive pattern and the nitrified first metal layer.

Abstract: An interconnect element is provided which includes a dielectric element having a major surface. Metal interconnect patterns are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of the major surface. A projecting conductive film extends over the major surface in at least one direction parallel to a plane defined by the major surface such that it contacts the dielectric element along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns.

Abstract: A metal wiring of a semiconductor device and a forming method thereof are provided. A dielectric layer is formed on a semiconductor substrate including a lower metal wiring. A SOG (spin on glass) coating layer is formed on the dielectric layer to inhibit material from another layer from infiltrating into the dielectric layer.

Abstract: A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in at least the interconnection, facing the via, of the interconnections adjacent to the interconnection connected to the via.

Abstract: Provided are a semiconductor package in which bonding pads of a semiconductor chip are electrically connected to interconnection portions by wire-bonding, and a method of manufacturing the semiconductor package. The semiconductor package includes: a substrate; an interconnection portion that is disposed on the substrate and comprises conductive patterns having a first thickness and conductive patterns having a second thickness that is smaller than the first thickness; at least one semiconductor chip that is mounted on the substrate and comprises a plurality of bonding pads; and a plurality of wires electrically connecting the conductive patterns and the bonding pads.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.

Abstract: A semiconductor device having a wafer level chip size package may include a semiconductor substrate having an integrated circuit formed thereon; a plurality of electrode pads formed on the semiconductor substrate; at least one rewiring layer which may include rewiring formed adjacent to the plurality of electrode pads; and a plurality of external electrodes formed on the rewiring layer. The plurality of electrodes and plurality of external electrodes may be sectioned and arranged in four areas having the same shapes. Each area may include a first group of N number of external electrodes arranged along an edge of the semiconductor substrate, a second group of (N?2) number of external electrodes arranged inside the first group of external electrodes, and a plurality of (2N?2) number of electrode pads arranged between the first and second groups of external electrodes.

Abstract: An epoxy resin composition for semiconductor encapsulation which does not contain conductive foreign metallic particles having such a size that they cannot be detected and eliminated by the conventional method for eliminating conductive foreign metallic particles. The epoxy resin composition for semiconductor encapsulation comprises the following components (A) to (D). Conductive foreign metallic particles having a size of 20 ?M or more are substantially not contained in the aforementioned epoxy resin composition. (A) An epoxy resin. (B) A phenol resin. (C) A hardening accelerator. (D) An inorganic filler.

Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.

Abstract: A method of manufacturing a mold for producing a light guide panel and a method of manufacturing the light guide panel using the mold are presented. The mold is made by manufacturing a pattern master on which a fine pattern is formed. A side mold for forming a light-receiving surface of a light guide panel is immersed in an electrolyte containing metal ions, along with the pattern master. A voltage is applied to the electrolyte and the side mold such that the fine pattern on the pattern master is transferred to the side mold with the metal ions in the electrolyte, forming a prism pattern forming portion on the side mold. The prism pattern is formed on a light-receiving portion of the light guide panel using the side mold thus prepared. The shape accuracy and surface accuracy of the prism pattern are improved by using the presented method.

Abstract: A solid carbon has CNTs dispersed therein and is formed about three-dimensionally ordered spherical voids arranged in an opal-like lattice.