Patents Issued in June 12, 2008
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Publication number: 20080135902Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Inventors: Shankar Sinha, Yi He, Zhizheng Liu, Ming-Sang Kwan
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Publication number: 20080135903Abstract: A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventor: Yongjun Jeff Hu
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Publication number: 20080135904Abstract: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.Type: ApplicationFiled: November 7, 2007Publication date: June 12, 2008Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Victor Kairys, Erez Sarig, David Zfira
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Publication number: 20080135905Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.Type: ApplicationFiled: February 19, 2008Publication date: June 12, 2008Applicant: Transmeta CorporationInventors: James B. Burr, Robert Fu
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Publication number: 20080135906Abstract: A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface.Type: ApplicationFiled: October 13, 2006Publication date: June 12, 2008Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Roger Lee, Guoqing Chen, Fumitake Mieno
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Publication number: 20080135907Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.Type: ApplicationFiled: January 29, 2008Publication date: June 12, 2008Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Jeng-Ping Lin, Pei-Ing Lee
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Publication number: 20080135908Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.Type: ApplicationFiled: October 31, 2007Publication date: June 12, 2008Inventors: Young-moon Choi, Ji-young Kim, In-seok Yeo, Sun-woo Lee
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Publication number: 20080135909Abstract: In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.Type: ApplicationFiled: November 30, 2007Publication date: June 12, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toru Takeguchi, Takuji Imamura, Kazushi Yamayoshi, Tomoyuki Irizumi, Atsunori Nishiura, Kaoru Motonami
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Publication number: 20080135910Abstract: In a semiconductor device and a method of fabrication thereof, a semiconductor device comprises a substrate including transistors and partitioned into a memory region and a logic region. A bit line is electrically connected to at least one of the transistors in the memory region. A logic capacitor is formed on the logic region. The logic capacitor includes a logic lower metal electrode of a same layer as that of the bit line, a logic dielectric film, and a logic upper metal electrode.Type: ApplicationFiled: December 6, 2007Publication date: June 12, 2008Applicant: Samsung Electronics Co., Ltd.Inventor: Kwan-young Youn
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Publication number: 20080135911Abstract: A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer. Another method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a portion of a top oxide layer, thereby causing oxygen to be introduced into the nitride layer and depositing a remaining portion of the top oxide layer, thereby assisting in controlling the amount of oxygen introduced into the nitride layer. A further method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby causing oxygen to be introduced into the nitride layer.Type: ApplicationFiled: December 27, 2007Publication date: June 12, 2008Inventor: Boaz Eitan
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Publication number: 20080135912Abstract: A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.Type: ApplicationFiled: October 24, 2007Publication date: June 12, 2008Inventors: Chang-Hyun Lee, Jung-dal Choi
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Publication number: 20080135913Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: ApplicationFiled: December 7, 2006Publication date: June 12, 2008Applicant: Spansion LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Publication number: 20080135914Abstract: In one embodiment, a method for forming a metallic nanocrystalline material on a substrate is provided which includes exposing a substrate to a pretreatment process, forming a tunnel dielectric layer on the substrate, exposing the substrate to a post-treatment process, forming a metallic nanocrystalline layer on the tunnel dielectric layer, and forming a dielectric capping layer on the metallic nanocrystalline layer. The method further provides forming the metallic nanocrystalline layer having a nanocrystalline density of at least about 5×1012 cm?2, preferably, at least about 8×1012 cm?2. In one example, the metallic nanocrystalline layer contains platinum, ruthenium, or nickel. In another embodiment, a method for forming a multi-layered metallic nanocrystalline material on a substrate is provided which includes forming a plurality of bi-layers, wherein each bi-layer contains an intermediate dielectric layer deposited on a metallic nanocrystalline layer.Type: ApplicationFiled: June 29, 2007Publication date: June 12, 2008Inventors: Nety M. Krishna, Ralf Hofmann, Kaushal K. Singh, Karl J. Armstrong
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Publication number: 20080135915Abstract: A non-volatile memory and method of fabricating the same are provided. The method of fabricating a non-volatile memory comprises forming a tunnel insulating layer, a first conductive layer and a first patterned hard mask layer on a semiconductor substrate sequentially. A first conductive pattern is formed by etching the first conductive layer using the first patterned hard mask layer as a mask. The first patterned hard mask layer is removed. A second patterned hard mask layer is formed on an edge of the first conductive pattern. A pair of opposing spacers is formed on sidewalls of the second patterned hard mask layer. The first conductive pattern is etched using the second patterned hard mask layer and the spacers as masks to form a pair of stacked structures comprising the spacers, the second patterned hard mask layer and the remaining first conductive pattern. A pair of inter gate insulating layers are formed on sidewalls of the first conductive pattern.Type: ApplicationFiled: April 20, 2007Publication date: June 12, 2008Inventors: Ing-Ruey Liaw, Thomas Chang
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Publication number: 20080135916Abstract: Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.Type: ApplicationFiled: November 26, 2007Publication date: June 12, 2008Inventors: Won-joo Kim, Yoon-dong Park, June-mo Koo, Suk-pil Kim
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Publication number: 20080135917Abstract: Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventors: Zhong Dong, Chiliang Chen
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Publication number: 20080135918Abstract: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Applicant: SPANSION LLCInventors: Wei Zheng, Chi Chang, Mark Randolph, Satoshi Torii
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Publication number: 20080135919Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easy to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching. Thus, no polysilicon residue will be formed on the sidewall of the dielectric layer.Type: ApplicationFiled: August 19, 2007Publication date: June 12, 2008Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (Shanghai) CORPORATIONInventors: Haitao JIANG, Xinsheng Zhong, Jiangpeng Xue, Gangning Wang
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Publication number: 20080135920Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.Type: ApplicationFiled: October 24, 2007Publication date: June 12, 2008Applicant: Macronix International Co., Ltd.Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
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Publication number: 20080135921Abstract: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n? epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.Type: ApplicationFiled: November 13, 2007Publication date: June 12, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
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Publication number: 20080135922Abstract: A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, and the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than conduction band minimum of the first through third insulating layers while being located in a position higher than conduction band minimum of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second iType: ApplicationFiled: September 13, 2007Publication date: June 12, 2008Inventors: Yuichiro Mitani, Masahiro Koike, Yasushi Nakasaki, Daisuke Matsushita
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Publication number: 20080135923Abstract: A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.Type: ApplicationFiled: February 14, 2008Publication date: June 12, 2008Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byoung-Woo Ye
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Publication number: 20080135924Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
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Publication number: 20080135925Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.Type: ApplicationFiled: February 16, 2005Publication date: June 12, 2008Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi
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Publication number: 20080135926Abstract: A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.Type: ApplicationFiled: November 7, 2007Publication date: June 12, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Syotaro Ono, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20080135927Abstract: An insulated gate semiconductor device, specifically, a trench lateral MOSFET having improved hot carrier resistance can be provided without increasing the number of processes and device pitch and without degrading device breakdown voltages and on-resistance characteristics RonA. A junction depth Xj of a p base region of a TLPM (trench lateral power MOSFET) is made smaller than the depth of a trench, and the trench is formed with a depth Dt of about 1.2 ?m such that the junction does not contact a curved corner part at the bottom of the trench.Type: ApplicationFiled: November 21, 2007Publication date: June 12, 2008Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Masaharu YAMAJI, Naoto FUJISHIMA, Mutsumi KITAMURA
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Publication number: 20080135928Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.Type: ApplicationFiled: October 31, 2007Publication date: June 12, 2008Applicant: STMicroelectronics S.r.I.Inventors: Alessandra Cascio, Giuseppe Curro
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Publication number: 20080135929Abstract: A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate.Type: ApplicationFiled: November 1, 2007Publication date: June 12, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20080135930Abstract: A power semiconductor device includes: a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film; a buried field plate electrode; a control electrode; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided on an upper side of the semiconductor substrate. The semiconductor substrate includes: a first semiconductor; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type; a fourth semiconductor layer; and a fifth semiconductor layer. The buried insulating film is thicker than a gate insulating film. At least one of the second semiconductor layer and the third semiconductor layer has a portion with its sheet dopant concentration varying along depth direction of the semiconductor substrate.Type: ApplicationFiled: November 13, 2007Publication date: June 12, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Wataru Saito
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Publication number: 20080135931Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridlay, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sanl, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20080135932Abstract: A semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner even when the active and passive elements include double sided electrode elements. When the semiconductor substrate is divided into plural field areas, an insulation separation trench that penetrates the semiconductor substrate surrounds each of the field areas, and each of the either of the plural active elements or the plural passive elements. Further, each of the plural elements has a pair of power electrodes for power supply respectively disposed on each of both sides of the semiconductor substrate to serve as the double sided electrode elements.Type: ApplicationFiled: December 4, 2007Publication date: June 12, 2008Applicant: DENSO CORPORATIONInventors: Yoshihiko Ozeki, Kenji Kouno, Tetsuo Fujii
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Publication number: 20080135933Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: ApplicationFiled: January 23, 2008Publication date: June 12, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Volker Dudek, Michael Graf
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Publication number: 20080135934Abstract: A laterally diffused metal oxide semiconductor transistor. The laterally diffused metal oxide semiconductor transistor includes a substrate, a drain formed thereon, a source formed on the substrate, comprising a plurality of individual sub-sources respectively corresponding to various sides of the drain, a plurality of channels formed in the substrate between the sub-sources and the drain, a gate overlying a portion of the sub-sources and the channels, and a drift layer formed in the substrate underneath the drain.Type: ApplicationFiled: April 6, 2007Publication date: June 12, 2008Inventor: Y.S. Liu
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Publication number: 20080135935Abstract: Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process.Type: ApplicationFiled: October 26, 2007Publication date: June 12, 2008Inventors: Young Kyun CHO, Tae Moon ROH, Jong Dae KIM
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Publication number: 20080135936Abstract: The method of manufacturing a semiconductor device includes: forming a gate insulating film on a semiconductor substrate; forming a thin silicon layer on the gate insulating film; and forming a metal film on the thin silicon layer, having a work function at the interface with respect to the gate insulating film of a value within a predetermined range.Type: ApplicationFiled: November 30, 2007Publication date: June 12, 2008Inventor: Kazuaki NAKAJIMA
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Publication number: 20080135937Abstract: A thin film transistor comprising: (a) an insulating layer; (b) a gate electrode; (c) a semiconductor layer; (d) a source electrode; and (e) a drain electrode, wherein the insulating layer, the gate electrode, the semiconductor layer, the source electrode, and the drain electrode are in any sequence as long as the gate electrode and the semiconductor layer both contact the insulating layer, and the source electrode and the drain electrode both contact the semiconductor layer, and wherein at least one of the source electrode, the drain electrode, and the gate electrode comprise coalesced coinage metal containing nanoparticles and a residual amount of one or both of a stabilizer covalently bonded to the coalesced coinage metal containing nanoparticles and a decomposed stabilizer covalently bonded to the coalesced coinage metal containing nanoparticles.Type: ApplicationFiled: December 12, 2007Publication date: June 12, 2008Applicant: XEROX CORPORATIONInventors: Yiliang Wu, Yuning Li, Beng S. Ong
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Publication number: 20080135938Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.Type: ApplicationFiled: January 29, 2008Publication date: June 12, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Perry H. Pelley, Troy L. Cooper, Michael A. Mendicino
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Publication number: 20080135939Abstract: A fabrication method of semiconductor and a structure thereof are disclosed herein. The present invention includes: providing a substrate; disposing a mask on the substrate, wherein the mask has a plurality of patterned openings to expose portions of the substrate; forming a metal layer on the exposed portions of the substrate; forming a surface treatment layer on the metal layer; removing the mask; performing a chip package step; and removing the substrate and the metal layer to form a height difference of semiconductor package with pads. The characteristic of the height difference not only can increase the thickness of the solder materials but also can easily check the soldering status.Type: ApplicationFiled: December 7, 2007Publication date: June 12, 2008Inventors: Chi Chih Lin, Bo Sun, Hung Jen Wang, Jen Feng Tseng
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Publication number: 20080135940Abstract: A semiconductor device includes an NMOS switching element having an N-type drain diffusion region coupled to an input and/or output terminal, and an N-type source diffusion region and a P-type substrate contact diffusion region coupled to a ground line; and an NMOS protection element having an N-type drain diffusion region coupled to the input and/or output terminal, and a gate, an N-type source diffusion region and a P-type substrate contact diffusion region coupled to the ground line, wherein the N-type source diffusion region and the P-type substrate contact diffusion region of the NMOS switching element are arranged adjacent to each other, and the N-type source diffusion region and the P-type substrate contact diffusion region of the NMOS protection element are arranged with a spacing therebetween. If the N and P types are interchanged, the ground line is replaced by a power supply line.Type: ApplicationFiled: September 19, 2006Publication date: June 12, 2008Inventor: Hiroyuki Hashigami
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Publication number: 20080135941Abstract: A trigger device. The device includes: a MOSFET comprising a source, a drain, a gate and a body; a modulating layer under the body; body and modulating layer contacts, the body contact separated from the source, drain and modulating contact by dielectric isolation in the body; the modulating layer contact separated from the source and drain by the dielectric isolation, the source and drain extending from a top surface of the body into the body a first distance, the body contact extending a second distance and the dielectric isolation extending a third distance, the third distance greater than the first or second distances; a first vertical bipolar transistor comprising the source, the body and the modulating layer; and a second vertical bipolar transistor comprising the drain, the body and the modulating layer.Type: ApplicationFiled: January 25, 2008Publication date: June 12, 2008Inventors: Steven H. Voldman, Michael J. Zierak
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Publication number: 20080135942Abstract: An SRAM cell includes a semiconductor substrate; a first transistor formed in a main plane of the semiconductor substrate; a second transistor formed in the main plane of the semiconductor substrate; and a first wiring layer connecting a gate electrode of the first transistor with a diffusion region of the second transistor inside a first hole and formed to be spaced from the main plane of the semiconductor substrate inside the first hole.Type: ApplicationFiled: November 13, 2007Publication date: June 12, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Sumito Minagawa
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Publication number: 20080135943Abstract: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.Type: ApplicationFiled: February 2, 2007Publication date: June 12, 2008Applicant: PROMOS TECHNOLOGIES INC.Inventor: Jung-Wu Chien
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Publication number: 20080135944Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.Type: ApplicationFiled: September 18, 2007Publication date: June 12, 2008Inventors: Reika ICHIHARA, Yoshinori Tsuchiya, Hiroki Tanaka, Masato Koyama
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Publication number: 20080135945Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.Type: ApplicationFiled: January 25, 2008Publication date: June 12, 2008Applicant: Texas Instruments IncorporatedInventor: Jiong-Ping Lu
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Publication number: 20080135946Abstract: An exemplary read only memory cell (200) includes a semiconductor layer (220), a gate stack (230), and a gate electrode (240). The gate stack includes a tunnel film (231), a charge storing layer (232), and a block layer (233) sequentially stacked adjacent to the semiconductor layer. The gate electrode is adjacent to the block layer. The charge storing layer is configured to store charges when data is written to the read only memory cell. The charge storing layer comprises at least two sub-layers having different molecular structures of material such that a plurality of interfacial traps is provided where the at least two sub-layers adjoin each other. A method for manufacturing the read only memory cell is also provided.Type: ApplicationFiled: December 11, 2007Publication date: June 12, 2008Inventor: Shuo-Ting Yan
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Publication number: 20080135947Abstract: An organic inverter and a method of manufacturing the same are provided, which regulates threshold voltages depending on positions when an inverter circuit is manufactured on a substrate using an organic semiconductor. To form a depletion load transistor and an enhancement driver transistor at adjacent positions of the same substrate, the surface of the substrate is selectively treated by positions or selectively applied by self-assembly monolayer treatment. Thus, a D-inverter having a combination of a depletion mode and an enhancement mode is more easily realized than a conventional method using a transistor size effect. Also, the D-inverter can be realized even with the same W/L ratio, thereby increasing integration density. That is, the W/L ratio does not need to be increased to manufacture a depletion load transistor, thereby improving integration density.Type: ApplicationFiled: October 31, 2007Publication date: June 12, 2008Inventors: Jae Bon KOO, Kyung Soo SUH, Seong Hyun KIM
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Publication number: 20080135948Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.Type: ApplicationFiled: February 21, 2008Publication date: June 12, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Haining S. Wang
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Publication number: 20080135949Abstract: A method of forming a stacked silicon-germanium nanowire structure on a support substrate is disclosed. The method includes forming a stacked structure on the support substrate, the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer; forming a fin structure from the stacked structure, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing the fin portion of the fin structure thereby forming the silicon-germanium nanowire being surrounded by a layer of oxide; and removing the layer of oxide to form the silicon-germanium nanowire. A method of forming a gate-all-around transistor comprising forming a stacked silicon-germanium nanowire structure that has been formed on a support substrate is also disclosed. A stacked silicon-germanium nanowire structure and a gate-all-around transistor comprising the stacked silicon-germanium nanowire structure are also disclosed.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Applicant: Agency for Science, Technology and ResearchInventors: Guo Qiang Lo, Lakshmi Kanta Bera, Hoai Son Nguyen, Navab Singh
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Publication number: 20080135950Abstract: Embodiments relater to a semiconductor device and a method of fabricating the same. A source/drain area may be formed by using the spacer having the dual structure of the oxide layer and nitride layer. After etching a part of the oxide layer, the salicide layer may be formed on the gate electrode and the source/drain area, and the spacer may be removed. The contact area may be ensured, so a higher degree of integration may be achieved.Type: ApplicationFiled: September 4, 2007Publication date: June 12, 2008Inventor: Jin-Ha Park
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Publication number: 20080135951Abstract: It is known to provide a reoxidation step in the manufacture of a MOSFET that serves a number of structural purposes in relation to the MOSFET. However, the need to provide materials of high dielectric constant for gate insulator layers of MOSFETs to accommodate a drive for smaller integrated circuits has led to excessive growth of an SiO2 interfacial layer between the gate insulator layer and a substrate. Excessive growth of the SiO2 layer results in an Effective Oxide Thickness that leads to increased leakage current in the MOSFET. Further, the replacement of polysilicon with metals as electrodes precludes oxygen exposure during processing. Consequently, the present invention provides replacing or preceding the reoxidation step with the deposition of an oxygen barrier layer over at least side walls of a gate electrode of the MOSFET, thereby providing a barrier for oxygen diffusion to the dielectric interface and metal gate electrode that prevents EOT increase and preserves metal gate electrode integrity.Type: ApplicationFiled: September 21, 2004Publication date: June 12, 2008Applicant: FREESCALE SEMICONDUCTOR, INCInventor: Vidya Kaushik