Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract: Some embodiments discussed relate to an integrated circuit and methods of making it, comprising a semiconductor substrate and a support layer disposed on the semiconductor substrate, wherein the support layer is doped using a noise-reducing dopant and a gate insulator disposed on the support layer, and a gate stack disposed on the gate insulator.

Abstract: A film with small hysteresis and high voltage resistance is obtained by reducing the carbon content in a gate insulating film on a SiC substrate. Specifically, the carbon content in the gate insulating film is set to 1×1020 atoms/cm3 or less. For this, using a plasma processing apparatus, a silicon oxide film is formed on the SiC substrate and then the formed silicon oxide film is reformed by exposure to radicals containing nitrogen atoms. Thus, the gate insulating film excellent in electrical properties is obtained.

Abstract: A semiconductor device includes low concentration source/drain regions and high concentration source/drain regions each being formed in a semiconductor substrate, a gate insulation film formed on part of the semiconductor substrate located between the low concentration source/drain regions when viewed from the top and a gate electrode formed of metal silicide on the gate insulation film. A gate length of upper part of the gate electrode is larger than a gate length of other part of the gate electrode.

Abstract: A functional block for assembly includes at least one element and a magnetic film attached to the element and having a magnetic remanence (MR/MS) of less than about 0.2, having a coercive field (Hc) of less than about 100 Oersteds (100 Oe) and having a permeability (?) of greater than about two (2). At least one element is selected from the group consisting of a semiconductor device, a passive element, a photonic bandgap element, a luminescent material, a sensor, a micro-electrical mechanical system (MEMS), an energy harvesting device and combinations thereof. An article for assembly includes a substrate and a patterned magnetic film disposed on the substrate and defining at least one receptor site. The patterned magnetic film is magnetized primarily in a longitudinal direction and is characterized by a BH product of greater than about 1 megaGauss Oe.

Abstract: Disclosed herein is an improved memory device wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

Abstract: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.

Abstract: The invention relates to a semiconductor component (100) comprising a semiconductor chip (10) configured as a wafer level package, a magnetic field sensor (11) being integrated into said semiconductor chip.

Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.

Abstract: A semiconductor device has an electrode pad, a capacitor and a substrate. The substrate has a given area on which the electrode pad and the capacitor are arranged. The electrode pad and the capacitor are arranged on the substrate so that each of at least two sides of the capacitor and each of at least two sides of the electrode pad is adjacent to each other at a given interval. The capacitor has a connecting side that connects the two sides of the capacitor and faces to the electrode pad. Outside angles of the capacitor formed by the connecting side and the two sides of the capacitor are more than 90 degrees.

Abstract: An image sensor and fabricating method thereof which reduces a light intensity differential between a pixel center and a pixel edge and prevents crosstalk. The image sensor can include a plurality of convex lens provided within a passivation layer and in vertical alignment with a corresponding photodiode, each convex lens including a color filter; having a predetermined color array, and a plurality of microlens provided over the passivation layer and in vertical alignment with a corresponding color filer.

Abstract: A solid-state imaging device includes the following elements. A photoelectric conversion section is arranged in a semiconductor layer having a first surface through which light enters the photoelectric conversion section. A signal circuit section is arranged in a second surface of the semiconductor layer opposite to the first surface. The signal circuit section processes signal charge obtained by photoelectric conversion by the photoelectric conversion section. A reflective layer is arranged on the second surface of the semiconductor layer opposite to the first surface. The reflective layer reflects light transmitted through the photoelectric conversion section back thereto. The reflective layer is composed of a single tungsten layer or a laminate containing a tungsten layer.

Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.

Abstract: An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.

Abstract: A smart card is formed of a memory having light-sensing cells to sense externally supplied light and generate a detection signal in response to the externally supplied light being sensed by the light-sensing cells, and a reset control circuit generating a reset signal in response to the detection signal, the reset signal operating to reset the smart card.

Abstract: The invention is directed to providing a semiconductor device receiving a blue-violet laser, of which the reliability and yield are enhanced. A device element converting a blue-violet laser into an electric signal is formed on a front surface of a semiconductor substrate. An optically transparent substrate is attached to the front surface of the semiconductor substrate with an adhesive layer being interposed therebetween. The adhesive layer contains transparent silicone. Since the front surface of the device element is covered by the optically transparent substrate, foreign substances are prevented from adhering to the front surface of the device element. Furthermore, the adhesive layer is covered by the optically transparent substrate. This prevents the adhesive layer from being exposed to outside air, thereby preventing the degradation of the adhesive layer 6 due to a blue-violet laser.

Abstract: Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.

Abstract: The semiconductor device includes a first conductive type semiconductor substrate; a Schottky electrode forming a Schottky interface between a surface of the semiconductor substrate and itself; a leakage suppression structure, formed in a surface region of the semiconductor substrate, for suppressing a leakage current by generating a depletion layer when a reverse bias voltage is applied between the Schottky electrode and the semiconductor substrate; and a highly doped layer formed in the surface region of the semiconductor substrate in a region between the surface and the leakage suppression structure, the highly doped layer being the first conductive type, exhibiting a higher impurity concentration than the semiconductor substrate, and forming the Schottky interface between the Schottky electrode and itself.

Abstract: High voltage schottky diodes are provided including a first conductivity type semiconductor substrate and a second conductivity type well region defined by the substrate. A first conductive film is provided on a surface of the substrate including the well. A conductive electrode is provided on at least one side of the first conductive film above the substrate including the well. An insulating film is provided between the conductive electrode and the substrate. A cathode contact region is provided outside the conductive electrode remote from the first conductive film. The cathode contact region is doped with high concentration impurities having a second conductive type.

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region is is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Abstract: A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that electrical current is evenly distributed in the conductor, even at the edge regions of the conductor. This even distribution of rhombic slots ensures that electrical current is evenly distributed at least in the central region, and in most if not all cases, across the entire region of the conductor including the edge regions. Thus, the reverse fill pattern prevents current crowding. By preventing current crowding, more stringent metal distribution targets can be met without creating or exacerbating problems associated with IR drop and EM, and without having to add any extra metal to avoid such problems.

Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

Abstract: A plurality of trenches are provided in a semiconductor layer and integrated by thermal oxidation to form an insulating region having void parts therein. The thickness of the insulating region can be controlled by the depth of the trenches. This makes it possible to form the insulating region having a thickness larger than that formed by using a conventional LOCOS method, without increasing crystal defects and the like. By providing the insulating region, for example, below an electrode pad, a stray capacitance can be reduced. Moreover, the stray capacitance can be further reduced by the void parts inside the insulating region.

Abstract: Semiconductor element having a semiconductor chip and a passive component, as well as a method for its production The invention relates to a semiconductor component (1) having a semiconductor chip (2), and a passive component (3), with the semiconductor component (1) having a coil (6) as the passive component (3). The semiconductor chip (2) and the passive component (3) are embedded in a plastic encapsulation compound (4) with connection elements to external contacts (31).

Abstract: A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.

Abstract: A semiconductor device includes a semiconductor substrate and a capacitor which is disposed on a principal surface of the semiconductor substrate. The capacitor includes a lower electrode film disposed on the principal surface of the semiconductor substrate, a dielectric film disposed on the lower electrode and an upper electrode film disposed on the dielectric film. The semiconductor device further includes an interconnection film which includes a portion disposed on the upper electrode film so as to be electrically coupled to the upper electrode film. Directions of residual stresses of the upper electrode film coincide with directions of residual stresses of the portion of the interconnection film. Each of the upper electrode film and the interconnection film may include at least one of platinum and iridium. Also, there is provided a method of manufacturing the semiconductor device.

Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.

Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Abstract: A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mesa surface may be free of the first passivation layer, and the first passivation layer may include a first material. The second passivation layer may be on the first passivation layer, at least a portion of the mesa surface may be free of the second passivation layer, and the second passivation layer may include a second material different than the first material.

Abstract: Nanolaminate-structure SrO/TiO films are formed on a lower electrode of a capacitor by molecular layer deposition kept in a rate-determined state by a surface reaction. The nanolaminate-structure SrO/TiO films are formed by alternately laminating one or more and 20 or less SrO molecular layers and one or more and 20 or less TiO molecular layers at 150° C. or more and 400° C. or less and at 10 Torr or more and the atmospheric pressure or less. This makes it possible to obtain the nanolaminate-structure SrO/TiO films with a high permittivity and a high coverage and with no occurrence of crystalline foreign substance.

Abstract: Embodiments relate to a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating a MOSFET. According to embodiments, a method of forming a MOSFET may include forming a first gate insulating layer on a semiconductor substrate, nitrifying the first gate insulating layer, forming a second gate insulating layer on the first gate insulating layer, injecting fluorine ions into the second gate insulating layer, and diffusing the fluorine ions into the first gate insulating layer.

Abstract: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12) to be patterned and a rear side (13). The substrate is oxidized in two steps. In a first step the rear side (13) is covered by a layer (4) that inhibits or hampers the oxidation. During a second step of the oxidation the oxidation-hampering layer (4) is no longer present. During both steps an oxide thickness is obtained on the front side (12) that is greater than an oxide thickness obtained on the rear side (13).

Abstract: A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key pattern of polysilicon in an active region of a semiconductor scribe lane.

Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

Abstract: Various embodiments of the present invention relate to systems, devices, and methods for treating a semiconductor substrate, such as a silicon wafer, in order to reduce current leakage therein. A semiconductor substrate is provided a plurality of heating treatments that create a denuded zone adjacent to a surface of the substrate and a core zone below the denuded zone. Oxygen impurities within the denuded zone are removed through an oxygen out-diffusion heat treatment. A plurality of macroscopic bulk micro defects is generated within the core zone through the combination of an agglomeration heat treatment and a macroscopic growth heat treatment. This plurality of macroscopic bulk micro defects inhibits migration of metallic contaminants that are located within the substrate. For exemplary purposes, certain embodiments are described relating to a semiconductor wafer heated in a sequence of three treatments.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; stacking a first device over the support structure; stacking a second device over the first device; connecting the first device and the second device to the lead-finger system; stacking a dummy device over the second device; and exposing a support structure bottom side and a dummy device top side for thermal dissipation.

Abstract: A semiconductor device (100) with a metal bump (203) on each interior contact pad (202) has a metallic leadframe with lead segments (220) with the first surface (220a) in one plane. The second surface (220b) is castellated across the segment width in two planes so that regions of a first segment thickness (240a) alternate with regions of a reduced (about 50%) second segment thickness (240b); the first thickness regions are in the locations corresponding to the chip interior contact pads (half-etched leadframe). The second segment surface faces the chip so that each first thickness region aligns with the corresponding chip bump. The chip bumps are attached to the corresponding second segment surface using reflow metal. Dependent on the orientation of the attached half-etched segment, thermomechanical stress concentrations away shift from the solder joints into the leadframe metal, or shear stress may reduced.

Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with a supported die through electrically conducting bumps or balls. By eliminating the need for a separate diepad and lateral isolation between an edge of the diepad and adjacent non-integral leads or pins, embodiments of packages fabricated by bump on leadframe (BOL) processes in accordance with embodiments of the present invention increase the space available to the die for a given package footprint. Embodiments of the present invention may also permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.

Abstract: A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a thin portion whose thickness is thinner than the thick portion. The length of each wire connection surface was furthermore formed shorter than the mounting surface, by arranging so that the thin portion of each lead dives below the semiconductor chip, securing the length of the mounting surface of each lead, a distance from the side face of the semiconductor chip to the side face of a molded body of the semiconductor device being shortened as much as possible, and the package size is brought close to chip size, with miniaturization of QFN.

Abstract: A lead frame of a through-hole light emitting diode (LED) is used to carry an LED chip, and a lens is used to package the chip and a portion of the lead frame. The lead frame includes at least two leads. One lead is used to carry the chip and each of the leads is extended outward from the lens and has a positioning bump. The positioning bumps partially protrude from the lens, such that when the lead frame is disposed on a circuit board, the lead frame is positioned through the positioning bumps and aligns the lens to guide an optical axis of the through-hole LED, thereby achieving the purposes of convenient assembly, thinness, and a reduced thermal-conducting distance.

Abstract: A low dropout (LDO) regulator device includes an LDO regulator integrated circuit housed in a 4-pin quad flat no-lead (QFN) package where the exposed die paddle is used as the ground terminal. The LDO regulator integrated circuit is formed on a semiconductor substrate. The 4-pin QFN package includes four perimeter lands connected to the input terminal, the output terminal, the enable terminal and the bypass terminal of the LDO regulator integrated circuit. The die paddle is to be electrically connected to a ground potential to allow the ground current of the LDO regulator integrated circuit to flow through the substrate and the die paddle of the 4-pin QFN package.

Abstract: An electronic component is disclosed. In one embodiment, the electronic component includes a frame having a base layer, a first layer, a second layer including palladium placed on the first layer, and a third layer including gold placed on the second layer. A semiconductor chip is positioned on the frame.

Abstract: A connecting tape made of insulating material is adhered between a stage unit 21 and a stage unit 22. The stage units 21 and 22 form united stage units by that. Therefore, edge parts 211 and 221 of the stage units 21 and 22 are bound by the connecting tape 41 and of which movements are restricted. The united stage units 21 and 22 are securely supported by support units 31 and 32 and support units 33 and 34. As a result, number of the support units is reduced and inner lead 12 consumed.

Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. Also, such a package in which the package substrate includes a two-tier substrate, each tier including a plurality of lead fingers having a lead finger bond pitch about twice the die pad pitch, the lead fingers of the first tier and the second tier having a staggered arrangement.

Abstract: Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.

Abstract: The present invention relates to a package device including a first substrate, a plurality of first chips positioned on the first substrate, a second substrate positioned on the first substrate, a second chip positioned on the second substrate, an adhesive layer positioned on the second chip, and a heat spreader positioned above the first substrate, the first chips, the second substrate, and the adhesive layer, wherein the heat spreader has a plurality of openings for cold air to flow into the package device and generate convection with hot air inside the package device in order to cool down the package device.

Abstract: A micromechanical component having at least two caverns is provided, the caverns being delimited by the micromechanical component and a cap, and the caverns having different internal atmospheric pressures. The micromechanical component and cap are hermetically joined to one another at a first specifiable atmospheric pressure, then an access to at least one cavern is produced, and subsequently the access is hermetically closed off at a second specifiable atmospheric pressure.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.