Abstract: A gallium nitride-based semiconductor stacked structure includes a single crystal substrate, a low-temperature buffer layer grown at a low temperature in a region contiguous to the single crystal substrate and a gallium nitride-based semiconductor layer overlying the low-temperature buffer layer. The low-temperature buffer layer possesses therein a single crystal layer formed of a hexagonal AlXGa?N-based Group III nitride material containing gallium predominantly over aluminum, wherein 0.5<??1 and X+?=1. The single crystal layer has crystal defects at a smaller density on a (1.0.?1.0.) crystal face than on a (1.1.?2.0.) crystal face. A method for the production of the gallium nitride-based semiconductor stacked structure includes forming on a single crystal substrate a low-temperature buffer layer grown at a low temperature falling in a range of 250° C. to 500° C.

Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.

Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.

Abstract: A light emitting diode is disclosed that is formed in the Group III nitride material system. The diode includes respective n-type and p-type layers for current injection and light emission. At least one n-type Group III nitride layer in the diode has dopants selected from the group consisting of elements with a larger atomic radius than silicon and elements with a larger covalent radius than silicon, with germanium and tellurium being exemplary.

Abstract: A light emitting device having a vertical topology, which is capable of achieving an enhancement in light emission efficiency and reliability, and a method for manufacturing the same are disclosed. The light emitting device includes a first-conductivity-type semiconductor layer, a light emitting layer arranged over the first-conductivity-type semiconductor layer, and a second-conductivity-type semiconductor layer arranged on the light emitting layer. The second-conductivity-type semiconductor layer includes an etch barrier layer.

Abstract: An array substrate includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region, and a common electrode including first, second, third, fourth and fifth portions, wherein the first and second portions are disposed at both sides of the data line, each of the third and fourth portions is connected to the first and second portions, and the fifth portion is connected to the second portion and is extended into a next pixel region adjacent to the pixel region.

Abstract: An object of the present invention is to provide a high-efficiency white light emitting element having a spectrum in a wide wavelength range. Another object is to provide a white light emitting element in which chromaticity of white color is hard to change over time. Still another object is to provide a white light emitting element in which the shape of an emission spectrum does not tend to depend on current density. A first light emitting element 310 and a second light emitting element 320 are serially laminated over a substrate 300. The first light emitting element 310 has a light emitting layer 312 between a first anode 311 and a first cathode 313, and the second light emitting element 320 has a light emitting layer 322 between a second anode 321 and a second cathode 323.

Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.

Abstract: An LED lamp including an LED and one or more phosphors, wherein for each phosphor, a figure of merit (FOM) defined as the product of (incident LED flux)×(excitation cross-section of the phosphor)×(phosphor material decay time) is less than 0.3. Such an arrangement provides a light emitting device with improved lumen output and color stability over a range of drive currents.

Abstract: Light-emitting devices (e.g., LEDs) and methods associated with such devices are provided. In some embodiments, the device includes a distribution of light-generating portions (including active regions) that are spatially localized and separated (e.g., horizontally or vertically) from one or more patterned light extraction portions. This arrangement can allow light generated by the device to propagate and pass through regions of low absorption (e.g., light-extraction portions) rather than in regions of high absorption (e.g., light-generating portions), which can enhance light emission. In some instances, the devices include one or more series of light extraction portions with features arranged in a first and/or second pattern, which may be formed on one or more interfaces of the device (e.g., an emission surface). Patterns can be defined by a series of features (e.g., holes) having certain characteristics (e.g.

Abstract: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs blue light emitted by the blue LED 1 to emit a fluorescence having a main emission peak in the wavelength range from 550 nm to 600 nm, inclusive, and which contains, as a main component, a compound expressed by the chemical formula: (Sr1-a1-b1-xBaa1Cab1Eux)2SiO4 (0?a1?0.3, 0?b1?0.8 and 0<x<1). The silicate phosphor particles disperse substantially evenly in the resin easily. As a result, excellent white light is obtained.

Abstract: An optical semiconductor device comprising: an internal lead; an optical semiconductor element mounted on the internal lead and electrically connected to the internal lead; a sealing resin for sealing the optical semiconductor element and the internal lead, the sealing resign provided with an attachment hole formed by side surfaces and a bottom surface, the side surfaces each including a convex curved-surface section in an upper portion and a planar-surface section in a lower portion contiguous to the curved-surface section, and the bottom surface being in a lower portion and facing the front surface of a functional region for emitting or receiving light of the optical semiconductor element, and the sealing resin being transparent to outgoing or incoming light; and an external terminal connected to the internal lead and adapted for surface mount.

Abstract: Light Emitting Diodes (LEDs) where the emission region, usually a (Al,In,Ga)N layer, is structured for efficient light extraction, are disclosed. The structuring is designed for light extraction from thin films, such as a photonic crystal acting as a diffraction grating. In addition, the structuring controls the in-plane emission and allows new modes into which light will be emitted. Various electrode designs are proposed, including ZnO structures which are known to lead to both excellent electrical properties, such as good carrier injection, and high transparency. Alternatively, the (Al,In,Ga)N layer can be replaced by structures with other materials compositions, in order to achieve efficient light extraction.

Abstract: An illumination device comprising a connection carrier (1), at least one light-emitting diode (10), an electrically insulating layer (3) and a fixing device (4) is specified. The connection carrier (1) has a first main area (1a) and a second main area (1b) remote from the first main area. The light-emitting diode (10) is fixed on the first main area (1a) of the connection carrier (1). The electrically insulating layer (3) is fitted to the second main area (1b) of the connection carrier (1) and projects laterally beyond the second main area (1b) of the connection carrier (1). The fixing device (4) is suitable for fixing the illumination device to a mounting area (2a) of a carrier (2), wherein the electrically insulating layer (3) is arranged between the second main area (1b) of the connection carrier (1) and the mounting area (2a) of the carrier (2). Furthermore, the fixing device (4) presses the connection carrier (1) against the mounting area (2a).

Abstract: A method is disclosed for obtaining a high-resolution lenticular pattern on the surface of a light emitting diode. The method comprises imprinting a patterned sacrificial layer of etchable material that is positioned on a semiconductor surface that is in turn adjacent a light emitting active region, and thereafter etching the imprinted sacrificial layer and the underlying semiconductor to transfer an imprinted pattern into the semiconductor layer adjacent the light emitting active region.

Abstract: A semiconductor device has a current spreading layer between a semiconductor material and an electrode for connecting the semiconductor material to an electrical power supply. The current spreading layer has two or more sub-layers of a first conductive material with patterned regions of a second conductive material distributed between the sub-layers for spreading an electrical current passing between the electrode and the semiconductor material. The second material has an ohmic resistance lower than the first material.

Abstract: In an element structure of a nitride semiconductor light emitting element, the laminate including a light emitting part having a laminate structure of a first n-type layer 13, a p-type clad layer 15 and an active layer 14 sandwiched between them, and a second n-type layer 16 present at the outer side of the light emitting part and at the p-type clad layer side. When the laminate is to be grown on a substrate 11, the light emitting part has the p-type clad layer 15 placed on the upper side of the second n-type layer 16 is placed on the further upper side of the light emitting part. The second n-type layer 16 is dry-etched to form an exposed surface. An electrode P12 is formed on the surface exposed by dry etching, whereby the electrode P12 becomes a p-side electrode having a low contact resistance, which is used for injecting a hole in the p-type clad layer 15 of the aforementioned light emitting part, even if the electrode P12 is formed in the n-type layer 16.

Abstract: A light emitting chip package having a carrier, at least one light emitting chip and a thermal enhanced cover is provided. The carrier includes a plurality of through holes. The light emitting chip is disposed on the carrier. The light emitting chip has an active surface, a back surface opposite to the active surface and a plurality of bumps disposed on the active surface. The light emitting chip is electrically connected to the carrier through the bumps. The thermal enhanced cover is disposed on the carrier to expose at least one side of the light emitting chip. The thermal enhanced cover includes a cover body and a plurality of protrusions connected thereto. A portion of the cover body is above the back surface of the light emitting chip. The protrusions are respectively inserted through the through holes. Therefore, the thermal dissipation efficiency of the light emitting chip package is improved.

Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.

Abstract: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.

Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.

Abstract: A germanium semiconductor device and a method of manufacturing the same are provided.

Abstract: In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor.

Abstract: In the nitride semiconductor heterojunction field effect transistor of the present invention, the floating gate layer (32), as the third layer, is formed between the control gate electrode (34) and the AlGaN layer (11), and the potential for the electrons in the AlGaN layer (11), which is substantially neighboring the floating gate layer (32), is able to be substantially high, and then the channel is able to be depleted. Hence, no current can be flowed through the channel (no drain current) at the time of no gate voltage, as so-called stable normally-off operation can be obtained.

Abstract: A semiconductor device having a multilayer structure, each layer including: a dummy pattern for ensuring a flatness thereof; a pad area in which a bonding pad is formed; an input-output circuit area in which an input-output circuit is formed, the input-output circuit area being adjacent to the pad area in plan view; and a dummy pattern confined area for forbidding an arrangement of the dummy pattern in every layer included in the semiconductor device, the dummy pattern confined area being provided between the pad area and the input-output circuit area in plan view.

Abstract: The invention relates to a semiconductor element (10) with an integrated circuit (12), which has at least two layers (14, 16, 18), which are electrically conductive in areas, arranged one over the other, and spaced from one another by at least one intermediate layer (24, 26), whereby in a first layer (14), trace sections (28) for providing a first voltage potential and in a second layer (16), trace sections (30) for providing a second voltage potential are provided, and with at least one protection diode (36) electrically connected to a trace section (28) of the first layer (14) and to a trace section (30) of the second layer (16), said diode which is configured to eliminate voltage peaks in a substrate layer (38) arranged beneath the first and second layer (14, 16) and which is arranged at least in part beneath a trace section.

Abstract: A circuitry for differential amplifying, logical inversion, NAND and/or NOR operations is provided, which includes at least one depletion mode transistor having JFET characteristics. A method for determining the properties of an electrochemical circuitry is provided, including at least one semi-finished transistor, by applying a solidified electrolyte to selected sets of electrochemically active transistor elements is also provided.

Abstract: A solid-state imaging device is provided and includes a photoelectric conversion unit and a charge transfer unit including charge transfer electrodes for transferring charges generated in the photoelectric conversion unit. Each of the charge transfer electrodes includes a first electrode of a first layer conductive film and a second electrode of a second layer conductive film, which are alternately arranged. The upper edge of the first electrode is protected by a canopy-shaped upper insulating film to ensure a distance between the first and second electrodes. In addition, the first and second electrodes are insulated from each other by an inter-electrode insulating film of a side wall insulating film formed by CVD so as to cover the side wall of the first electrode.

Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.

Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

Abstract: On a silicon wafer (1) to which carbon is intentionally added, an element separation insulation film (2) is selectively formed. A well (3) is formed in an element active region defined by the element separation insulation film (2). When the element separation insulation film (2) and the well (3) are formed, the silicon wafer (1) is appropriately heated, so that after the well (3) is formed, no precipitated oxygen exists on the well (3) and precipitated oxygen exists at a position deeper than the well (3). A silicon nitride film is formed as a gate insulation film (4) on the well (3). A silicon film is formed on the gate insulation film (4), and these are patterned to form a gate electrode (6).

Abstract: A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.

Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

Abstract: Disclosed is a manufacturing method for forming a FET on a glass substrate at low temperatures. A polycrystalline silicon layer 2 is formed on a glass substrate 1, germanium layers 11, 12 are formed on the polycrystalline silicon layer in regions that are to become a source and a drain, ions serving as a dopant are implanted into at least the germanium layers, and annealing is subsequently applied to thereby cause the implanted dopant to diffuse into the polycrystalline. silicon layer, form a source region S and a drain region D and crystallize the germanium layers. Alternatively, the dopant is implanted also into the polycrystalline silicon layer at such a dosage that will not cause the polycrystalline silicon layer to become amorphous. Annealing for crystallizing the germanium is subsequently carried out. Annealing may be performed in the neighborhood of 500° C.

Abstract: A transistor device is formed on a flexible substrate such that device processing remains at a low temperature. A first gate dielectric layer is formed over gate metal by annodization, eliminating relatively high-temperature dielectric deposition processes and difficulties with in-process substrate deformation. A second gate dielectric layer may optionally be provided over the first in order to provide an improved dielectric/semiconductor interface. A high performance pixel, and process for producing same, may thus be provided on a flexible substrate.

Abstract: This invention relates to field effect transistors having carbon nanotube contacts and to a method of making these field effect transistors. The field effect transistors have better contacts as the source and drains as well as the bridge are made of carbon nanotubes. The fabrication of the proposed embodiment becomes possible by using a fabrication process which involves exposing the structure to two different temperatures.

Abstract: A thin film transistor includes a substrate, a semiconductor layer on the substrate, a thermal oxide layer on the semiconductor layer, a gate electrode on the thermal oxide layer, the gate electrode positioned to correspond to a channel region of the semiconductor layer, an interlayer insulating layer on the substrate, and source and drain electrodes electrically connected to the semiconductor layer.

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract: A method and apparatus to operate a pixel circuit within an active pixel image sensor in a common gate amplifier mode.

Abstract: A method, apparatus, and system that provides one or more charge collecting protection regions in a pixel array, each formed below a storage region of a pixel cell, but not below at least one photosensor of one pixel of the array. The storage region includes a floating diffusion region and/or a storage gate in the pixel cell of the imaging device. The protection regions can keep stray charges from reaching the storage regions.

Abstract: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality of photo diode regions and a shielding layer formed overlying the interlayer dielectric layer. A silicon dioxide bearing material is overlying the shielding layer. A plurality of lens structures are formed on the silicon dioxide bearing material. The sensor also has a color filter layer overlying the lens structures and a plurality of second lens structures overlying the color filter layer according to a preferred embodiment.

Abstract: A photodiode comprises a support substrate, an insulating layer formed over the support substrate, a silicon semiconductor layer formed over the insulating layer and having a device forming area and device isolation areas which surround the device forming area, a device isolation layer formed in the device isolation areas, a P+ diffusion layer formed in the device forming area close to one edge lying inside the device isolation layer by diffusing a P-type impurity in a high concentration, an N+ diffusion layer spaced away from the P+ diffusion layer and formed in the device forming area close to the other edge opposite to the one edge of the device isolation layer by diffusing an N-type impurity in a high concentration, a low concentration diffusion layer formed in the device forming area located between the P+ diffusion layer and the N+ diffusion layer by diffusing an impurity of the same type as either one of the P+ diffusion layer and the N+ diffusion layer in a low concentration, and silicide layers respe

Abstract: An image sensor may comprise photodiodes on a semiconductor; color filters on the photodiodes; a planarization layer covering the color filters; and microlenses on the planarization layer, including alternate hydrophilic microlenses and hydrophobic microlenses contacting the edges of the hydrophilic microlenses, corresponding to respective color filters.

Abstract: A method of forming an organic ferroelectric film configured to include an organic ferroelectric material with a crystalline property as a principal material includes (a) forming a low crystallinity film having a crystallinity lower than a crystallinity of the organic ferroelectric film on one surface of a substrate, and (b) forming the organic ferroelectric film from the low crystallinity film. The step (a) includes applying a liquid material containing the organic ferroelectric material on the one surface of the substrate and then drying the liquid material, and the step (b) includes heating and pressurizing the low crystallinity film to enhancing the crystallinity in the low crystallinity film while fairing the low crystallinity film.

Abstract: A semiconductor memory, comprising: a first memory cell transistor disposed on a semiconductor substrate; a second memory cell transistor disposed on the semiconductor substrate and having a first source-drain region in common with the first memory cell transistor; a first ferroelectric capacitor disposed with a via in between above a second source-drain region of the first memory cell transistor; a second ferroelectric capacitor disposed with a via in between above a second source-drain region of the second memory cell transistor; an interlayer dielectric disposed on the semiconductor substrate, as coating the memory cell transistors and the ferroelectric capacitors, the interlayer dielectric having a contact hole through which the first source-drain region is partially exposed at the bottom and upper electrodes of the first and second ferroelectric capacitors are partially exposed at the top; and a wiring layer filled into the contact hole, which connects the first source-drain region, the upper electrode o