Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

Abstract: A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode.

Abstract: A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.

Abstract: A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Abstract: A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generates an output upon discrimination that said memory device is satisfying conditions for performing test, and when an output of the entry circuit is generated and a memory arrangement of the memory device is in a write enable state, a gate circuit generates an output to activate a buffer circuit, by which the internal signal is written to the memory arrangement by being connected to a data write input of the memory arrangement via the buffer circuit, then reading the written data to the outside from the memory arrangement, and performing the measurement related to the internal signal by detecting data change points.

Abstract: A semiconductor memory device includes a sense amplifier SA, a pair of bit lines BLT, BLB, a transfer switch SW provided between the sense amplifier SA and the pair of bit lines BLT, BLB, a precharge circuit PC that precharges the sense amplifier SA and the pair of bit lines BLT, BLB at the same potential, and a control circuit CTL. The control circuit CTL sets the transfer switch SW in the off state in the state before data is written or read, and turns on the transfer switch SW when writing or reading data via the pair of bit lines BLT, BLB. With this arrangement, a defective current flowing to the sense amplifier SA can be decreased, even when a word line WL and a bit line BL are shortcircuited.

Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

Abstract: Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

Abstract: A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.

Abstract: Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract: A semiconductor memory device performs a refresh operation sequentially for a word line selected based on a row address when receiving a refresh request, and comprises: a memory cell array divided into M banks; a refresh counter for sequentially outputting a count value corresponding to the word line to be refreshed in response to the refresh request; and a row address converter for supplying row addresses different from one anther in at lest two banks among the M banks by converting the count value. In the semiconductor memory device, a predetermined number of selected word lines are refreshed at the same time in the banks in accordance with different patterns from one another, and the maximum value of the total number of the selected word lines refreshed at the same time for all the M banks is controlled to be lower than 2M.

Abstract: Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed.

Abstract: A semiconductor memory device includes a memory cell which includes first and second inverter circuits. Each of the first and second inverter circuits includes a load transistor which includes a source connected to a first power supply terminal, and a driving transistor which includes a drain connected to a drain of the load transistor via a memory node, a gate connected to a gate of the load transistor, a source connected to a second power supply terminal, and a back gate connected to a third power supply terminal. A first power supply voltage is applied to the first power supply terminal. A ground voltage is applied to the second power supply terminal. A source voltage higher than the ground voltage is applied to the third power supply terminal.

Abstract: In a semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, a word driver circuit that drives the word line has a drive PMOS transistor and drive NMOS transistor which are connected in series between a first node and a second node and each of which has a gate connected to a third node, the word line being connected to a connection node of the two transistors. A first voltage or a second voltage lower than the first voltage is then applied to the third node, and the first voltage or second voltage is applied to the first node. In addition, between the third node and the gate of the drive PMOS transistor, there is provided a leakage prevention NMOS transistor having a gate applied with the first voltage or a voltage in the vicinity thereof.

Abstract: A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Abstract: An integrated circuit includes a circuit output, a data input that receives a data signal, and a clock input that receives a clock signal. The integrated circuit further includes first and second logic gates. The first logic gate has a first input coupled to the clock input, a second input coupled to the data input, and an output and a second logic gate. The second logic gate has a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output. Setup time of the data signal relative to the clock signal at the second logic gate is improved by reciprocal gating of the data and clock signals.

Abstract: A word line selecting circuit of a semiconductor memory apparatus having at least two memory areas and a plurality of word lines formed across the two memory areas is provided. The circuit includes: a decoder configured to decode an input address and configured to decode a word line corresponding to the decoded input address from the plurality of word lines; and an address counter configured to count the decoded input address such that the word lines in the memory areas are alternately selected according to a refresh signal.

Abstract: One embodiment provides a memory device including a memory bank, a first receiver, and a second receiver. The memory bank includes memory cells. The first receiver is configured to receive a clock signal and provide a data clock signal based on the clock signal. The second receiver is configured to receive the clock signal and provide a command/address clock signal based on the clock signal. The first receiver provides the data clock signal to output read data from the memory cells. The second receiver provides the command/address clock signal to execute commands.

Abstract: One embodiment provides a memory including a first receiver, a second receiver, a circuit, a first buffer, and a second buffer. The first receiver is situated on one side of the memory and configured to receive a first clock signal and provide a first clock tree signal. The second receiver is situated on another side of the memory and configured to receive a second clock signal and provide a second clock tree signal. The circuit is configured to receive the first clock tree signal and provide a distributed clock signal. The first buffer is configured to selectively provide one of the first clock tree signal and the distributed clock signal to the one side of the memory and the second buffer is configured to selectively provide one of the second clock tree signal and the distributed clock signal to the other side of the memory.

Abstract: One embodiment provides a memory device including a first receiver and a second receiver. The first receiver is configured to receive a single ended clock signal and provide a first clock signal based on the single ended clock signal to provide a memory function. The second receiver is configured to receive a differential clock signal and provide a second clock signal based on the differential clock signal to provide the memory function. Only one of the first receiver and the second receiver is selected to provide the memory function.

Abstract: A method for forming and imploding cavities within a cavitation chamber is provided. The method uses a cavitation piston, coupled to a hydraulically actuated piston, to form the desired cavities during piston retraction and then implode the cavities during piston extension. The cavitation fluid is degassed prior to hydraulically driving cavitation within the chamber. Degassing can be performed within the cavitation chamber or within a separate degassing chamber. In one aspect, a coupling sleeve is interposed between the hydraulic driver and the cavitation chamber. Preferably the coupling sleeve is evacuated. In another aspect, a cavitation fluid circulatory system is coupled to the cavitation chamber. In-line valves on the chamber inlets allow the chamber to be isolated, when desired, from the circulatory system.

Abstract: The disclosure provides a method which includes transmitting signals over a time period between a downhole location and a surface location during drilling of a wellbore; recording the time of each signal at the surface using a surface clock and the time of each signal downhole using a downhole clock; and correcting the downhole measurements using the recorded times.

Abstract: Disclosed is a system for detecting seismic events, the system including a plurality of seismic receivers, at least one of the receivers in the plurality adapted for: monitoring seismic activity, providing an alert to at least another of the receivers in the plurality upon detection of a seismic event, and triggering the monitoring in the at least another of the receivers in the plurality. A method and computer program product for monitoring seismic events is also disclosed.

Abstract: A method and system of operating single vibrator source points for seismic data acquisition includes acquiring real-time field survey locations for a first plurality of seismic vibrators, determining at least one geometrical relationship between each of the first plurality of seismic vibrators as a function of the field survey locations, selecting a second plurality of seismic vibrators from the first plurality of vibrators as a function of the at least one geometrical relationship, selecting source parameter data for the second plurality of seismic vibrators as a function of the field survey locations and driving the second plurality of seismic vibrators to propagate seismic energy into the earth. A third plurality of vibrators is selected based on geometrical relationships and associated source parameters are determined based on vibrator locations. Multiple vibrator groups may acquire data continuously without interruption.

Abstract: Originating from a novel and an exact algebraic formula for the impulse response of a plane acoustic reflector at zero offset due to a point acoustic source the present invention provides a method for computing an exact impulse response of a plane acoustic reflector at zero offset due to a point acoustic source; and originating from the method, methods for testing and validating algorithms for numerical modeling of seismic reflection, seismic migration and seismic inversion; a method for testing the efficacy of ray-theoretical solution for a given source-reflector configuration; another method for computing zero-offset reflection response of a circular reflector at its central axis; yet another method for validating an interpretation of a reflector as a planar structure; still yet another method for estimating the seismic source-time function when the zero-offset reflection response of a plane reflector is given.

Abstract: Three data subsets are obtained in three selected azimuthal directions from seismic data in heterogeneous, anisotropic media. Azimuthal velocities are determined for each of the data subsets. A linear system of equations in the three selected azimuthal directions and the three determined azimuthal velocities is solved for three independent parameters. An azimuthal time migration velocity function is constructed from the three solved independent parameters. A time migration traveltime function is constructed from the constructed azimuthal time migration velocity function.

Abstract: A method for interpreting seismic data includes displaying seismic data on a graphic digitizing tablet. At least one data point is entered into a seismic data interpretation program by contacting a write end of a digitizing stylus to the digitizing tablet at a user-selected position within the displayed seismic data.

Abstract: A method is provided for building a subsurface velocity model from a plurality of bins of marine acquired seismic traces of the subsurface.

Abstract: One embodiment includes a method comprising receiving an acoustic signal that is propagated along a drill string. The method also includes correlating the acoustic signal to a first stored acoustic signal representing a first symbol, wherein the first stored acoustic signal is acquired from a propagation along the drill string in an approximately noise free environment.

Abstract: The present invention relates to a digital beamformer in ultrasound imaging after the process of receiving a digital echo signal. Provided herein is a time multiplexed device and method for beamforming. The device includes an echo data write/read unit, a multi-beam processing unit, a channel data summing unit, and a parameter distributing and synchronizing unit for distributing and synchronizing respective receive parameters to the echo data write/read unit and the multi-beam processing unit through a parameter load bus for each of the beams in the channel.

Abstract: The present invention relates to a sonar method and apparatus of tracking objects underwater. Specifically, the method and apparatus can be used to acoustically track a multitude of objects in a hemispherical volume 360° azimuth and 180° elevation relative to the location of the apparatus. The method and apparatus of the present invention provide four-dimensional, real-time tracking of underwater objects.

Abstract: A seismic sensor includes a housing having a device for releasably affixing the housing to the Earth. A seismic sensing element is disposed within the housing. A wireless signal communication device is associated with the housing and is in signal communication with the seismic sensing element. The communication device is in signal communication with a seismic data recording unit.

Abstract: A marine seismic exploration method and system comprised of continuous recording, self-contained ocean bottom pods characterized by low profile casings. An external bumper is provided to promote ocean bottom coupling and prevent fishing net entrapment. Pods are tethered together with flexible, non-rigid, non-conducting cable used to control pod deployment. Pods are deployed and retrieved from a boat deck configured to have a storage system and a handling system to attach pods to cable on-the-fly. The storage system is a juke box configuration of slots wherein individual pods are randomly stored in the slots to permit data extraction, charging, testing and synchronizing without opening the pods. A pod may include an inertial navigation system to determine ocean floor location and a rubidium clock for timing. The system includes mathematical gimballing. The cable may include shear couplings designed to automatically shear apart if a certain level of cable tension is reached.

Abstract: A diet watch includes a housing with an adjustable wristband attached thereto, at least one accelerometer disposed within the housing, a microcontroller disposed within the housing and operatively coupled to the accelerometer and a feedback device operatively coupled to the microcontroller. The accelerometer provides a signal indicative of an orientation of a user's hand in space. The microcontroller uses the signal from the at least one accelerometer to determine that a bite was taken by the user and starting a timer to countdown a preset time interval. The feedback device provides an indication to the user that another bite of food may be taken after the preset time interval has elapsed.

Abstract: The inventive mechanism comprises a series of toothed wheels meshing each with other or by groups and driven by a mobile which is connected to a basic timepiece movement by means of a mobile, wherein each toothed wheel is superimposed by a plate or disc carrying figures or signs and rotating in a corresponding bore of the timepiece dial.

Abstract: An audio system that allows audio to be stored and/or moved between components of the audio system by means of digital plug-in cards.

Abstract: A storage apparatus includes a plurality of carriages that are arranged in a matrix and store and transport objects. The plurality of carriages includes a first carriage that stores and transports the object, a second carriage that stores and transports the object, a third carriage that stores and transports the object, and a shifting unit that shifts the third carriage to a position different from matrix positions of the first and the second carriages, and shifts the second carriage to a position of the third carriage when the first carriage shifts to a position of the second carriage.

Abstract: Disclosed is an optical disc having angular information and a wobble track. A wobble signal generated according to the wobble track includes a phase corresponding to an angle of the optical disc. A detecting system for detecting the angular information of the optical disc is also disclosed, which includes a wobble signal detecting apparatus, a reference clock signal generating apparatus, and a phase comparator. The wobble signal detecting apparatus is used for detecting the wobble track on the optical disc to generate a wobble signal. The reference clock signal generating apparatus is used for generating a reference clock signal according to the wobble signal. The phase comparator is used for comparing the wobble signal and the reference clock signal to obtain the angular information of the optical disc. Alternatively, the wobble signal detecting apparatus can be used for detecting the wobble signal on the optical disc.

Abstract: An optical disk drive with a defocus-prohibited device comprising: a frame; a cover disposed on the frame; a disk-rotating device disposed at an end of the frame; two guiding rods disposed at sides of the frame respectively and elongated from the end with the disk-rotating device to another end of the frame; a pick-up head capable of moving back and forth on the two guiding rods, and reading an optical disk driven by the disk-rotating device; and at least one flexible member being disposed between the pick-up head and the cover for providing a force on the pick-up head in advance.

Abstract: An optical disc apparatus has a bottom cover member provided with an opening. A peripheral part of a unit mechanism deck member serving as a support member in a functional unit mechanism or a motor base holding a spindle motor and fixed to the unit mechanism deck member is projected outside through the opening when the optical disc apparatus is set in a loaded state to space a part of the functional unit mechanism projecting in a direction opposite to a direction in which the peripheral part of the unit mechanism deck member or the motor base is projected outside from a surface of the optical disc.

Abstract: An optical recording medium driving apparatus supporting an optical recording medium having multiple recording layers includes head means including a focusing mechanism and a spherical aberration correction mechanism; focusing control means for driving the focusing mechanism on the basis of a reflected light to perform focusing control on each recording layer; spherical aberration correcting means for driving the spherical aberration correction mechanism on the basis of a spherical aberration correction value to correct spherical aberration; and control means for controlling the focusing control means so as to set the spherical aberration correction value given by shifting the spherical aberration correction value appropriate for the midpoint between a target layer and a first recording layer by a desired value in the spherical aberration correcting means and controlling the focusing control means so as to perform the focusing control with the spherical aberration correction value after the shift being set.

Abstract: The present invention relates to a holographic recording medium, adapted to store additional information for the recorded holograms, and to a holographic pickup for a holographic storage system for use with the holographic recording medium. According to the invention, the holographic recording medium has a holographic layer for storing holograms and a servo layer for positioning a light beam for reading and/or recording of a hologram relative to the holographic recording medium, wherein the servo layer is recordable or rewritable. A holographic pickup for use with such a holographic recording medium includes a light source for recording additional data in the servo layer of the holographic recording medium.

Abstract: [Problem to be Solved] It has been a problem that, with focusing servo control based on a focus error signal according to a conventional astigmatism method, due to a positional deviation of a received light beam on the light-receiving plane of a photodetector or an offset caused by asymmetry in the intensity distribution of reflected light, an error occurs in the focus error signal, whereby the focusing servo cannot correctly be performed.

Abstract: An optical-disk device includes a record unit recording data onto an optical disk, and a management-information-record unit configured to additionally write the latest disk-management information about the optical disk in management-information-record areas provided on the optical disk. When a first area of the management-information-record areas is short of a vacant area used to additionally write the disk-management information, the management-information-record unit records padding data in an unrecorded area of the first area, and additionally writes the disk-management information in a second area of the management-information-record areas, and wherein when the first area includes an unrecordable area where the disk-management information can be additionally written with difficulty, the management-information-record unit stops additionally writing the disk-management information in the first area, and additionally writes the disk-management information in the second area.

Abstract: When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The sizes of the primary and supplementary spare areas are determined by the number of defects generated upon initialization. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded, so that the spare areas can be efficiently managed. Also, in the defect management method, when an area that has already been linearly replaced is allocated as a supplementary spare area, defective blocks within the allocated supplementary spare area are not used for linear replacement, and the entries of a secondary defect list (SDL) with respect to the defective blocks are not changed.

Abstract: This optical disc drive has an optical pickup head that emits a light beam to an optical storage medium, detects the light beam reflected from the optical storage medium, and outputs a signal based on the received reflected light; a jitter measuring unit for measuring jitter in signals output from the optical pickup head; and an evaluation unit for determining from the measured jitter if the optical storage medium is good or defective. The jitter measuring unit measures jitter in a train of 3T or longer marks or spaces from an optical storage medium to which digital information is recorded as a train of marks or spaces of length kT based on a period T and an integer k of two or more.

Abstract: An optical disk apparatus carries out focusing operation at a position shifted by a very small distance from the surface of a disk or from the recording surface of the disk in such a condition that the disk is stopped or is rotating at a speed sufficiently lower than a normal operational speed for the first focusing operation, after that, the disk is rotated at the normal rotational speed and a focus deviation amount is stored, and then focusing operation on an information recording surface is performed while applying the stored focus deviation component to a focus moving means.

Abstract: According to one embodiment, a disk drive having a head-motion control system. The disk drive comprises a defect evading unit. The defect evading unit includes a defect-approach determining unit and an evasion-orbit defining unit. The defect-approach determining unit determines a position near a defective part, which the head is approaching, on the basis of defect position information. The evasion-orbit defining unit changes the motion orbit of the head on the basis of the position determined by the defect-approach determining unit, thereby making the head evade the defective part.

Abstract: When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The sizes of the primary and supplementary spare areas are determined by the number of defects generated upon initialization. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded, so that the spare areas can be efficiently managed. Also, in the defect management method, when an area that has already been linearly replaced is allocated as a supplementary spare area, defective blocks within the allocated supplementary spare area are not used for linear replacement, and the entries of a secondary defect list (SDL) with respect to the defective blocks are not changed.