Abstract: A capacitor includes a lower electrode, a dielectric layer, an upper electrode, and a ruthenium oxide layer. At least one of the lower electrode and the upper electrode is formed of a ruthenium layer, and the ruthenium oxide layer is disposed next to the ruthenium layer.

Abstract: Disclosed is a method of manufacturing a semiconductor device formed by laminating a capacitor including a bottom metal electrode, a capacitive insulating film, and an upper metal electrode. When the capacitive insulating film is formed by performing a first step of forming a first dielectric layer on the bottom metal electrode by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric; and a second step of forming a second dielectric layer on the first dielectric layer by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric, a film forming temperature in the first step is set so as to be lower than a film forming temperature in the second step.

Abstract: According to one embodiment, a collector electrode including metal is used for a sink region for connecting an n+ type buried layer, so that the sink region can be narrowly formed. Further, an interval between a base region and the collector electrode can be reduced, thereby considerably decreasing the size of the transistor. Furthermore, collector resistance is reduced, so that the performance of the transistor can be improved.

Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

Abstract: A method of making a nitride semiconductor substrate having the steps of providing a free-standing substrate that is of a nitride semiconductor and has one of a penetrating pit and a penetrating crack that penetrate from a top surface to a back surface of the free-standing substrate, attaching a metal to the penetrating pit or the penetrating crack, the metal being adapted to be nitrided, and nitriding the metal to form a nitride that seals the penetrating pit or the penetrating crack. A nitride semiconductor substrate has a free-standing substrate that is formed of a nitride semiconductor and has one of a penetrating pit and a penetrating crack that penetrate from a top surface to a back surface of the free-standing substrate, and a metal nitride that seals the penetrating pit or the penetrating crack. The metal nitride is formed of GaN, InN and AlN.

Abstract: A template 100 for three-dimensional thin-film solar cell substrate formation for use in three-dimensional thin-film solar cells. The template 100 comprises a substrate which comprises a plurality of posts 102 and a plurality of trenches 104 between said plurality of posts 102. The template 100 forms an environment for three-dimensional thin-film solar cell substrate formation.

Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.

Abstract: A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.

Abstract: An indicator that denotes the cleavage direction is arranged along with an integrated circuit of a semiconductor chip. This indicator makes it possible to cut the semiconductor chip along the cleavage direction even if the integrated circuit is arranged not to be in the cleavage direction.

Abstract: A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.

Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.

Abstract: A method of processing a semiconductor structure is provided. The method includes forming a polish stop layer over one or more features on a substrate; forming a first dielectric layer over the polish stop layer, a valley portion of the first dielectric layer being just above a top of the polish stop layer; and polishing the dielectric layer down to the top of the polish stop layer. By forming a just enough dielectric layer to allow gap-fill on the substrate and polishing the dielectric layer down to the top of the polish stop layer, the method can reduce the cost and controls associated with forming the first dielectric layer.

Abstract: A method for fabricating a semiconductor device having a non-salicide region is provided. In one embodiment, the method includes forming a non-salicide buffer oxide layer on a substrate having an isolation layer formed therein, forming a first photoresist pattern on the non-salicide buffer oxide layer to define a first region, implanting silicon ions into the first region, removing the first photoresist pattern, forming a silicon oxide layer on the first region by performing a thermal oxidization process, forming a second photoresist pattern on the silicon oxide layer, forming a non-salicide region on an upper side of the substrate, on which the silicon oxide layer has been formed, by performing a wet etch process using the second photoresist pattern as a mask, and removing the second photoresist pattern.

Abstract: One or more passivation layers are added to the end of a semiconductor process flow to provide additional protection for devices (e.g., transistors) formed during the process. An additional layer is then formed and/or an anneal is performed to mitigate threshold voltage shifting that may be induced by the passivation layers. Mitigation of threshold voltage shifting increases the life expectancy of devices (e.g., transistors) formed during the process, which in turn mitigates yield loss by facilitating predictable or otherwise desirable behavior of the devices (e.g., transistors).

Abstract: A method for manufacturing a semiconductor device featuring a high-stress dielectric layer is disclosed. The method involves the deposition of a comparatively thick liner layer that exerts increased strain on an underlying gate and active areas, resulting in enhanced carrier mobility through the transistor and heightened transistor performance. The method also involves the amelioration of fabrication problems that might arise from the deposition of a comparatively thick liner layer by forming such layer with at least a partially direction deposition process. Also disclosed are semiconductor devices manufactured in accordance with the disclosed methods.

Abstract: A semiconductor device including a first insulating layer having a hydroxyl radical formed over a semiconductor substrate; a line layer having a plurality of line patterns formed over the first insulating layer, the plurality if line patterns being arranged such that a spatial gap is provided therebetween; a fluorine-doped second insulating layer formed in the spatial gap between respective line patterns; and a multilayered diffusion prevention layer including a first oxide layer for suppressing an increase of a dielectric constant between the plurality of line patterns and a second oxide layer for preventing the diffusion of fluorine from the fluorine-doped second insulating layer into the first insulating layer.

Abstract: A package may comprise a substrate provided with noise absorbing material. The noise absorbing material may absorb noise from a signal path in the substrate to prevent the noise from reaching other signals or signal paths.

Abstract: Methods and apparatus for multichip modules having improved shielding and isolation properties.

Abstract: A package includes: a package body including a substrate, an electronic component mounted on a first surface of the substrate, and a sealing resin layer for sealing the electronic component; and a shield case for covering the sealing resin layer, the shield case being made of metal and having an inverted U-shape in a cross-sectional view, wherein a bent part of the shield case is formed in such a manner that at least a part of an end of the shield case is bent toward a second surface of the substrate opposite to the first surface, and the bent part abuts on the second surface so that the shield case is attached to the substrate.

Abstract: Leadframes resistant to stress and semiconductor devices incorporating such leadframes are described, including but not limited to QFN packages and the like. According to preferred embodiments disclosed herein, a stress-resistant leadframe for a semiconductor device includes a paddle for receiving a semiconductor chip. The paddle is supported with tie bars extending between the paddle and leadframe edge. One or more flexion bar included within the span of at least one of the tie bars is configured to alleviate mechanical stresses potentially encountered by the leadframe.

Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.

Abstract: Packaged microelectronic semiconductor devices and methods for their assembly are described. According to preferred embodiments of the invention, chip-on-lead techniques are adapted to provide chip-on-lead packages using cantilevered leads. Exemplary embodiments of the invention include methods using a temporary brace to support the cantilevered leads during chip mounting. Versatile chip package embodiments are disclosed including those in which the chip mounting pad is smaller than the chip(s) mounted thereupon, and further examples wherein the chip mounting pad is dispensed with and a chip is mounted on the cantilevered leads alone.

Abstract: Methods for assembling thermally enhanced semiconductor device packages are disclosed in which a chip assembly has a chip affixed to a leadframe. A thermal pad is affixed to a surface of the chip, and the chip assembly is encapsulated whereby a surface of the thermal pad remains exposed to form at least a portion of a surface of the package favorable for the egress of heat from the chip. Also disclosed are thermally enhanced semiconductor device packages made using the methods of the invention.

Abstract: A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.

Abstract: A method, apparatus, and system relating to an IC package. The method includes providing a leadframe including a die pad for receiving a die and a plurality interconnect pillars, attaching a die to the die pad, bonding the die to the leadframe, and encapsulating the die and the leadframe to form a first IC package having a top surface and an opposing bottom surface, where the interconnect pillars extend from the top surface of the first IC package to the bottom surface of the first IC package.

Abstract: The present invention discloses a super thin chip scale package structure and method of the same. The super thin chip scale package structure comprises a substrate, a wafer with a plurality of die having a plurality of bonding pads, a first dielectric layer, a via conductive layer, a second dielectric layer, a redistribution layer trace and soldering bumps formed on the wafer in sequence. Due to minimizing the sizes of the package structure, the present invention can provides a super thin chip scale package structure. Especially, the method for manufacturing the super thin chip scale package comprises sawing the wafer and back-lapping the back side of the wafer and etching the back side of the substrate to provide the super thin chip scale package structure. Accordingly, the present invention can minimize the size of the package structure, and improve the manufacturing process effectively.

Abstract: A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, a back surface and bonding pads disposed on the active surface. The lead frame includes a die pad, an insulating layer, transfer bonding pads and inner leads. The back surface of the chip is fixed on the die pad. The insulating layer is disposed on the die pad outside the chip. The transfer bonding pads are disposed on the insulating layer. The first bonding wires are respectively connected to the bonding pads and the transfer bonding pads. The second bonding wires are respectively connected to the transfer bonding pads and the inner leads. The chip package structure has smaller volume and a higher yield rate.

Abstract: A chip package structure including a circuit board, a solder mask, and a chip package is provided. The circuit board has at least one contact on its surface. The solder mask covers the circuit board and has at least one first opening for exposing the contact. The chip package is disposed on the circuit board, and includes a chip and a leadframe, which has at least one lead that is electrically connected to the chip. The lead has an insertion portion that corresponds to the contact and inserts into the first opening. A solder bump is filled into the first opening and fastened to the insertion portion, thereby the connection between the lead and the contact of the chip package structure is secured.

Abstract: A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.

Abstract: A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires connected with the leads. By means of the above-described lead frame, the subsequent packaging process of the semiconductor chip; including dual chips and/or multi-chips assembly, is simplified and the effect of the manufacturing process is improved, at the same time, the manufacturing cost is reduced.

Abstract: The present invention provides a multi-die semiconductor package structure and a manufacturing method thereof, which includes providing at least two dies and a lead frame including a die pad and a lead wire located at the periphery of the die pad, the die pad has a via hole at the edge thereof, binding a base opposite side of a first die to the die pad; electrically connecting the first die to the lead wire through the via hole; binding a base side of a second die to the die pad, the first and second dies are disposed on the opposite sides of the die pad respectively; electrically connecting the second die to the lead wire; stacking other dies above the first or second die and electrically connecting them to the lead wire; and encapsulating said at least two dies and the lead frame to form a package.

Abstract: A lead frame includes a lead frame main body having a plurality of die pad portions each having a chip mounting surface on which a semiconductor chip is mounted, a plurality of lead portions provided to surround the plurality of die pad portions respectively, and a frame portion for supporting the plurality of die pad portions and the plurality of lead portions, an adhesive film pasted on a lower surface of the lead frame main body by pressing, and a first metal film provided on surfaces of the plurality of lead portions and connected electrically to the semiconductor chip respectively, wherein second metal films whose thickness is substantially equal to a thickness of the first metal film are provided to the chip mounting surface of the plurality of die pad portions respectively.

Abstract: A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first metal layer, and a multiple conductive layer comprising another first metal layer and a second metal layer disposed on the another first metal layer. A plurality of wires are attached to an upper surface of the single conductive layer and/or an upper surface of the second metal layer of the multiple conductive layer. Contact pads on a power control semiconductor chip and a low power semiconductor chip driving the power control semiconductor chip are electrically connected to the wires.

Abstract: A semiconductor package including a leadframe which has one or more anchor pads formed on and/or defined by the die pad thereof. Such anchor pad(s) may be provided in any one of a multiplicity of different pad shapes, and are adapted to satisfy the required mechanical anchoring and thermal dissipation thresholds for the package, while still enabling high density circuit routing on the printed circuit board under the package. The leadframe of the semiconductor package further includes a plurality of leads which are segregated into at least two sets, with the leads of each set extending along and in spaced relation to respective ones of the peripheral edge segments defined by the die pad. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads of each set by conductive wires.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.

Abstract: In some embodiments, an array capacitor for decoupling multiple voltages is presented. In this regard, an array capacitor is introduced having two electrically isolated capacitor regions. Other embodiments are also disclosed and claimed.

Abstract: A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.

Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.

Abstract: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL. A third dielectric layer is formed under a second die. A second re-distribution conductive layer (RDL) is formed under the third dielectric layer. A fourth dielectric layer is formed under the second RDL. Conductive bumps are coupled to the first RDL and the second RDL. A surrounding material surrounds the second die. The second die is coupled to the first die through the first RDL, second RDL and the conductive bumps.

Abstract: A memory module includes a module substrate and a plurality of package units mounted to the module substrate such that they partially overlap each other. Each package unit has at least one memory semiconductor package attached thereto. Each package unit includes a flexible substrate, which has outer terminals provided over a lower surface adjacent to one edge thereof to form electrical connections with the module substrate, and the memory semiconductor package attached to one surface or each of both upper and lower surfaces of the flexible substrate.

Abstract: A bridge stack integrated circuit package-on-package system is provided including forming a first integrated circuit package system having a first substrate, forming a second integrated circuit package system having a second substrate, and mounting a bridge integrated circuit package system on the first substrate and on the second substrate.

Abstract: A mountable integrated circuit package-in-package system is provided including mounting an adhesion spacer over an integrated circuit die and a package substrate, mounting an integrated circuit package system having an inner adhesion structure with the inner adhesion structure on the adhesion spacer, and forming a package encapsulation for covering the integrated circuit package system over the adhesion spacer.

Abstract: Semiconductor devices and methods for their assembly are described in which IC packages may be combined in novel configurations. A multi-package semiconductor device system and associated methods for its construction include a plurality of packaged semiconductor devices, each provided with at least one lateral electrical contact. The plurality of packaged semiconductor devices so provided are fixed in a coplanar configuration and have the adjacent lateral contacts coupled for operation in concert.

Abstract: A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion, mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion, and forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.

Abstract: A method of forming a package, comprising providing a set of dies on a substrate. The substrate may have a first die on its upper side and a second die on its lower side. A first interconnect may be provided in the substrate, wherein the first interconnect penetrates through the substrate to couple the dies to the substrate.

Abstract: A microelectronic assembly that includes a first microelectronic element having a first rear surface. The assembly further includes a second microelectronic element having a second rear surface. The second microelectronic element is attached to the first microelectronic element so as to form a stacked package. The first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.

Abstract: A method of forming a package, comprising providing a set of dies on a substrate. The dies may be stacked on the substrate and may be coupled to the substrate by an interconnect provided on a side surface of the stacked dies.

Abstract: An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer on a side opposite the base die.

Abstract: An IC package including a plurality of BGA IC packages stacked on a printed circuit board and a method of manufacturing the same. The IC package includes a printed circuit board, a first BGA IC package, having a plurality of first solder balls, stacked on the printed circuit board, a second BGA IC package, having a plurality of second solder balls, stacked on the first BGA IC package, and an interposer having a plurality of through-holes, which are filled by the second solder balls in a molten state such that the length of the second solder balls increases while the second solder balls harden, the interposer being joined to the top of the first BGA IC package.

Abstract: A package on package structure for semiconductor devices comprises at least one first level package having at least first level semiconductor die therein, wherein the package having first level contact pads formed on a first upper and lower surfaces of the first level package, the first level package having a first level upper build up layers and/or a first level lower build up layer to couple to bonding pads of the first level semiconductor die to contact first level pads on the both upper and lower surfaces of the first level package; a second level package having at least one second semiconductor die contained therein, wherein the second level package has a second level contact pads on a second upper and lower surfaces of the second level package, and conductive connecting through holes; wherein the second level package have a second level upper build up layer and/or second level lower build up layer to couple second level bonding pads of the second semiconductor die to contact second level pads and the co