Patents Issued in July 3, 2008
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Publication number: 20080157128Abstract: Provided are methods for producing multiple distinct transistors from a single semiconductor layer, and apparatus incorporating transistors so produced.Type: ApplicationFiled: December 1, 2006Publication date: July 3, 2008Applicant: Johns Hopkins UniversityInventors: Howard E. Katz, Cheng Huang
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Publication number: 20080157129Abstract: An alternative sensing circuit for a micro-electro-mechanical system (MEMS) microphone and a sensing method thereof are provided. The sensing circuit reads out output signals of an MEMS electret microphone or an MEMS condenser microphone. In considering different operating requirements of the different MEMS microphones, for example, low power consumption for the MEMS electret condenser microphone or high sensitivity for the MEMS condenser microphone, the manner of using two kinds of MEMS microphone sensing components in one circuit can significantly increase the flexibility of using the MEMS microphone and can be applied to the application or design of a condenser sensing component.Type: ApplicationFiled: April 13, 2007Publication date: July 3, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Chun Hsu, Wen-Chieh Chou
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Publication number: 20080157130Abstract: A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventor: Peter L.D. Chang
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Publication number: 20080157131Abstract: A selective spacer for semiconductor and MEMS devices and method of manufacturing the same. In an embodiment, a selective spacer is formed adjacent to a first non-planar body having a greater sidewall height than a second non-planar semiconductor body in a self-aligned manner requiring no patterned etch operations. In a particular embodiment, a margin layer of a particular thickness is utilized to augment an existing structure and provide sufficient margin to protect a sidewall with a spacer that is first anisotropically defined and then isotropically defined. In another embodiment, the selective spacer formation prevents etch damage by terminating the anisotropic etch before a semiconductor surface is exposed.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Rajwinder Singh, Willy Rachmady, Uday Shah, Jack T. Kavalieros
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Publication number: 20080157132Abstract: A method of forming a gate of a transistor can include forming a nitride film over a semiconductor substrate; forming a photoresist pattern defining a gate channel region of a transistor over the nitride film; forming a nitride pattern by etching the nitride film using the photoresist pattern as a mask; removing the photoresist pattern; forming an oxide film over the semiconductor substrate using a thermal oxidation process; removing the nitride pattern to expose a portion of the surface of the semiconductor substrate corresponding to the removed nitride pattern; and then forming a recessed pattern corresponding to the gate channel region in the exposed semiconductor substrate.Type: ApplicationFiled: December 10, 2007Publication date: July 3, 2008Inventor: Dae-Young Kim
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Publication number: 20080157133Abstract: A semiconductor device and a fabricating method thereof are provided. A first device having a photodiode cell can be disposed adjacent to a second device having a transistor, and a connection electrode can electrically connect the first device and the second device.Type: ApplicationFiled: October 24, 2007Publication date: July 3, 2008Inventor: JAE WON HAN
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Publication number: 20080157134Abstract: A CMOS image sensor and method the same are disclosed. The method comprises forming an insulating interlayer including a plurality of photodiodes on a semiconductor substrate, forming a plurality of metal lines within the insulating interlayer, sequentially forming an oxide layer and a passivation layer on the insulating interlayer, forming a TEOS layer on the passivation layer, forming a planarization layer on a portion of the TEOS layer, and forming a microlens on the planarization layer.Type: ApplicationFiled: November 30, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventor: Chang Eun LEE
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Publication number: 20080157135Abstract: A CMOS image sensor and a method of manufacturing thereof is capable of preventing a feed-through phenomenon. A CMOS image sensor includes a reset transistor which may include an epi-layer formed over a semiconductor substrate. The reset transistor also includes a channel layer formed over the epi-layer to form a channel. A trap area may be formed in a central portion of the reset transistor. A gate electrode may be formed over the epi-layer with a gate insulating film interposed therebetween. A gate spacer may be formed over both sidewalls of the gate electrode. A diffusion area may be formed at both sides of the gate spacer.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventor: Keun-Hyuk Lim
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Publication number: 20080157136Abstract: A photosensor includes a semiconductor thin film for photoelectric conversion having a first side portion and a second side portion. A source electrode extends in the longitudinal direction of the semiconductor thin film and has a side edge portion that overlaps the first side portion of the semiconductor thin film, and a drain electrode extends in the longitudinal direction and has a side edge portion that overlaps the second side portion of the semiconductor thin film. At least one of the side edge portions of the source and drain electrodes has protruding portions which are arranged along the longitudinal direction and which overlap the semiconductor thin film, and notched portions formed between the protruding portions. An ohmic contact layer is formed between the semiconductor thin film and the protruding portions of the at least one of the side edge portions of the source and drain electrodes.Type: ApplicationFiled: December 20, 2007Publication date: July 3, 2008Applicant: Casio Computer Co., Ltd.Inventors: Hiroshi Matsumoto, Ikuhiro Yamaguchi, Hirokazu Kobayashi
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Publication number: 20080157137Abstract: An image sensor and a method of fabricating an image sensor are provided. The image sensor can include a color filter layer formed on a substrate and a microlens array on the color filter layer. The microlens array includes a first set of microlenses formed of a low temperature oxide layer and a second set of microlenses formed of a photoresist layer. The second set of microlenses can be formed between the first set of microlenses to provide a zero gap.Type: ApplicationFiled: August 21, 2007Publication date: July 3, 2008Inventor: EUN SANG CHO
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Publication number: 20080157138Abstract: A complementary metal oxide semiconductor (CMOS) image sensor (CIS) and a method for fabricating the same. A method for fabricating a CIS includes implanting first conductive type dopants in a semiconductor substrate to form a photodiode region in a surface of the semiconductor substrate, implanting second conductive type dopants in the photo diode region to form a second conductive type diffusion region, and implanting fluorine ions in the second conductive type diffusion region to form a fluorine diffusion region.Type: ApplicationFiled: August 28, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventor: Joung Ho LEE
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Publication number: 20080157139Abstract: An image sensor including a first epitaxial layer having a first photodiode, a second epitaxial layer formed on and/or over the first epitaxial layer, the second epitaxial layer having a second photodiode and a first plug, and a third epitaxial layer formed on and/or over the second epitaxial layer, the third epitaxial layer having a third photodiode, a second plug and an isolation layer.Type: ApplicationFiled: October 9, 2007Publication date: July 3, 2008Inventor: Sang-Gi Lee
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Publication number: 20080157140Abstract: An image sensor including a semiconductor substrate having a photodiode, at least one interlayer dielectric layer formed over the semiconductor substrate and an oxide layer passes through the interlayer dielectric layer.Type: ApplicationFiled: October 9, 2007Publication date: July 3, 2008Inventor: Eun-Sang Cho
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Publication number: 20080157141Abstract: A method of manufacturing a CMOS device including: sequentially forming a first silicon oxide film and a first polysilicon film on a lower substrate; performing an ion implantation process with respect to the first polysilicon film to form a plurality of lower conductors spaced apart from one another at a predetermined interval; forming a plurality of N-type semiconductor films and P-type semiconductor films which are formed by being spaced apart from one another at a predetermined interval and are in contact with the lower conductors; forming a plurality of upper conductors electrically connected to the N-type semiconductor films and P-type semiconductor films; forming an upper substrate on the upper conductors; forming a second polysilicon film on the upper substrate; forming a device isolation film and a photodiode in the second polysilicon film; forming a gate electrode including an insulating sidewall on the second polysilicon film; forming an insulating film on an epitaxial layer with the gate electrodeType: ApplicationFiled: October 19, 2007Publication date: July 3, 2008Inventor: Chang Hun Han
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Publication number: 20080157142Abstract: The present invention relates to a method for manufacturing a CMOS image sensor. The method comprises forming a photodiode and a transistor on a semiconductor substrate which is divided into a pixel region and a peripheral region, forming a plurality of oxide films and metal wiring on the semiconductor substrate, depositing a silicon oxynitride (SiON) layer on the oxide film, performing an array etch in the pixel region in order to reduce the optical length of the pixel region, depositing a silicon nitride (SiN) layer over the etched pixel region and silicon oxynitride layer, and forming a micro lens on the silicon nitride layer. Advantageously, the method prevents the generation of circular defects in the peripheral region while maintaining the refractive index in the pixel region.Type: ApplicationFiled: October 28, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventor: Jeong Su Park
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Publication number: 20080157143Abstract: A CMOS image sensor comprising an epitaxial layer formed on a semiconductor layer, a device isolating layer formed on the epitaxial layer in order to divide the isolating layer into an active region and a device isolating region, the active region including a photo diode region and a transistor region, a drive transistor including a gate electrode formed on the epitaxial layer and a gate spacer formed on both side walls of the gate electrode, a floating diffusion region formed on the epitaxial layer, a trench hole formed in the device isolating layer and epitaxial layer in an area between the photo diode region and the floating diffusion region, a poly wiring formed in the trench hole which extends from the gate electrode to the drive transistor, and an impurity diffusion region formed by ion implanting the epitaxial layer on the side of the gate spacer.Type: ApplicationFiled: November 30, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventor: Keun Hyuk LIM
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Publication number: 20080157144Abstract: A method of fabricating a CMOS image sensor comprising forming an epitaxial layer on a semiconductor substrate, the epitaxial layer comprising a pixel and logic area, forming an STI layer in an insulating layer on the epitaxial layer, forming a plurality of wells and a gate pattern having a spacer on the insulating layer, forming a plurality of source and drain regions in the insulating layer using ion implantation, forming a salicide blocking layer on the insulating layer and gate pattern in the pixel area, forming a plurality of silicide layers in the logic area by performing a silicidation process, sequentially forming a PMD liner nitride layer and a PSG (phosphosilicate glass) layer on the salicide blocking layer in the pixel area and the insulating layer and gate pattern in the logic area, and forming a plurality of contacts connecting the PSG layer to the source and drain regions.Type: ApplicationFiled: November 30, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventor: Sang Gi LEE
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Publication number: 20080157145Abstract: A method of fabricating a CMOS image sensor can include forming a first conductive type epitaxial layer on a heavily doped first conductive type substrate, forming a device isolation layer on a prescribed portion of the epitaxial layer, forming a gate electrode on an active area of the epitaxial layer defined by the device isolation layer, forming a second conductive type first diffusion area to be connected to a surface of the epitaxial layer by carrying out ion implantation on the epitaxial layer for forming a photodiode therein, and forming a second conductive type second diffusion area by carrying out ion implantation on a boundary between the gate electrode and the first diffusion area. Accordingly, the gate and the depletion region of the photodiode are connected, thereby suppressing noise generation by enabling electrons trapped by defects to move freely via the depletion area.Type: ApplicationFiled: December 10, 2007Publication date: July 3, 2008Inventor: Dong-Bin Park
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Publication number: 20080157146Abstract: An image sensor includes: a photodiode and a transistor formed in a semiconductor substrate that is defined as a device isolation region and an active region; a first interlayer insulating film formed over the semiconductor substrate; a metal wire formed over the first interlayer insulating film; a second interlayer insulating film formed over the first interlayer insulating film including the metal wire; and a color filter layer and a micro lens formed over the second interlayer insulating film. The first interlayer insulating film includes a first tetraethyl orthosilicate (TEOS) film, a first hydrogen silsequioxane (HSQ) film, and a second tetraethyl orthosilicate film, which are sequentially laminated.Type: ApplicationFiled: December 18, 2007Publication date: July 3, 2008Inventors: Jung-Kyu Kim, Yeo-Jo Yun
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Publication number: 20080157147Abstract: A CMOS image sensor and method of manufacture reduces the problem of electron loss in a floating diffusion area. A method of fabricating a CMOS image sensor includes forming a gate electrode over a first conductive type semiconductor substrate. A second conductive type first diffusion layer is formed within the semiconductor substrate to be aligned with an edge of one side of the gate electrode. A spacer may be attached to both sidewalls of the gate electrode. A first conductive type second diffusion layer may be formed within the first diffusion layer to leave a distance amounting to a width of the spacer in-between. A second conductive type third diffusion layer may be formed within the semiconductor substrate to be aligned with an edge of the other side of the gate electrode. A first conductive type fourth diffusion layer may be formed over the third diffusion layer, and a first conductive type fifth diffusion layer may be formed under the third diffusion layer.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventor: Keun-Hyuk Lim
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Publication number: 20080157148Abstract: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a logic circuit part. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the logic circuit part of the second wafer.Type: ApplicationFiled: December 26, 2007Publication date: July 3, 2008Inventor: JAE WON HAN
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Publication number: 20080157149Abstract: A CMOS image sensor may include a gate electrode on a gate insulating layer in an active region of a semiconductor substrate; a photodiode region in the semiconductor substrate on one side of the gate electrode; a floating diffusion region in the semiconductor substrate on another side of the gate electrode; and a complementary impurity region in the semiconductor substrate on the other side of the gate electrode, overlapping with the floating diffusion region.Type: ApplicationFiled: December 11, 2007Publication date: July 3, 2008Inventor: Seung Hyun Kim
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Publication number: 20080157150Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.Type: ApplicationFiled: December 13, 2007Publication date: July 3, 2008Inventor: Hee Sung Shim
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Publication number: 20080157151Abstract: Embodiments of the invention relate to a CMOS image sensor. In detail, a CMOS image sensor can have improved sensitivity. The CMOS image sensor includes a photodiode on a semiconductor substrate, a drive transistor including a gate connected to the photodiode, a first grounded electrode and a second electrode connected to a current detector, a transfer transistor connected between the photodiode and the gate to apply voltage or charges generated in the photodiode to the gate, an optional select transistor between the second electrode and the current detector, and an optional reset transistor connected to a power line, configured to reset the photodiode. Accordingly, the CMOS image sensor can read the output of a photodetector without substantial attenuation.Type: ApplicationFiled: December 13, 2007Publication date: July 3, 2008Inventor: Byung Tak Jang
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Publication number: 20080157152Abstract: The embodiment relates to a complementary metal oxide semiconductor (CMOS) image sensor and more particularly, to a CMOS image sensor and a manufacturing method thereof capable of improving electron storing capacity in a floating diffusion area. The CMOS image sensor includes a first gate electrode on a semiconductor substrate; a photodiode in the semiconductor substrate on one side of the first gate electrode; a floating diffusion area in the semiconductor substrate on an opposite side of the first gate electrode; a capacitor including a lower capacitor electrode connected to the floating diffusion area, a dielectric layer on the lower capacitor electrode, and an upper capacitor electrode; a drive capacitor coupled to the lower capacitor electrode and having a second gate electrode connected to the floating diffusion area. The electron storing capacity of the floating diffusion node is increased, making it possible to improve the dynamic range of the image sensor.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventor: Hee Sung Shim
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Publication number: 20080157153Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).Type: ApplicationFiled: March 4, 2008Publication date: July 3, 2008Applicant: CANON KABUSHIKI KAISHAInventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
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Publication number: 20080157154Abstract: A Complementary Metal Oxide Semiconductor (CMOS) image sensor and methods for fabricating the same. In one example embodiment of the invention, a method for manufacturing a Complementary Metal Oxide Semiconductor (CMOS) image sensor includes several acts. First, a metal pad is formed over a semiconductor substrate. Next, a protection film is formed over the semiconductor substrate and the metal pad. Then, the protection film is selectively removed to expose a surface of the metal pad. Next, a first planarization film is formed over the protection film. Then, a color filter layer is formed over the first planarization film. Next, a second planarization layer is formed over the color filter layer. Then, a first material layer is formed over the second planarization layer. Next, a second material layer is formed over the first material layer. Then, a micro lens is formed out of the first and second material layers.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventor: Sang Sik Kim
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Publication number: 20080157155Abstract: According to one embodiment, after forming transistors on a semiconductor substrate, a stopper layer and an interlayer insulating film are formed. Then, a contact hole is formed in the interlayer insulating film and a copper film is formed on the interlayer insulating film to bury the inside of the contact hole with copper. After that, the copper film on the interlayer insulating film is removed by low-pressure CMP polishing or ECMP polishing to planarize a surface thereof to form plugs. Thereafter, a barrier metal, a lower electrode, a ferroelectric film, and an upper electrode are formed. In this manner, a semiconductor device (FeRAM) having a ferroelectric capacitor is formed.Type: ApplicationFiled: February 28, 2008Publication date: July 3, 2008Applicant: FUJITSU LIMITEDInventor: Wensheng WANG
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Publication number: 20080157156Abstract: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.Type: ApplicationFiled: March 18, 2008Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sivananda K. Kanakasabapathy, David W. Abraham
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Publication number: 20080157157Abstract: A DRAM capacitor uses ruthenium or ruthenium oxide as an upper electrode and hafnium dioxide or zirconium oxide as an insulation layer. The DRAM capacitor is intended to suppress diffusion of ruthenium, etc. into hafnium dioxide. Tantalum pentoxide or niobium oxide having a higher permittivity than that of the insulation layer is inserted as a cap insulation layer to the boundary between the upper electrode of ruthenium or ruthenium oxide and the insulation layer of hafnium dioxide or zirconium oxide to thereby suppress diffusion of ruthenium, etc. into hafnium dioxide, etc.Type: ApplicationFiled: November 15, 2007Publication date: July 3, 2008Inventors: Osamu TONOMURA, Hiroshi MIKI, Tomoko SEKIGUCHI, Kenichi TAKEDA
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Publication number: 20080157158Abstract: A semiconductor device capacitor fabrication method that is capable of enabling the simultaneous use of an oxide capacitor and a PIP capacitor of a semiconductor device depending upon whether metal line terminals are used. The semiconductor device capacitor fabrication method can include forming an active region and a first gate electrode over a semiconductor substrate, partially depositing a silicon nitride layer, over which a capacitor will be formed, over the first gate electrode, forming a second gate electrode over the silicon nitride, sequentially forming a first insulation layer and a second insulation layer over the resultant structure and forming line terminals extending through the first insulating layer and the second insulating layer for a transistor and a capacitor.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventor: Jung-Ho Ahn
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Publication number: 20080157159Abstract: A metal-on-semiconductor varactor with a high value of Cmax/Cmin comprises a semiconductor bottom plate with an array of semiconductor pillars. The pillars may be in an accumulation mode to provide a high capacitance or in a depletion mode to provide a low capacitance. The maximum capacitance in an accumulation mode is primarily determined by the capacitance of the semiconductor pillars. The minimum capacitance in a depletion mode is primarily determined by a capacitor formed on an inter-pillar semiconductor surface between the semiconductor pillars. The minimum capacitance, and hence the value of Cmax/Cmin may be tuned by adjusting process parameters, design parameters and by alterations in the MOS varactor structure such as forming a highly doped semiconductor layer beneath the inter-pillar semiconductor surface or forming a plate insulator.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Jae-Eun Park
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Publication number: 20080157160Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first interlayer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Applicant: SPANSION LLCInventor: Simon S. Chan
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Publication number: 20080157161Abstract: Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate. Other embodiments including additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Qiang Tang, Venkat Narayanan
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Publication number: 20080157162Abstract: An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Inventors: Brian S. Doyle, Suman Datta, Jack Kavalieros, Robert Chau
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Publication number: 20080157163Abstract: There are provided EEPROM devices and methods of forming the same. The device includes: a substrate having an active region defined by a device isolation layer; a first sense line and a second sense line which straightly extend on the substrate and have a memory gate; a first word line and a second word line which extend to be parallel to the first sense line and the, second sense line at the substrate and have a select gate; and an isolation region which extends in a direction crossing an extension direction of the first sense line and the second sense line to parts of the first and second word lines, which discontinuously electrically isolates the memory gates, and which makes the select gate stepped.Type: ApplicationFiled: January 2, 2008Publication date: July 3, 2008Applicant: Samsung Electronics Co., Ltd.Inventor: Weon-Ho Park
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Publication number: 20080157164Abstract: Disclosed are methods for fabricating a flash memory. One method comprises forming an oxide layer on both a gate structure, which includes a floating gate and a control gate, on a cell area and a gate on a periphery area of a semiconductor substrate. An insulating layer having a thickness of 800 ? to 1200 ? can be formed on the oxide layer, and a photoresist pattern that covers the periphery area while exposing the cell area can be formed. The insulating layer formed on the exposed cell area can be wet-etched such that the insulating layer on the cell area has a thickness different from a thickness of the insulating layer on the periphery area. After the photoresist pattern is removed, spacers can be formed by performing reactive-ion etching over an entire surface of the semiconductor substrate.Type: ApplicationFiled: October 25, 2007Publication date: July 3, 2008Inventor: JI HO HONG
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Publication number: 20080157165Abstract: A flash memory device and a method of manufacturing a flash memory device are provided. The flash memory device includes a gate region on a semiconductor substrate, spacers on sidewalls of the gate region, and a passivation layer between the semiconductor substrate and a portion of each spacer.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventor: JIN HA PARK
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Publication number: 20080157166Abstract: A flash memory device including a cell region and a logic region formed over a semiconductor substrate; a pair of stacked gates formed spaced apart over the cell region; a pair of first spacers formed over the cell region in direct contact with at least one side of the stacked gates; a pair of gate electrodes formed spaced apart over the logic region; a pair of second spacers formed over the logic region in direct contact with at least one side of the gate electrodes; a first photoresist layer formed over the cell area between the first spacers and a second photoresist layer formed over the logic area between the second spacers, the second photoresist layer having a predetermined thickness sufficient to protect the second spacers.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventor: Cheon Man Sim
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Publication number: 20080157167Abstract: Embodiments relate to a flash memory device and to method of fabricating a flash memory device is disclosed. According to embodiments, a method may include forming a device isolation layer on a semiconductor substrate to define active regions, forming floating gate patterns on the active regions, forming the photoresist patterns on the device isolation layer such that the photoresist patterns have side walls higher than the floating gate patterns, forming spacer patterns at the side walls of the photoresist patterns such that the spacer patterns partially cover the floating gate patterns, and etching the floating gate patterns by a predetermined depth using the spacer patterns as an etching mask.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventor: Tae-Woong Jeong
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Publication number: 20080157168Abstract: A nonvolatile memory includes a semiconductor substrate having a body member and a step member formed on the body member, a highly doped first well layer formed on the step member, a control electrode formed on the step member, a first and a second diffusion layers in the substrate, lightly doped second well layers formed on the main surface of the substrate between the first or the second diffusion layer and the first well layer, and a first and a second charge-storage multi-layers sandwiching the step member and the control electrode, each of the first and the second charge-storage multi-layers including a bottom oxide layer, a charge-storage film, a top oxide layer and a floating electrode which are formed in that order.Type: ApplicationFiled: December 5, 2007Publication date: July 3, 2008Inventor: Toshikazu Mizukoshi
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Publication number: 20080157169Abstract: Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventor: Jack H. Yuan
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Publication number: 20080157170Abstract: An electrically programmable memory cell and corresponding method for fabricating the same, provide a reduced electron tunneling threshold to reduce parasitic substrate currents during cell programming. A floating gate of the cell is formed over an injector dopant region diffused within and encompassed by a first dopant region. Both dopant regions are situated beneath a self-aligned tunneling window of the floating gate. The dopant regions are each high concentration dopants and of complementary species to one another. The injector dopant region produces an increase in surface potential that lowers a tunneling barrier height and produces the lower electron tunneling threshold.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Applicant: ATMEL CORPORATIONInventor: Bohumil Lojek
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Publication number: 20080157171Abstract: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Prashant Majhi, Kyu S. Min, Wilman Tsai
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Publication number: 20080157172Abstract: The present invention relates to a nano-scale flash memory device having a saddle structure, and a fabrication method thereof. Particularly, the invention relates to a highly integrated, high-performance flash memory device having a saddle structure for improving the scaling-down characteristic and performance of the MOS-based flash memory device. According to the invention, a portion of an insulating film around a recessed channel is selectively removed to expose the surface and sides of the recessed channel. A tunneling insulating film is formed on the exposed surface and sides of the recessed channel. On the resulting structure, a floating electrode, an inter-electrode insulating film and a control electrode are formed, thus fabricating the device. Particularly when the floating electrode is made of an insulating nitride film or pluralities of nano-scale dots, an excellent memory device can be made without using an additional mask.Type: ApplicationFiled: December 6, 2005Publication date: July 3, 2008Inventor: Jong-Ho Lee
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Publication number: 20080157173Abstract: A flash memory device includes a tunnel insulating layer formed over a semiconductor substrate, a charge trap layer formed over the tunnel insulating layer and configured to trap electric charges, a blocking insulating layer formed over the charge trap layer, and a gate electrode formed over the blocking insulating layer and including a first conductive layer and a second conductive layer doped with N and P impurities respectively. Further, a method of erasing a flash memory device includes providing a flash memory device including a gate electrode having a first conductive layer and a second conductive layer doped with N and P impurities respectively, and performing an erase operation in a state where a thickness of a depletion layer at an interface of a PN junction comprising the first conductive layer and the second conductive layer is increased due to a negative potential bias applied to the gate electrode.Type: ApplicationFiled: May 14, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Young-Ok HONG
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Publication number: 20080157174Abstract: A non-volatile memory device and a method of fabricating the same are disclosed. The method includes the steps of: providing a semiconductor substrate having isolation layers in an isolation region, a tunnel insulating layer formed between the isolation layers, and first electron charge layers formed between the isolation layers, wherein the isolation layers comprise projections extending higher than the semiconductor substrate; etching the first electron charge layers, thereby reducing the thickness of the first electron charge layers and exposing sidewalls of the isolation layers; performing a first etch process to reduce the width of the projections; forming second electron charge layers between the projections on the first electron charge layers; and performing a second etch process to remove the projections between the second electron charge layers.Type: ApplicationFiled: June 28, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Yoo Nam Jeon
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Publication number: 20080157175Abstract: A flash memory device and method of fabricating the same are provided. A flash memory device includes a tunnel insulating layer on a substrate, a floating gate on the tunnel insulating layer, and ONO layer on the floating gate, and a control gate formed oil the ONO layer. According to an embodiment, the ONO layer of a first oxide layer, a nitride layer, and a second oxide layer is formed from a single oxide film deposited on the floating gate. The nitride layer can be formed between the first oxide layer and the second oxide layer by nitriding a vertically intermediate region of the single oxide film.Type: ApplicationFiled: September 28, 2007Publication date: July 3, 2008Inventor: DAE YOUNG KIM
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Publication number: 20080157176Abstract: A nonvolatile memory device having lower bit line contact resistance and a method of fabricating the same is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type may include first and second fins. A common bit line electrode may connect one end of the first fin to one end of the second fin. A plurality of control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode may be positioned between the common bit line electrode and the plurality of control gate electrodes. The first string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode may be positioned between the first string selection gate electrode and the plurality of control gate electrodes.Type: ApplicationFiled: September 21, 2007Publication date: July 3, 2008Inventors: Won-joo Kim, Yoon-dong Park, June-mo Koo, Suk-pil Kim, Sung-jae Byun
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Publication number: 20080157177Abstract: A flash device and a manufacturing method thereof are provided. An ONO pattern can be formed on a floating gate, and a control gate can be formed on the ONO pattern. The ONO pattern can be formed with a portion that projects farther out than the sides of the floating gate and the control gate.Type: ApplicationFiled: October 30, 2007Publication date: July 3, 2008Inventor: HYUN JU LIM