Abstract: A semiconductor device, and method for manufacturing a device with selective copper plating in a deep via. The method comprises etching a plurality of deep trenches in the surface of wafer, sequentially forming an insulating layer, a copper anti-diffusion layer, a metal layer, and a copper seed layer over the surface and deep trenches of the wafer, performing a first planarization process in order to remove the copper seed layer on the surface of wafer while retaining the copper seed layer in the deep trenches of the wafer, and forming a plurality of via patterns by copper plating the copper seed layer remaining in the deep trenches of the wafer.

Abstract: A method for fabricating a semiconductor device having a metal wiring is provided. The method includes: forming an inter-metal dielectric (IMD) layer on the semiconductor substrate having a first metal wiring formed therein, the IMD layer including a first IMD layer and a second IMD layer; forming a via hole in the IMD layer to expose the first metal wiring; forming an ion barrier layer on sidewalls of the via hole; forming a diffusion barrier layer on the semiconductor substrate, on which the ion barrier layer has been formed; forming a metal layer on the semiconductor substrate in the via hole; and forming a second metal wiring on the semiconductor substrate, the second metal wiring contacting the metal layer in the via hole.

Abstract: Disclosed is a method for forming a metal interconnection in a semiconductor device. In a damascene process, a capping barrier metal layer is formed generally only on a lower metal interconnection in order to prevent the diffusion of atoms from the lower metal interconnection into an upper dielectric layer. The capping barrier metal layer prevents the increase of an effective dielectric constant of a lower inter-metal dielectric layer that surrounds the lower metal interconnection, and may reduce the resistance of the metal interconnection, thereby improving the reliability, speed and/or other characteristics of the semiconductor device.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: Direct termination of a wiring metal in a semiconductor device. Direct termination of an AlCu stack or an AlCu layer is made with an underlying Cu wiring level. The AlCu stack or AlCu layer covers all of the Cu wiring level such that it has a border that extends beyond all of the wiring to prevent exposure from occurring.

Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

Abstract: Disclosed is a method of manufacturing an alignment key of a semiconductor device. According to an embodiment, the method includes forming an insulating layer on a semiconductor substrate on which a cell region and a scribe line are defined, forming a photoresist pattern on the insulating layer and etching the insulating layer using the photoresist pattern as an etch mask so as to form a contact hole on the cell region and a mark hole on the scribe line, depositing a metal layer in the contact hole and the mark hole, and planarizing the metal layer so as to form a contact and an alignment mark. The mark hole can be the same size as the contact hole. In addition, the mark hole can be formed in plurality on the scribe line.

Abstract: Multi-layer semiconductor devices and methods for their assembly are described in which the IC packages are endowed with vertical passive delay cells in order to approximately equalize, within selected design tolerances, the signal propagation delays among electrical traces within the package.

Abstract: A semiconductor device includes a semiconductor substrate with a pattern region and a dummy region, an interlayer dielectric film arranged on the semiconductor substrate, a semiconductor layer pattern arranged on the interlayer dielectric film in the pattern region, a dummy pattern arranged on the interlayer dielectric film in the dummy region, a contact plug arranged inside the interlayer dielectric film, and the contact plug connecting the semiconductor layer pattern to the semiconductor substrate, and a dummy plug arranged inside the interlayer dielectric film, the dummy plug corresponding to the dummy pattern. A method for fabricating the semiconductor device includes forming these structures.

Abstract: The present invention relates to a semiconductor device, comprising a plurality of word lines arranged on a semiconductor substrate, wherein plurality of word lines are grouped into groups of two word lines, a spacer dielectric layer formed between each group of two word lines, and an interlayer dielectric layer formed so as to fill the area between the word lines in each group of two word lines and cover the word lines and the spacer dielectric layers.

Abstract: A semiconductor device and fabricating method thereof are provided. A semiconductor substrate includes at least two holes for receiving devices, and at least two devices are inserted into the holes of the semiconductor substrate. Connection electrodes electrically connect the devices with each other, and the bonding pad portion provides signal connection between the connected devices and an outside device.

Abstract: Provided are a semiconductor package and a module printed circuit board (PCB) for mounting the same. Each of the semiconductor package and the module PCB includes a substrate, a first-type pad structure disposed in a first region of the substrate, and a second-type pad structure disposed in a second region of the package substrate. The first-type pad includes a first conductive pad disposed on the package substrate and a first insulating layer coated on the package substrate. The first insulating layer has a first opening by which a portion of a sidewall of the first conductive pad is exposed, and partially covers the first conductive pad. The second-type pad includes a second insulating layer coated on the package substrate to have a second opening and a second conductive pad disposed on the package substrate in the second opening to have an exposed sidewall.

Abstract: A method of forming a low-k dielectric layer and structure thereof are disclosed. The present invention forms a BSG layer containing fluorine as an insulating interlayer beneath an FSG layer to enable the BSG layer to capture fluorine diffusing from the FSG layer. Accordingly, the present invention is able to effectively prevent such a problem as a dielectric constant increase of a lower insulating interlayer due to fluorine diffusion, signal transfer characteristic degradation, poor adhesion between the lower insulating interlayer and a barrier metal layer, delamination due to the poor adhesion, and the like.

Abstract: RF semiconductor devices and methods of making the same are disclosed. In a disclosed method, a trench for defining an active region and an element isolation region is formed in a semiconductor substrate. One or more gate lines is then formed within the active region. Next, an insulating layer is formed on the semiconductor substrate and the gate lines. Contact holes are then formed in the insulating layer. Contact plugs are then formed in the contact holes. Thereafter, a conductive pattern is electrically connected with the contact plugs.

Abstract: Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.

Abstract: A semiconductor device comprises a package board, a first semiconductor chip which is rectangular in shape, has a plurality of first pads arranged along its short side and is placed on the package board, and a second semiconductor chip which is rectangular in shape, has a plurality of second pads arranged along its short side and is placed on the first semiconductor chip so that a vertex of the second semiconductor chip at which its long side and its short side along which no pads are arranged meet falls on a vertex of the first semiconductor chip at which its long side and its short side along which no pads are arranged, and the long sides of the first and second semiconductor chips intersect each other.

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: A flip-chip package may include: a semiconductor chip having first pads arranged substantially along a first direction; a substrate having second pads, arranged substantially in a zigzag form aligned with the first pads as a center line, and facing the semiconductor chip; and conductive bumps for electrically connecting the first pads to the second pads in a one-to-one relationship. Adjacent conductive bumps may extend in different directions. A method of manufacturing a flip-chip package may include: forming conductive bumps that extend along different directions on first pads of a semiconductor chip; and connecting second pads of a substrate to the conductive bumps in a one-to-one relationship. A method of manufacturing a flip-chip package may include: forming conductive bumps that extend along different directions on second pads of a substrate; and connecting first pads of a semiconductor chip to the conductive bumps in a one-to-one relationship.

Abstract: The present invention provides a semiconductor device package having pseudo chips structure comprising a first substrate with die receiving through holes formed thereon; a first die having first bonding pads and a second die having second bonding pads disposed within the die receiving through holes, respectively; an adhesion material formed in the gap between the first and second die and sidewalls of the die receiving though holes of the first substrate; redistribution lines formed to couple the first contact pads formed on the first substrate to the first bonding pads and the second bonding pads, respectively; and a protection layer formed on the redistribution lines, the first die, the second die and the first substrate.

Abstract: Embodiments relate to forming a pre-metal dielectric (PMD) layer. According to embodiments, the method may include depositing material of which the pre-metal dielectric layer is made on a semiconductor substrate through a chemical vapor deposition (CVD) process employing a high frequency (HF) power in a range from about 2550 mW to about 2650 mW; and polishing the material to form the pre-metal dielectric layer.

Abstract: A semiconductor module includes a semiconductor chip sealed with an encapsulation resin prevented from overflowing from an inside of the outer edge by a wiring pattern extended portion extending from the wiring pattern along an outer edge of a solder resist pattern at an outside of the outer edge of the solder resist pattern.

Abstract: An integrated circuit package system includes a bottom pad with a bottom tie bar, attaching an integrated circuit die over the bottom pad, attaching a top pad with a top tie bar, over the integrated circuit die, and applying an encapsulant wherein the top tie bar integral to the top pad, is exposed on a side of the encapsulant.

Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract: A method for fabricating a device adapted for precision aligning integrated circuits having small-scale architecture in a stack, the method includes obtaining dimensions of the integrated circuits; fabricating a precision guide using the dimensions; and fabricating alignment fiducials into at least one of the precision guide and a carrier wafer. A method for placing integrated circuits having small-scale architecture into a stack, the method includes selecting a device adapted for precision aligning the integrated circuits into the stack and precision aligning the integrated circuits into the stack.

Abstract: A recyclable stamp device and a recyclable stamp process for wafer bond are provided. The recyclable stamp device includes a substrate, a protective layer, a stack film structure and a cap. The protective layer is disposed on the substrate. An opening is positioned at the substrate and the protective layer to expose the substrate. The stack film structure includes an adhesion layer, a stress control layer and a wafer bond alignment mark layer. The adhesion layer is disposed on the protective layer and the exposed substrate. The stress control layer is disposed on the adhesion layer. The wafer bond alignment mark layer is disposed on the stress control layer. The wafer bond alignment mark layer includes an alignment mark at a side of the opening. The cap has a capping portion disposed on the wafer bond alignment mark layer corresponding to the opening.

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract: A composite hollow aspirator shaft is formed of fiberglass-reinforced phenolic resin that reduces the amount of vibration that is transferred to the motor rotating the shaft, and the motor's bearings. This extends motor and bearing life. When the aspirator tip is rotated in a liquid, fluidic forces are transferred to the shaft. Rather than transmitting those forces into the motor and its bearings, the composite aspirator shaft attenuates the forces to prevent most of them from reaching the motor and its bearings. The composite shaft material has a flexural modulus, or ratio, within the elastic limit of any applied stress, and is sufficiently low to allow the transfer of the flexural or oscillatory energy into heat within the shaft instead of conveying the energy in the form of vibration/oscillations along the axial length of the shaft. As an added advantage, the fiberglass resists abrasion better in wastewater than stainless steel used in the prior art.

Abstract: Various embodiments are described for humidifying an air stream in a duct are described. In one form the duct is part of a humidification system in a building such as a residence or commercial structure while in another form the duct is part of a standalone unit. The described embodiments use ultrasonic elements for generating a mist composed of droplets and fog and the fog is drawn or pushed by an air stream towards a duct. The duct utilizes a dispersal structure formed of one or a plurality of tubes with openings and distributed at least partly across the duct so that the air stream in the duct can entrain the fog and distribute this in manner whereby the fog can quickly dissipate and evaporate for humidification of the air stream.

Abstract: A sauna apparatus includes a heating section for heating air to generate heated air, a heated-air-blowing section for sending the heated air, a humidifying section for humidifying air to generate humidified air, a humidified-air-blowing section for sending the humidified air, a merging chamber for mixing the sent heated air and the sent humidified air to generate heated and humidified air, and an outlet for blowing the heated and humidified air generated. This sauna apparatus provides air having uniform temperature distribution and uniform humidity distribution, and allows temperature and humidity to be controlled easily.

Abstract: The invention concerns a device for increasing the relative humidity of an air flow (13), comprising air humidifying means (25) which are arranged in the air flow (13), and which are configured to supply humidifying water to the air flow (13). The invention is characterized in that said air humidifying means (25) are connected to a humidifying circuit (5) which comprises a recycling pump (7) for recycling the humidifying water in the humidifying circuit (5), and a humidifying heat exchanger (13) for heating the humidifying water so that it reaches a temperature lower than boiling point. The invention aims at creating a device enabling the humidifying power to be significantly increased, at a low cost and with little space requirement. Therefor, the humidifying means include a hollow porous material (15) which is connected to the humidifying circuit (5).

Abstract: There is provided an optical modeling apparatus that forms a model of a desired shape by sequentially forming hardened layers by irradiating a light curable resin with light. The apparatus includes a first light source that emits a light beam for plotting on the resin, a scanning device that scans the light beam from the first light source over the resin, a second light source that emits light that irradiates one fixed region of the resin at a time, a spatial light modulator that spatially modulates the light from the second light source and blanket-exposes a specified region of the resin, and an exposure position adjuster that moves, in at least one direction, the light from the spatial light modulator. The light beam from the scanning device and the light from the spatial light modulator form each hardened layer.

Abstract: The method of manufacturing an optical interference color display is described. A first electrode structure is formed over a substrate first. At least one first area, second area and third area are defined on the first electrode structure. A first sacrificial layer is formed over the first electrode structure of the first area, the second area and the third area. Moreover, a second sacrificial layer is formed over the first sacrificial layer inside the second area and the third area. In addition, a third sacrificial layer is formed over the second sacrificial layer inside the third area. The etching rates of all sacrificial layers are different. Then, a patterned support layer is formed over the first electrode structure. Next, a second electrode layer is formed and the sacrificial layers are removed to form air gaps. Therefore, the air gaps are effectively controlled by using the material having different etching rates.

Abstract: A mold structure, a patterning method thereof and a method of fabricating an LCD device using the same are disclosed, which can realize a conformal contact by applying a voltage between a mold structure and a material layer being opposite to each other in an In-Plane Printing process, so as to prevent defective patterns, wherein the mold structure comprises a mold whose surface is provided with patterns; a backplane for supporting the mold; and a conductive film formed between the backplane and the mold.

Abstract: A composition and a method for fabricating microcapsules encapsulating phase-change material by interfacial condensation polymerization are provided. In this composition and method, a surfactant and an organic solvent are not needed.

Abstract: A method of manufacturing low-haze plastic window glazing is claimed where a portion of a panel mold interior is polished with an abrasive material no finer than 600 grit size. Plastic resin is then introduced into the mold under heat and pressure to form a panel. Weatherable coating is then applied to portions of the panel via a wet coating process. An abrasion resistant coating is then applied to portions of the panel via a plasma application technique. This method produces a window glazing with at least one portion having no more than 1% haze.

Abstract: The present invention relates to a wheelchair having a back plate and a seat plate and a manufacturing method thereof, and more particularly, to a customized wheelchair having a back plate and a seat plate formed to fit a body shape and a manufacturing method thereof. In a method of manufacturing a customized wheelchair having a back plate and a seat plate which are designed to fit a body shape, the method includes steps of: forming a preliminary molding material which is directly formed to fit a back and a hip of a user; fixing the preliminary molding material to a molding frame; filling a foaming resin in the molding frame fixed with the preliminary molding material; hardening the foaming resin filled in the molding frame; and releasing a last molding material which is foamed and hardened to have a shape of the back and the hip of the user by the preliminary molding material.

Abstract: Methods for fabricating a composite structure with a flange having a tethered corner involving providing a composite structure forming tool including a first endplate and a second endplate and having a composite structure formed thereabout, applying at least one ply of barrier fibers about the composite structure adjacent to the first endplate of the composite structure forming tool, and wrapping at least one fiber tow about the barrier fibers.

Abstract: Disclosed herein is a method of manufacturing electrolyte-impregnated anode and cathode for a molten carbonate fuel cell. The method is intended to manufacture electrolyte-impregnated electrodes for controlling an electrolyte present in unit cells of a molten carbonate fuel cell by adding electrolyte powder to prepare an electrolyte slurry, which is necessary for forming electrodes, molding electrodes containing an electrolyte in an in-situ state so that they meet the specifications for the unit cells of a fuel cell stack using a tape casting method, and then sintering the electrodes. The method includes preparing electrolyte slurry, nickel slurry and organic substance slurry; mixing the electrolyte slurry with the nickel slurry and the organic substance slurry to form mixed slurry; defoaming the mixed slurry; tape-casting the mixed slurry; and drying and sintering the tape-cast slurry.

Abstract: A filter housing, in particular for an air filter for the air intake tract of an internal combustion engine, in which the filter housing (16) includes at least one upper housing section (12) and at least one lower housing section (11) which can be assembled to each other in a sealed manner. The housing sections (11, 12) are produced as centrifugally cast parts and have a geometrically defined outer face (A) and a geometrically defined inner face (I) configured such that the outer face of one of the housing sections (11, 12) can be connected to the inner face of the other housing section, whereby the housing sections can be manufactured in a cost-effective manner and can fit one another snugly.

Abstract: In a skin needle manufacturing apparatus 10, a material melted in a syringe 45 is discharged from a fine hole 47a of a pin member 47 and is caused to adhere to a base 48. A computer 50 causes a drive mechanism 48 to separate the pin member 47 from the base 48. Then, the material 80 having adhered to the pin member 47 and the base 48 is drawn out. A projection portion 48b formed of a part of the material 80, which has adhered to the base 48, is formed into a skin needle 81. Consequently, a skin needle can relatively easily be manufactured without requiring excessive time, effort, and cost.

Abstract: A composition containing a proton-conductive copolymer, a polymer electrolyte membrane containing the composition; a method of producing the membrane; and a fuel cell employing the membrane. The composition includes: a proton-conductive copolymer comprising a first styrene repeating unit, a second styrene repeating unit, and a dimethylsiloxane repeating unit; and a cross-linked polymer obtained from a cross-linking reaction between a siloxane oligomer having an unsaturated bond and a cross-linking agent. The cross-linked polymer has the same properties as the dimethylsiloxane repeating unit of the proton-conductive copolymer.

Abstract: The invention relates to a method for the transverse drawing of an unoriented or longitudinally-oriented film web made from thermoplastic plastic. According to said method, an undrawn or longitudinally-drawn film (9) is introduced into a transverse drawing frame in which heater fields (1) are heated to a transverse drawing temperature TQ, in the attached drawing fields (2) a clip chain is drawn in the transverse direction by divergent (V-shaped) guides and a temperature TF is applied to fixing fields where TQ>TF. In the drawing fields and/or the heating fields (1) the boundary zones (5) of the film (8) are heated or thermally insulated such that the boundary zones (5) of the film (8) have a higher temperature than the middle of the film web (6) on transverse drawing and/or fixing.

Abstract: A process by which many kinds of unstretched films comprising a thermoplastic resin are produced each in a small amount and high yield. A thermoplastic resin (A) to be formed into an unstretched film and another thermoplastic resin (B) are separately melted by heating. The thermoplastic resin (B) is introduced to each edge part of a T-die (2) for extrusion. The two resins are ejected and extruded on a casting roll so that the thermoplastic rosin (B) is disposed on the side of each edge of the thermally melted thermoplastic resin (A). Thus, an unstretched film (20) is formed which comprises the thermoplastic resin (A) and the thermoplastic resin (B) disposed on the side of each edge of the resin (A). Thereafter, the parts constituted of the thermoplastic resin (B) are removed y cutting to form a target unstretched film (20) consisting only of the thermoplastic resin (A).

Abstract: The invention provides carpet fibers prepared from a blend of polymeric components, said fiber exhibiting improved properties, such as improved spinnability and improved fire resistance. The carpet fibers particularly comprise a majority of polytrimethylene terephthalate (PTT) and a minority of polyethylene terephthalate (PET). The invention further provides yarns and carpets prepared from the inventive fibers, said yarns and carpets likewise exhibiting improved properties. The invention also provides methods of improving various physical properties (such as fire resistance, spinnability, and elongation) of a polymeric composition.

Abstract: Provided is a method of reducing the incidence of defects caused by die drool or die drips on extruded polymeric products such as films and sheets. The method includes the step of directing a flow of gas towards the die. The flow of gas is substantially parallel to one or more surfaces of the extrudate, and the temperature of the gas is about 50° C. to about 300° C. when it impinges on the surface of the die. Moreover, selecting the temperature or flow rate of the gas provides a method of determining the surface roughness of the extruded polymer.

Abstract: The present invention discloses a method for fast fabricating microneedle arrays with an embossing process and a method for fabricating an embossing mold of a microneedle array, wherein a master pattern of a high aspect ratio silicon microneedle array is fabricated with a microelectromechanical technology, and the master pattern is used to fabricate an embossing mold; a thermosetting material is filled into the embossing mold; then, baking, pressing and mold-stripping are undertaken; thereby, disposable solid polymer microneedle arrays can be batch-fabricated.